Method for operating dynamic memory

Abstract

A method for operating a dynamic memory is provided, and the method includes the following steps. A refresh operation is performed on the dynamic memory according to predetermined interval time T, an operation command is received in real time at the same time, a read operation is performed on a selected memory cell according to position information of the selected memory cell in the operation command when the operation command is received, and state data read in the read operation is temporarily stored in a read buffer. The interval time T is less than time t required for a voltage value of a capacitor in the memory cell to drop to a critical capacitor voltage value for the read operation to correctly read the state data of the memory cell during a write operation. According to operation command type information in the operation command, corresponding operations are performed on the selected memory cell.

Claims

1. A method for operating a dynamic memory, wherein the dynamic memory comprises wordlines and bitlines arranged vertically to each other and memory cells arranged in an array between the wordlines and the bitlines, each memory cell comprises a capacitor and a two-terminal gate device connected in series, the two-terminal gate device has bidirectional conduction characteristics and has a conduction threshold voltage V.sub.TH and a holding voltage V.sub.hold, and the method comprises the following steps: (1) performing a refresh operation on the dynamic memory according to predetermined interval time T, receiving an operation command in real time at the same time, performing a read operation on a selected memory cell according to position information of the selected memory cell in the operation command when receiving the operation command, and temporarily storing state data read in the read operation, wherein the interval time T is less than time t required for a voltage value of the capacitor in the memory cell to drop to a critical capacitor voltage value for the read operation to correctly read the state data of the memory cell during a write operation; (2) performing a corresponding operation on the selected memory cell according to operation command type information in the operation command and outputting the temporarily stored data to a corresponding I/O port if a received operation command type is a read operation and then performing step (3), performing step (3) if the received operation command type is a refresh operation, or performing step (4) if the received operation command type is a write operation; (3) performing a write state 1 operation on the selected memory cell, determining the temporarily stored data of the selected memory cell next, and ending the operation if the temporarily stored data is in state 1 or performing a write state 0 operation on the selected memory cell if the temporarily stored data is in state 0; and (4) obtaining operation information of the write operation, and correspondingly performing the write state 1 operation or the write state 0 operation on the selected memory cell according to the obtained operation information of the write operation.

2. The method for operating the dynamic memory according to claim 1, wherein in step (1), the step of performing the read operation on the selected memory cell and temporarily storing the state data read in the read operation specifically comprises: (a) applying a bitline voltage V.sub.BLread on the bitline connected to the selected memory cell and applying a wordline voltage V.sub.Wlread on the wordline connected to the selected memory cell to generate a read voltage of V.sub.read at both ends of the memory cell to be read, wherein the read voltage V.sub.read is configured to keep the two-terminal gate device in the selected memory cell in state 0 to be turned off and to turn on the two-terminal gate device in the selected memory cell in state 1 to change the selected memory cell from state 1 to state 0, and generates a read current; (b) detecting whether a read current is provided on the bitline connected to the selected memory cell and determining that the selected memory cell is in state 1 if a read current is provided and outputting a state 1 signal, otherwise determining that the selected memory cell is in state 0 if a read current is not provided and outputting a state 0 signal; and (c) sending the outputted state signal to a read buffer for temporary data storage.

3. The method for operating the dynamic memory according to claim 2, wherein in step (a), the read voltage V.sub.read satisfies the following relationships: V.sub.read?V.sub.C1>V.sub.TH and V.sub.read?V.sub.C0<V.sub.TH, where V.sub.C1 is the capacitor voltage when the memory cell is in state 1, and V.sub.C0 is the capacitor voltage when the memory cell is in state 0.

4. The method for operating the dynamic memory according to claim 1, wherein performing the write state 1 operation on the selected memory cell is implemented by applying a voltage V.sub.WL1 on the wordline connected to the selected memory cell and applying a voltage V.sub.BL1 on the bitline connected to the selected memory cell to form a voltage difference of V.sub.IN1 at both ends of the selected memory cell, and performing the write state 0 operation on the selected memory cell is implemented by applying a voltage V.sub.WL0 on the wordline connected to the selected memory cell and applying a voltage V.sub.BL0 on the bitline connected to the selected memory cell to form a voltage difference of V.sub.IN0 at both ends of the selected memory cell, the voltage difference V.sub.IN1 and the voltage difference V.sub.IN0 satisfy the following relationships:
V.sub.IN1=V.sub.BL1?V.sub.WL1, V.sub.IN0=V.sub.BL0?V.sub.WL0
|V.sub.IN1|=|V.sub.IN0|
V.sub.TH<|V.sub.IN1|I|V.sub.IN0|<V.sub.TH+V.sub.Hold
|V.sub.IN1|?V.sub.Hold+|V.sub.BL1|<V.sub.TH
|V.sub.IN1?V.sub.Hold+|V.sub.WL1|<V.sub.TH
|V.sub.IN1?V.sub.Hold+|V.sub.BL0|<V.sub.TH
|V.sub.IN1?V.sub.Hold+|V.sub.WL0|<V.sub.TH
|V.sub.IN1?V.sub.Hold+|V.sub.BLread|<V.sub.TH
|V.sub.IN1?V.sub.Hold+|V.sub.WLread|<V.sub.TH.

5. The method for operating the dynamic memory according to claim 4, wherein the interval time T is less than the time t required for the capacitor voltage in the memory cell to drop from ?V.sub.IN|?V.sub.Hold| to V.sub.read?V.sub.TH, and V|.sub.IN|=|V.sub.IN1|=|V.sub.IN0|.

6. The method for operating the dynamic memory according to claim 1, wherein step (4) specifically comprises: directly performing the write state 1 operation on the selected memory cell when the operation information of the write operation is a write state 1; and performing the write state 1 operation on the selected memory cell first and performing the write state 0 operation on the selected memory cell next when the operation information of the write operation is a write state 0.

7. The method for operating the dynamic memory according to claim 1, wherein the position information of the selected memory cell in the operation command comprises bitwise, entire row, entire column, or matrix position information.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a schematic flow chart of a method for operating a dynamic memory provided by an embodiment of the disclosure.

(2) FIG. 2 and FIG. 3 correspond to functional block diagrams of a method for a dynamic memory bitwise operation and a method for a dynamic memory entire row operation provided by an embodiment of the disclosure.

(3) FIG. 4 and FIG. 5 correspond to graphs of applying a 4.5V read voltage to selected memory cells in state 1 and state 0 provided by an embodiment of the disclosure.

(4) FIG. 6 is a graph of applying?4.5V write 1 voltage to the selected memory cell in state 0 provided by an embodiment of the disclosure.

(5) FIG. 7 is a graph of applying 4.5V write 0 voltage to the selected memory cell in state 1 provided by an embodiment of the disclosure.

(6) FIG. 8 is a voltage graph of a refresh operation for the selected memory cell in state 0 provided by an embodiment of the disclosure.

DESCRIPTION OF THE EMBODIMENTS

(7) In order to make the objectives, technical solutions, and advantages of the disclosure clearer and more comprehensible, the disclosure is further described in detail with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein serve to explain the disclosure merely and are not used to limit the disclosure.

(8) In order to ensure that the capacitor leakage in a memory cell does not affect the read and write operations of the memory cell, the disclosure provides a method for operating a dynamic memory. The applicable dynamic memory includes wordlines and bitlines arranged vertically to each other and memory cells arranged in an array between the wordlines and the bitlines. Herein, each memory cell includes a capacitor and a two-terminal gate device connected in series. The two-terminal gate device has bidirectional conduction characteristics and has a conduction threshold voltage V.sub.TH and a holding voltage V.sub.hold.

(9) FIG. 1 is a flow chart of a method for operating a dynamic memory provided by an embodiment of the disclosure. As shown in FIG. 1, the method includes the following steps S10 to S40, and the steps are described in detail as follows.

(10) In step S10, a refresh operation is performed on the dynamic memory according to predetermined interval time T, an operation command is received in real time at the same time, a read operation is performed on a selected memory cell according to position information of the selected memory cell in the operation command when the operation command is received, and state data which is read is temporarily stored. Specifically, it may be temporarily stored in a read buffer.

(11) In step S10, the interval time T is less than time t required for a voltage value of a capacitor in the memory cell to drop to a critical capacitor voltage value for the read operation to correctly read the state data of the memory cell during a write operation. Since the voltage of the capacitor in the memory cell may gradually drop due to the leakage effect, when the voltage value of the capacitor drops to the critical capacitor voltage value for correctly reading the state data at this time during the read operation, read and write errors may occur in the subsequent read operation. For instance, when the current write state of the memory cell is 1 and the voltage value of the capacitor in the memory cell at this time is V.sub.1, if leakage occurs in the capacitor in the memory cell at this time, the voltage of the capacitor may gradually drop from V.sub.1. When the read operation correctly reads state 1, the voltage of the capacitor must be between V.sub.2 to V.sub.3 (V.sub.3 is greater than V.sub.2). As such, the memory cell needs to be refreshed before the capacitor voltage drops from V.sub.1 to V.sub.2 to ensure that the subsequent read operation reads state data errors. In the same way, the situation when the memory cell is in write state 0 may be known, and description thereof is not provided in this embodiment.

(12) The operation command provided in this embodiment includes the position information of the selected memory cell and an operation command type, and the operation command type includes a read operation, a write operation, and a refresh operation. The position information of the selected memory cell includes bitwise, entire row, entire column, or matrix position information. That is, the position information of the wordline and the bitline where the selected memory cell is located is configured to perform read and write operations on the memory cells in the dynamic memory correspondingly bitwise, by entire row, by entire column, and by matrix. For instance, when it is necessary to perform bitwise read and write operations on memory cells in the dynamic memory, it is only necessary to obtain information about the memory cells to be operated, that is, the information of the wordlines and bitlines where the memory cells are located. Based on this information, corresponding operations may then be performed according to the operation method provided by this embodiment. When it is necessary to perform read and write operations on the entire row of memory cells in the dynamic memory, only the wordline and bitline information of the row of memory cells is required. Based on this information, corresponding operations may then be performed according to the operation method provided by this embodiment. In the same way, it can be known how to implement the read and write operations of the entire column and matrix, and description thereof is not provided in this embodiment.

(13) In this embodiment, the dynamic memory will only work after receiving an operation command. Further, after receiving the operation command, the dynamic memory may immediately read the selected memory cell and sends the current state data of the selected memory cell to the read buffer for temporary storage, so as to correctly perform a write operation on the memory cell through the state data temporarily stored in the read buffer during the subsequent write operation. After the data is temporarily stored, the next operation is performed according to the operation command type the operation command, such as the following step S20.

(14) In S20, a corresponding operation is performed on the selected memory cell according to the operation command type information in the operation command, and the temporarily stored data in the read buffer is outputted to a corresponding I/O port if the received operation command type is a read operation and step S30 is then performed, step S30 is performed if the received operation command type is a refresh operation, or step S40 is performed if the received operation command type is a write operation.

(15) In S30, a write state 1 operation is performed on the selected memory cell, the temporarily stored data of the selected memory cell in the read buffer is determined next, and the operation is ended if the temporarily stored data is in state 1, or a write state 0 operation is performed on the selected memory cell if the temporarily stored data is in state 0.

(16) In steps S20 and S30, after each read operation, a refresh operation execution step is performed. This is because the refresh operation execution step is to rewrite the data of the selected memory cell temporarily stored in the read buffer, so as to facilitate the correct write operation of the memory cell through the state data temporarily stored in the read buffer during the subsequent write operation.

(17) In S40, operation information of the write operation is obtained, and according to the operation information of the write operation, the write state 1 operation or the write state 0 operation is correspondingly performed on the selected memory cell. Herein, the operation information of the write operation includes the write state 1 operation and the write state 0 operation. When the operation information of the write operation is the write state 1, the write state 1 operation may be directly performed on the selected memory cell. When the operation information of the write operation is the write state 0, the write state 1 operation is performed on the selected memory cell first and the write state 0 operation is performed on the selected memory cell next.

(18) In the method for operating the dynamic memory provided by this embodiment, it is set to perform an interval refresh operation on the selected memory cell according to the time T. Further, the interval time T is less than the time t required for the voltage value of the capacitor in the memory cell to drop to the critical capacitor voltage value for the read operation to correctly read the state data of the memory cell during the write operation. In this way, even if leakage occurs in the capacitor in the memory cell, it can effectively ensure that the read operation can always correctly read the state data of the memory cell. In addition, when an operation command is received, it is set to immediately perform a read operation on the selected memory cell and temporarily store the state data. Further, a refresh operation execution step (rewriting the temporarily stored data to the memory cell) is performed after each read operation. In this way, it can effectively ensure that the state data of the memory cell is correctly written in the subsequent write operation.

(19) In an embodiment, the implementation of the read operation provided in this embodiment can be accomplished by applying specific voltages on the wordline and the bitline connected to the selected memory cell, and the specific steps are provided as follows:

(20) In step 1, a bitline voltage V.sub.BLread is applied on the bitline connected to the selected memory cell and a wordline voltage V.sub.Wlread is applied on the wordline connected to the selected memory cell to generate a read voltage of V.sub.read at both ends of the memory cell to be read. The read voltage V.sub.read is configured to keep the two-terminal gate device in the selected memory cell in state 0 to be turned off and to turn on the two-terminal gate device in the selected memory cell in state 1 to change the selected memory cell from state 1 to state 0, and generates a read current. That is, the read voltage V.sub.read satisfies the following relationships: V.sub.read?V.sub.C1>V.sub.TH and V.sub.read?V.sub.C0<V.sub.TH, where V.sub.C1 is the capacitor voltage when the memory cell is in state 1, and V.sub.C0 is the capacitor voltage when the memory cell is in state 0.

(21) In step 2, it is detected whether a read current is provided on the bitline connected to the selected memory cell, and it is determined that the selected memory cell is in state 1 if a read current is provided and a state 1 signal is outputted, otherwise it is determined that the selected memory cell is in state 0 if a read current is not provided and a state 0 signal is outputted. After the read operation, the selected memory cells are all in state 0, and then proceed to the next step according to the received operation command type, such as the above step S20.

(22) In step 3, the outputted state signal is sent to a read buffer for temporary data storage.

(23) In an embodiment, performing the write state 1 operation on the selected memory cell may be implemented by applying a voltage V.sub.WL1 on the wordline connected to the selected memory cell and applying a voltage V.sub.BL1 on the bitline connected to the selected memory cell to form a voltage difference of V.sub.IN1=V.sub.BL1?V.sub.WL1 at both ends of the selected memory cell.

(24) Performing the write state 0 operation on the selected memory cell may be implemented by applying a voltage V.sub.WL0 on the wordline connected to the selected memory cell and applying a voltage V.sub.BL0 on the bitline connected to the selected memory cell to form a voltage difference of V.sub.IN0=V.sub.BL0?V.sub.WL0 at both ends of the selected memory cell.

(25) Herein, V.sub.IN1 and V.sub.IN0 are two voltage pulses with the same amplitude and opposite polarities, namely |V.sub.IN1=|V.sub.IN0|. In order to write data normally, it is necessary to satisfy the relationship: V.sub.TH<|V.sub.IN1|=|V.sub.IN0|<V.sub.TH+V.sub.Hold. The principle is provided as follows. When an operating voltage pulse VII with an amplitude between V.sub.TH and V.sub.TH+V.sub.Hold is applied to both ends of the memory cell, the initial impedance state of the gate transistor is a high-impedance state, the voltage on the capacitor is 0V, the applied voltage pulse V.sub.IN1 is completely added to the gate transistor, and its amplitude is greater than V.sub.TH. In this way, the gate transistor is switched from a high-impedance state to a low-impedance state, the capacitor is quickly charged, and as the capacitor voltage rises, the voltage at both ends of the gate transistor drops. When the voltage across the gate transistor drops below V.sub.Hold, the gate transistor is switched from a low-impedance state to a high-impedance state, and the capacitor voltage is maintained at V.sub.IN1?V.sub.Hold at this time. After the operating voltage V.sub.IN1 is applied, the capacitor voltage V.sub.IN1?V.sub.Hold is less than V.sub.TH, the gate transistor remains in a high-impedance state, the capacitor voltage remains at V.sub.IN1?V.sub.Hold, and the writing of the logic state 1 is completed. For the writing principle of the logic state 0, reference may be made to the abovementioned writing principle of the logic state 1, which is not going to be described in detail in this embodiment. The difference between the two is that the operating voltage pulses V.sub.IN0 and V.sub.IN1 have the same amplitude and opposite polarities, and the capacitor voltage has the same amplitude and opposite polarity as the capacitor voltage in the logic state 0, which is ??V.sub.IN0|?V.sub.Hold|.

(26) According to the principle of writing state 1 and writing state 0 of the memory cell provided in this embodiment, it can be known that no matter whether it is writing state 1 or writing state 0, the voltage value across the capacitor in the memory cell at this time is ?V.sub.IN|?V.sub.Hold| and |V.sub.IN|=|V.sub.IN1|=|V.sub.IN0|. Therefore, in this write operation mode, the interval time T of the refresh operation provided by the disclosure shall be less than the time t required for the capacitor voltage in the memory cell to drop from ?V.sub.IN|?V.sub.Hold| to V.sub.read?V.sub.TH.

(27) At the same time, in order to ensure that the voltage applied on the wordline and bitline may not affect the storage state of a half-selected cell (a memory cell that shares the same wordline or bitline as the selected memory cell) and a unselected memory cell (a memory cells that share neither a wordline nor a bitline with the selected memory cell) when the read and write operations are performed on the selected memory cell, V.sub.BL1, V.sub.WL1, V.sub.BL0, and V.sub.WL0 need to satisfy the following relationships:
|V.sub.IN1|?V.sub.Hold+|V.sub.BL1|<V.sub.TH
|V.sub.IN1|?V.sub.Hold+|V.sub.WL1|<V.sub.TH
|V.sub.IN1|?V.sub.Hold+|V.sub.BL0|<V.sub.TH
|V.sub.IN1|?V.sub.Hold+|V.sub.WL0|<V.sub.TH
|V.sub.IN1|?V.sub.Hold+|V.sub.BLread|<V.sub.TH
|V.sub.IN1?V.sub.Hold+|V.sub.WLread|<V.sub.TH.

(28) Herein, V.sub.TH represents the conduction threshold voltage of a two-terminal gate transistor device of the dynamic memory, V.sub.Hold represents the holding voltage of the two-terminal gate transistor device in the dynamic memory, V.sub.BL1 represents the voltage applied to the bitline connected to the selected memory cell when being in writing state 1, V.sub.WL1 represents the voltage applied on the wordline connected to the selected memory cell when being in writing state 1, V.sub.BL0 represents the voltage applied on the bitline connected to the selected memory cell when being in writing state 0, V.sub.WL0 represents the voltage applied on the wordline connected to the selected memory cell when being in writing state 0, V.sub.BLread represents the voltage applied on the bitline connected to the selected memory cell during the read operation, V.sub.Wlread represents the voltage applied on the wordline connected to the selected memory cell during the read operation, the capacitor voltage fluctuation range in the selected memory cell in state 1 is: ??V.sub.IN1?V.sub.Hold| to V.sub.read?V.sub.TH, and the capacitor voltage of the capacitor voltage in the selected memory cell in state 0 is: V.sub.read?V.sub.TH to ?V.sub.IN1?V.sub.Hold|.

(29) |V.sub.IN1?V.sub.Hold is the capacitor voltage amplitude after the state writing is completed. Because there is leakage in the capacitor, the capacitor voltage after the state writing is completed may gradually decrease over time, so the maximum voltage across the capacitor is |V.sub.IN1?V.sub.Hold. Therefore, it is only necessary to ensure that the half-selected cell whose capacitor voltage is |V.sub.IN1?V.sub.Hold is not affected when the memory cell is read and written. That is, the voltage across the gate transistor corresponding to the half-selected cell is always less than the threshold voltage V.sub.TH, that is, V.sub.BL1, V.sub.WL1, V.sub.BL0, V.sub.WL0, V.sub.BLread, V.sub.Wlread plus |V.sub.IN1?V.sub.Hold is less than V.sub.TH.

(30) In order to illustrate the disclosure more clearly, the disclosure is described below in together with specific embodiments.

(31) A 1S1C memory is provided, where the selected threshold voltage Vth of the gate transistor is 4V, and the holding voltage V.sub.hold is 3V.
V.sub.IN1=?4.5V,V.sub.BL1=?2.5V,V.sub.WL1=2V
V.sub.IN0=4.5V,V.sub.BL0=2.5V,V.sub.WL0=?2V
V.sub.read=4.5V,V.sub.BLread=2.5V,V.sub.WLread=?2V

(32) The capacitor voltage in state 1 is: ?1.5V to 0.5V, and the capacitor voltage in state 0 is: 0.5V to 1.5V.

(33) As shown in FIG. 2, a method for a dynamic memory bitwise operation is provided.

(34) When an operation command is received, a read operation is immediately performed on the selected memory cell, that is, V.sub.read=4.5V is applied to the selected memory cell. For the selected memory cell in state 1, as shown in FIG. 4, the applied bitline voltage (see reference numeral 31 in FIG. 4) is 2.5V, and the applied wordline voltage (see reference numeral 32 in FIG. 4) is ?2V. In this way, the voltage across the gate transistor device in the memory cell is greater than 4V. The gate transistor device is turned on to generate a read current (see reference numeral 34 in FIG. 4), and the capacitor voltage (see reference numeral 33 in FIG. 4) may change from ?1V to 1.5V, that is, it is in state 0. For the selected memory cell in state 0, as shown in FIG. 5, the applied bitline voltage (see reference numeral 41 in FIG. 5) is 2.5V, and the applied wordline voltage (see reference numeral 42 in FIG. 5) is ?2V. In this way, the voltage across the gate transistor device is less than 4V. The gate transistor is turned off, no read current is generated (see reference numeral 44 in FIG. 5), and the capacitor voltage (see reference numeral 43 in FIG. 5) is maintained at 1.4V. By monitoring whether there is a read current in the bitline, the state of the selected memory cell can be determined, and the data obtained after reading may be temporarily stored in the read buffer. After the read operation, the memory cell is in state 0.

(35) If the type of the received operation command is a refresh operation, V.sub.IN1=?4.5V is applied to the memory cell. As shown in FIG. 6, the applied bitline voltage (see reference numeral 52 in FIG. 6) is ?2.5V, and the applied wordline voltage (see reference numeral 51 in FIG. 6) is 2V. Because the current memory cell is in state 0, the voltage across the gate transistor is greater than 4V, the gate transistor may be turned on, the capacitor voltage (see reference numeral 53 in FIG. 6) in the memory cell becomes ?1.5V, and the writing of state 1 is completed. At this time, the state of the data in the read buffer is determined. If it is state 1, the operation ends, and if it is state 0, V.sub.IN0=4.5V is applied to the memory cell. As shown in FIG. 7, the applied bitline voltage (see reference numeral 61 in FIG. 7) is ?2.5V, and the applied wordline voltage (see reference numeral 62 in FIG. 7) is 2V. Because the current memory cell is in state 1, the voltage across the gate transistor is greater than 4V, the gate transistor may be turned on, the capacitor voltage (see reference numeral 63 in FIG. 7) in the memory cell becomes 1.5V, the writing of state 0 is completed, and the operation is ended.

(36) If the received operation command is a read operation, the data temporarily stored in the read buffer is output to the I/O port, and then the refresh operation is performed to complete the write-back of the memory cell data.

(37) If the received operation command is a write 1 operation, V.sub.IN1=?4.5V is applied to the memory cell. As shown in FIG. 6, the applied bitline voltage (see reference numeral 52 in FIG. 6) is ?2.5V, and the applied wordline voltage (see reference numeral 51 in FIG. 6) is 2V. Because the current memory cell is in state 0, the voltage across the gate transistor is greater than 4V, the gate transistor may be turned on, the capacitor voltage (see reference numeral 53 in FIG. 6) of the memory cell becomes ?1.5V, and the writing of state 1 is completed.

(38) If the received operation command is a write 0 operation, V.sub.IN1=?4.5V is applied to the memory cell first. As shown in FIG. 6, the applied bitline voltage (see reference numeral 52 in FIG. 6) is ?2.5V, and the applied wordline voltage (see reference numeral 51 in FIG. 6) is 2V. Because the current memory cell is in state 0, the voltage across the gate transistor is greater than 4V, the gate transistor may be turned on, the capacitor voltage 53 of the memory cell becomes ?1.5V, and the writing of state 1 is completed. V.sub.IN0=4.5V is applied to the memory cell next. As shown in FIG. 7, the applied bitline voltage (see reference numeral 61 in FIG. 7) is ?2.5V, and the applied wordline voltage (see reference numeral 62 in FIG. 7) is 2V. Because the current memory cell is in state 1, the voltage across the gate transistor is greater than 4V, the gate transistor may be turned on, the capacitor voltage (see reference numeral 63 in FIG. 7) in the memory cell becomes 1.5V, the writing of state 0 is completed, and the operation is ended.

(39) As shown in FIG. 3, a method for operating an entire row of a dynamic memory is provided.

(40) When an operation command is received, V.sub.read=4.5V is applied to the entire row of memory cells, that is, a voltage V.sub.Wlread=?2V is applied to the wordline shared by the entire row of memory cells and a voltage V.sub.BLread=2.5V is applied to the bitline connected to each memory cell. For the memory cell in state 1, as shown in FIG. 4, the voltage across the gate transistor is greater than 4V, the gate transistor is turned on, and a read current (see reference numeral 34 in FIG. 4) is generated, and the capacitor voltage (see reference numeral 33 in FIG. 4) becomes 1.5V, that is, it is in state 0. For the memory cell in state 0, as shown in FIG. 5, the voltage across the gate transistor is less than 4V, the gate transistor is turned off, no read current (see reference numeral 44 in FIG. 5) is generated, and the capacitor voltage (see reference numeral 43 in FIG. 5) remains stable. By monitoring whether there is a read current in the bitline, the state of the corresponding memory cell can be determined, and the data obtained after reading may be temporarily stored in the read buffer of the entire row. After the read operation, the entire row of memory cells is in state 0.

(41) If the received operation command is a refresh operation, V.sub.IN1=?4.5V is applied to the entire row of memory cells, as shown in FIG. 6. That is, a voltage V.sub.WL1=2V is applied to the wordline shared by the entire row of memory cells and a voltage V.sub.BL1=?2.5V is applied to the bitline connected to each memory cell. Because the entire row of memory cells is currently in state 0, so the voltage across the gate transistor is greater than 4V, and the gate transistor may be turned on, so that the entire row of memory cells is in state 1. It is then determined whether the temporarily stored data of each bit is state 1 or state 0 in the row read buffer, if the state is 1, the operation can be ended, and if the state is 0, V.sub.IN0=4.5V is then applied to the corresponding memory cell, as shown in FIG. 7. That is, a voltage V.sub.WL0=?2V is applied to the word line shared by the entire row of memory cells, and a voltage V.sub.BL0=2.5V is applied to the bitline connected to the memory cells that need to be written to 0. When the voltage across the gate transistor of the corresponding memory cell is greater than 4V, the gate transistor may be turned on, and the writing of state 0 is completed.

(42) If the received operation command is a write operation, V.sub.IN1=?4.5V is applied to the entire row of memory cells, as shown in FIG. 6. That is, a voltage V.sub.WL1=2V is applied to the wordline shared by the entire row of memory cells and a voltage V.sub.BL1=?2.5V is applied to the bitline connected to each memory cell. Because the entire row of memory cells is currently in state 0, so the voltage across the gate transistor is greater than 4V, and the gate transistor may be turned on, so that the entire row of memory cells is in state 1. According to the operation command, which memory cells need to be written into state 0 is determined, and V.sub.IN0=4.5V is applied to the corresponding memory cells, as shown in FIG. 7. That is, a voltage V.sub.WL0=?2V is applied to the word line shared by the entire row of memory cells, and a voltage V.sub.BL0=2.5V is applied to the bitline connected to the memory cells that need to be written to 0. When the voltage across the gate transistor of the corresponding memory cell is greater than 4V, the gate transistor may be turned on, and the writing of state 0 is completed.

(43) As shown in FIG. 8, a logic state 0 operation is performed on the memory cell, a write pulse V.sub.IN0=4.5V is applied, and it can be seen that the capacitor voltage remains near 1.5V after the write is completed. Since then, due to the leakage phenomenon of the capacitor, the capacitor voltage gradually decreases from 1.5V over time and drops to 0.5V at time t, and the capacitor voltage corresponding to the logic state 0 is: 0.5V to 1.5V. If it continues to drop, the logic state stored in the memory cell may change from 0 to 1, that is, an error occurs in the stored data. Therefore, it is necessary to perform a refresh operation on the memory cell before the capacitor voltage drops to 0.5V to rewrite data. Therefore, it is necessary to refresh the data stored in the memory cell every interval time T. The interval time T is less than the time t required for the capacitor voltage to drop from the highest value to the lowest value due to the leakage of the capacitor in the memory cell, that is, it is less than the time t required for the voltage value of the capacitor in the memory cell to drop to the critical capacitor voltage value for the read operation to correctly read the state data of the memory cell during the write operation.

(44) In the disclosure, even if leakage occurs in the capacitor in the selected memory cell, the normal operation of the read and write operations performed on this memory cell is effectively ensured

(45) A person having ordinary skill in the art should be able to easily understand that the above description is only preferred embodiments of the disclosure and is not intended to limit the disclosure. Any modifications, equivalent replacements, and modifications made without departing from the spirit and principles of the disclosure should fall within the protection scope of the disclosure.