Secure starting of an electronic circuit

Abstract

A method of checking the authenticity of the content of a non-volatile memory of an electronic device including a microcontroller and an embedded secure element includes starting the microcontroller with instructions stored in a first non-reprogrammable memory area associated with the microcontroller, starting the secure element, executing, with the secure element, a signature verification on the content of a second reprogrammable non-volatile memory area associated with the microcontroller, and if the signature is verified, using the secure element to send the first key to the microcontroller.

Claims

1. A method to check authenticity of content in a non-volatile memory of an electronic device, the electronic device having a microcontroller and an embedded secure element, the method comprising: starting the microcontroller with first instructions stored in a first non-reprogrammable memory area of the non-volatile memory associated with the microcontroller, wherein the first non-reprogrammable memory area has been programmed one time with start-up program instructions; starting the secure element, the secure element containing a first key arranged to decipher content in a second reprogrammable area of the non-volatile memory associated with the microcontroller; executing, with the secure element, a signature verification on the content in the second reprogrammable area; in response to a determination that the signature is verified, sending, with the secure element, the first key to the microcontroller; generating a second key with the microcontroller; transmitting the second key to the secure element; using the second key in a ciphering operation of the first key prior to sending the first key to the microcontroller; and based on an authenticated update of content in a reprogrammable memory area of the non-volatile memory, modifying a second signature stored in the secure element.

2. The method of claim 1, wherein the second key is arranged according to a public key asymmetric algorithm.

3. The method of claim 2, wherein the asymmetric ciphering key is unique for every microcontroller/secure element pair.

4. The method of claim 1, wherein the first key is not stored in either of the first non-reprogrammable memory area or the second reprogrammable memory area.

5. The method of claim 1, further comprising: waiting, by the microcontroller, for a response from the secure element before executing instructions stored in the second area.

6. The method of claim 1, further comprising: based on an authenticated update of the content in the second reprogrammable memory area, modifying a signature stored in the secure element.

7. The method of claim 1, wherein the first key is generated by the secure element.

8. The method of claim 1, comprising: if the signature is not verified, interrupting a power supply of the microcontroller.

9. An electronic device, comprising: a microcontroller to execute start-up program instructions; an embedded secure element; and a non-volatile memory organized with a first non-reprogrammable area and a second reprogrammable area, the first non-reprogrammable area having the start-up program instructions stored one time therein, wherein the start-up program instructions are arranged to direct the microcontroller to: initiate an authentication function in the secure element, the authentication function configured to decipher content in the second reprogrammable area using a first key stored in the secure element, the authentication function further configured to verify a signature formed based on content stored in the second reprogrammable area; generate a second key; transmit the second key to the secure element; and receive the first key from the secure element after the signature is verified, wherein the received first key has been ciphered using the second key, wherein based on an authenticated update of content in a reprogrammable memory area of the non-volatile memory, a signature stored in the secure element is modified.

10. The electronic device of claim 9, further comprising: an intermediate circuit interposed between the microcontroller and the secure element, the intermediate circuit structured to receive control information from the microcontroller via a first communication path, and the intermediate circuit structured to pass the control information to the secure element via a second communication path.

11. The electronic device of claim 10, wherein the intermediate circuit is a wireless communications circuit.

12. The electronic device of claim 10, wherein the intermediate circuit includes a near-field communication (NFC) controller.

13. The electronic device of claim 9, further comprising: a switch circuit arranged to force a reset of the microcontroller if the signature is not verified.

14. The electronic device of claim 9, wherein the electronic device is a mobile device.

15. A method performed by a secure element, comprising: receiving a first direction from a microcontroller to initiate a boot sequence, wherein the microcontroller is coupled to a non-volatile memory, the non-volatile memory organized with a first non-reprogrammable area and a second reprogrammable area, and wherein a set of start-up program instructions programmed one time in the first non-reprogrammable memory area causes transmission of the first direction; receiving from the microcontroller a ciphered first security key generated by the microcontroller; deciphering the first security key; deciphering a portion of a non-volatile memory associated with the microcontroller using the first security key; calculating a first signature of the deciphered portion of the non-volatile memory; in response to a determination that the first signature is valid, sending a ciphered second security key to the microcontroller; and based on an authenticated update of content in a reprogrammable memory area of the non-volatile memory, modifying a second signature stored in the secure element.

16. The method of claim 15, further comprising: if the first signature is determined to be invalid, forcing the microcontroller to reset.

17. The method of claim 16, further comprising: after initiating the boot sequence, waiting for the ciphered first security key for a determined period of time; and if the determined period of time is exceeded, forcing the microcontroller to reset.

18. The method of claim 15, wherein the first and second security keys are arranged according to a public key asymmetric algorithm, and wherein the second security key is unique for every microcontroller/secure element pair.

19. The method of claim 15, wherein the method is performed in a secure element embedded in a mobile device.

Description

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

(1) Non-limiting and non-exhaustive embodiments are described with reference to the following drawings, wherein like labels refer to like parts throughout the various views unless otherwise specified. One or more embodiments are described hereinafter with reference to the accompanying drawings in which:

(2) FIG. 1 is a very simplified representation in the form of blocks of an embodiment of an electronic device equipped with a microcontroller and with an embedded secure element;

(3) FIG. 2 is a simplified representation illustrating an embodiment of a start-up sequence of the microcontroller of the electronic device of FIG. 1; and

(4) FIG. 3 is a simplified representation illustrating another embodiment of a start-up sequence of the microcontroller of the electronic device of FIG. 1.

DETAILED DESCRIPTION

(5) The same elements have been designated with the same reference numerals in the different drawings.

(6) For clarity, only those steps and elements which are useful to the understanding of the embodiments which will be described have been shown and will be detailed. In particular, the applications of the electronic device have not been detailed, the described embodiments being compatible with usual applications of such devices. Further, protocols of signal exchange between the different elements of the electronic device have not been detailed either, the described embodiment being, here again, compatible with currently-used protocols. In the following description, when reference is made to terms approximately, about, and in the order of, this means to within 10%, preferably to within 5%.

(7) FIG. 1 very schematically shows, in the form of blocks, an example of an electronic device 1 of the type to which the embodiments which will be described apply.

(8) Device 1, for example, a cell phone, an electronic key, etc., comprises a microcontroller 2 (CPUCentral Processing Unit) in charge of controlling all or part of the programs and applications executed in the device. Microcontroller 2 communicates, via one or a plurality of address, data, and control buses 12, with different electronic circuits and peripherals (not shown) of device 1, for example, display control circuits, of a keyboard, etc., as well as with various wired or wireless input-output interfaces 14 (I/O) (for example, Bluetooth). Microcontroller 2 generally integrates volatile and non-volatile memories and also processes the content of similar memories 16 (MEM (VM/NVM)) of device 1. Microcontroller 2 and various circuits of device 1 are powered by a power unit 18 (PU). For example, unit 18 is a battery, possibly associated with a voltage regulator.

(9) In applications targeted by the present disclosure, device 1 further comprises an embedded secure element 3 (for example, eSEembedded Secure Element or eUICCembedded Universal Integrated Circuit Card) which includes a secure microprocessor. Element 3 is intended to contain the secure services or applications of the electronic device, for example, payment, access control, and other applications.

(10) Possibly, an intermediate element or circuit 4, for example, a near-field communication controller 4 (NFC), also called contactless front end (CLF), a Bluetooth controller, etc., equips device 1. Element 4 (illustrated in dotted lines in FIG. 1) is capable of being used by microcontroller 2, for example by connections of twin-wire type (I2C or SPI) and, by element 3, by a connection of single-wire type (SWPSingle Wire Protocol).

(11) According to the voltage level withstood by secure element 3, said element is either powered by unit 18 or, as shown in FIG. 1, by element 4, which is itself powered by unit 18. For example, the case of a microcontroller 2 and of a contactless communication controller 4 powered under a voltage in the order of 3 volts by unit 18 and of an element 3 powered under a voltage in the order of 1.8 volt (PWR) by controller 4 can be considered. The need for a power supply by NFC controller 4 may be due to the levels used by the communication protocols between the controller and secure element 3.

(12) It is provided to take advantage of the presence of embedded secure element 3 to check the authenticity of the content (data, instructions, etc.) of all or part of the memories associated with microcontroller 2.

(13) FIG. 2 is a simplified representation illustrating an embodiment of a start-up sequence of microcontroller 2 of electronic device 1 of FIG. 1.

(14) Risks inherent to the starting of microcontroller 2 in terms of data security are that, in the case where the microcontroller code (program) is pirated, the data of the embedded secure element risk being pirated. This risk occurs at the start, called cold boot, which follows a powering-on since not all the mechanisms for controlling the access to the different circuits have been initialized yet and, in particular, the configuration of the memories in free areas and reserved areas. The problem is not as critical in the case of a hot reset of the device, that is, with no interruption of the microcontroller power supply, since such memory area configuration mechanisms are generally untouched. However, the described embodiment may also be implemented in case of a partial or total deleting of the memory on reset.

(15) At a starting (powering-on of the electronic circuits of the device) or a reset with an interruption of the power supply, microcontroller 2 starts by accessing a set area 51 (BOOT) of its non-volatile memory containing a code (a start-up program). Area 51 generally is a read-only memory area, that is, non-volatile and non-reprogrammable (sometimes called immutable). It is thus set on manufacturing and does not risk being modified by a possible pirate. Indeed, the memory areas 52 (MEMCPU) which should be protected are non-volatile memory areas which will be exploited by microcontroller 2 when applications will need accessing element 3. Such areas 52 also contain code (instructions) and data, which are reprogrammable according to applications. If a pirate succeeds in storing an attack code in these areas, he/she risks being able to access secure element 3.

(16) The start-up code 51 executed by the microcontroller contain an instruction for starting secure element 3 (i.e., a function, Fn(BOOT) of eSE) as well as, subsequently in the sequencing of the initialization process (illustrated by an arrow 53), an instruction INST for starting a process of checking or verification of the content of area 52 by element 3. Once instruction INST is communicated by microcontroller 2 to element 3, microcontroller 2 sets to a hold mode (HOLD) where it waits for a response from secure element 3. As long as it does not receive this response, it does not carry on the execution of the code that it contains.

(17) The checking CHECK performed by element 3 comprises reading all or part of area 52 and executing an authenticity check mechanism. For example, this mechanism is a signature calculation based on the code and data contained in area 52, and for checking this signature against a reference signature stored in element 3. In this case, in case of an authorized modification of the content of area 52, the reference signature stored in element 3 is updated to allow subsequent authenticity checks.

(18) If element 3 validates the authenticity of the content of area 52, it responds (OK) to microcontroller 2. The latter can then leave its hold mode and execute the rest of the initialization based on the content of area 52.

(19) However, if element 3 does not validate (NOK) the content of area 52, it causes, via a switch K interposed on the power supply line of microcontroller 2, an interruption of this power supply. This then forces the microcontroller to be restarted and the above-described steps are repeated. If the error originates from a transient malfunction, the next execution validates the starting. However, if the code contained in area 52 effectively poses a problem (be it after an attack or after a memory problem), microcontroller 2 will successively start, for example, until battery 18 is out or endlessly as long as device 1 is connected, but without ever passing start phase BOOT.

(20) Preferably, at the starting of element 3 (Fn(BOOT) eSE), the latter monitors the arrival of a request (instruction INST) originating from microcontroller 2. In the case where this request does not arrive after a certain time, determined relatively to the usual time between the start and the arrival or request INST (for example, in the order of some hundred milliseconds), element 3 causes the interruption of the power supply of microcontroller 2. This provides additional security in case of a disturbance of start program BOOT of the microcontroller.

(21) FIG. 3 is a simplified representation illustrating another embodiment of a start-up sequence of the microcontroller of the electronic device of FIG. 1.

(22) According to this embodiment, everything is performed by exchange of messages between microcontroller 2 and secure element 3, without necessarily acting on (interrupting) the microcontroller power supply.

(23) The starting of microcontroller 2 and of secure element 3 is caused in the same way as in the previous embodiment, that is, at the starting (block 61, BOOT CPU) of microcontroller 2, the latter cases the starting (block 62, BOOT eSE) of secure element 3. Once it has started, element 3 sets to a mode where it waits for an instruction (WAIT).

(24) Further, the checking of the content of area 52 or of the non-volatile memory areas (NVM) containing code to be checked is also performed, preferably, by a signature check by element 3.

(25) According to the embodiment of FIG. 3, the code and the fixed data, stored in non-volatile memory 52 and forming the data of initialization of microcontroller 2 after the starting thereof, are ciphered. The ciphering used is for example a symmetrical AES-type ciphering. However, instead of being stored in microcontroller 2, the ciphering key is stored in secure element 3.

(26) Once microcontroller 2 has started (end of block 61) and it has given a start instruction to element 3, it generates a key (block 63, GEN KeyAESRDM), preferably a random number of the size of the AES used to cipher the code.

(27) Microcontroller 2 then transmits key KeyAESRDM to the secure element. Preferably, this transmission is performed by a public key mechanism, the microcontroller ciphering key KeyAESRDM with the public key of the algorithm (block 64, CIPHER KeyAESRDM (PUBLIC KEY)). Preferably, microcontroller 2 does not store random number KeyAESRDM in the non-volatile memory. Indeed, it is sufficient for it to store this number in the volatile memory, which decreases risks of attack. Once key KeyAESRDM has been transmitted, the microcontroller sets to the waiting mode (WAIT).

(28) Element 3 deciphers KeyAESRDM by means of the public key mechanism (block 65, DECIPHER KeyAESRDM)) and stores it (block 66, STORE KeyAESRDM).

(29) Element 3 then deciphers (block 67, DECIPHER CODE (AESCodeKey) the code contained in area 52 of the non-volatile memory of microcontroller 2 (or associated therewith) and calculates and checks (block 68, COMPUTE/CHECK SIGNATURE) the code signature.

(30) If the signature is incorrect (output N of block 69, OK?), element 3 does not respond to microcontroller 2 and the operation thereof is stopped (STOP).

(31) If the signature is correct (output Y of block 69), element 3 ciphers key AESCodeKey with key KeyAESRDM (block 70, CIPHER AESCodeKey (KeyAESRDM)) and sends it to microcontroller 2. The latter deciphers key AESCodeKey (block 71, DECIPHER AESCodeKey (PUBLIC KEY)) with key KeyAESRDM.

(32) Microcontroller 2 then uses key AESCodeKey to decipher the code contained in area 52 and to execute it (EXECUTE). However, key AESCodeKey is not stored in the non-volatile memory by microcontroller 2. Thus, on the side of microcontroller 2, number KeyAESRDM and key AESCodeKey are only stored in volatile storage elements (RAM, registers, or the like).

(33) According to an alternative embodiment, key AESCodeKey is generated by secure element 3 for each change of signature of the code contained in area 52, that is, each time this code is modified.

(34) According to another variation, on manufacturing of the circuits (of microcontroller 2 and of secure element 3), the ciphering code of memory 52 of the microcontroller is generated by secure element 3. This means that code AESCodeKey varies from one device 1 to another.

(35) Preferably, the asymmetric key (pair of public and private key) is unique per pair of microcontroller component 2/secure element 3.

(36) It should be noted that the two embodiments and their respective variations may be combined. For example, in case of an authentication failure according to the second embodiment (output N of block 69, FIG. 3), it may be provided for the secure element to interrupt the microcontroller power supply according to the embodiment described in relation with FIG. 2.

(37) Various embodiments have been described. Various modifications will occur to those skilled in the art. In particular, the selection of the memory areas having a content to be checked depends on the application and may vary. Further, the selection of the data exchange ciphering processes between the secure element and the microcontroller also depends on applications. Further, the practical implementation of the embodiments which have been described is within the abilities of those skilled in the art by using on the functional indications given hereabove.

(38) Such alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the spirit and the scope of the present invention. Accordingly, the foregoing description is by way of example only and is not intended to be limiting. The present invention is limited only as defined in the following claims and the equivalents thereto.

(39) The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.