Envelope tracking power amplifier circuit

Abstract

An envelope tracking (ET) power amplifier circuit is disclosed. The ET power amplifier circuit includes ET tracker circuitry configured to output an ET modulated output voltage having an output voltage envelope that tracks a target voltage envelope of an ET modulated target voltage. Impedance adjustment circuitry in the ET power amplifier circuit is provided between a first node and a second node coupled to a feedback voltage input and a voltage output of the ET tracker circuitry, respectively. A power amplifier circuit(s) includes a first amplifier and a second amplifier coupled respectively to the first node and the second node. As such, it is possible to configure the impedance adjustment circuitry to provide adjustment impedance to offset output impedance of the ET tracker circuitry, thus helping to reduce voltage error in the ET power amplifier circuit.

Claims

1. An envelope tracking (ET) power amplifier circuit, comprising: ET tracker circuitry having an output impedance and configured to receive an ET modulated target voltage having a target voltage envelope at a voltage input and generate an ET modulated output voltage having an output voltage envelope tracking the target voltage envelope at a voltage output; impedance adjustment circuitry comprising a first node coupled to a feedback voltage input of the ET tracker circuitry and a second node coupled to the voltage output, the impedance adjustment circuitry configured to provide an adjustment impedance between the first node and the second node; and at least one power amplifier circuit comprising: a first amplifier comprising a first voltage input coupled to the first node of the impedance adjustment circuitry; and a second amplifier comprising a second voltage input coupled to the second node of the impedance adjustment circuitry.

2. The ET power amplifier circuit of claim 1 wherein: the output impedance of the ET tracker circuitry causes a voltage error between the output voltage envelope and the target voltage envelope; and the impedance adjustment circuitry is further configured to provide the adjustment impedance to offset the output impedance of the ET tracker circuitry to reduce the voltage error between the output voltage envelope and the target voltage envelope.

3. The ET power amplifier circuit of claim 2 wherein the impedance adjustment circuitry is further configured to provide the adjustment impedance to offset at least ninety percent of the output impedance.

4. The ET power amplifier circuit of claim 1 wherein the output impedance is determined by an output inductance of the ET tracker circuitry.

5. The ET power amplifier circuit of claim 4 wherein the impedance adjustment circuitry comprises at least one inductor configured to generate an adjustment inductance to offset the output inductance of the ET tracker circuitry.

6. The ET power amplifier circuit of claim 5 wherein: the first amplifier is configured to receive a first ET modulated supply voltage from the first node; and the second amplifier is configured to receive a second ET modulated supply voltage from the second node.

7. The ET power amplifier circuit of claim 6 wherein the second ET modulated supply voltage is greater than the first ET modulated supply voltage.

8. The ET power amplifier circuit of claim 6 wherein: the first amplifier is configured to receive a radio frequency (RF) signal at a first signal input and output the RF signal at a first signal output; and the second amplifier is configured to receive the RF signal at a second signal input coupled to the first signal output and output the RF signal at a second signal output.

9. The ET power amplifier circuit of claim 6 wherein: the first ET modulated supply voltage induces a first current in the first amplifier; the second ET modulated supply voltage induces a second current in the second amplifier; and the second current equals the first current multiplied by a current ratio greater than one.

10. The ET power amplifier circuit of claim 9 wherein the impedance adjustment circuitry is further configured to generate the adjustment inductance varying in proportion to the output inductance and the current ratio.

11. The ET power amplifier circuit of claim 10 wherein the adjustment inductance generated by the at least one inductor in the impedance adjustment circuitry equals the output inductance plus a multiplication of the output inductance and the current ratio.

12. The ET power amplifier circuit of claim 1 wherein the at least one power amplifier circuit comprises a first power amplifier circuit having a first current ratio and a second power amplifier circuit having a second current ratio greater than the first current ratio.

13. The ET power amplifier circuit of claim 12 wherein the impedance adjustment circuitry comprises a first inductor and a second inductor provided in a serial arrangement between the first node and the second node, the first inductor is provided between the first node and an intermediate node, and the second inductor is coupled between the intermediate node and the second node.

14. The ET power amplifier circuit of claim 13 wherein the first power amplifier circuit comprises a respective first amplifier having a respective first voltage input coupled to the intermediate node and a respective second amplifier having a respective second voltage input coupled to the second node.

15. The ET power amplifier circuit of claim 13 wherein the first power amplifier circuit comprises a respective first amplifier having a respective first voltage input coupled to the first node and a respective second amplifier having a respective second voltage input coupled to the second node.

16. The ET power amplifier circuit of claim 1 wherein the at least one power amplifier circuit is a differential power amplifier circuit comprising a plus amplifier and a minus amplifier.

17. The ET power amplifier circuit of claim 16 wherein the plus amplifier and the minus amplifier are provided in parallel between a first voltage node coupled to the first node and a second voltage node coupled to the second node.

18. The ET power amplifier circuit of claim 16 wherein: the plus amplifier has a plus supply voltage input coupled to the second node; and the minus amplifier has a minus supply voltage input coupled to the first node.

19. The ET power amplifier circuit of claim 18 wherein: the output impedance is determined by an output inductance of the ET tracker circuitry; and the impedance adjustment circuitry comprises at least one inductor configured to generate an adjustment inductance to offset the output inductance of the ET tracker circuitry.

20. The ET power amplifier circuit of claim 19 wherein the adjustment inductance equals four times the output inductance.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The accompanying drawings incorporated in and forming a part of this specification illustrate several aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.

(2) FIG. 1A is a schematic diagram of a conventional envelope tracking (ET) power amplifier circuit including ET tracker circuitry configured to generate an ET modulated output voltage based on an ET modulated target voltage;

(3) FIG. 1B is a schematic diagram showing that an output impedance of an ET tracker circuitry in the ET power amplifier circuit of FIG. 1A can be modeled by an output inductance;

(4) FIG. 2 is a schematic diagram of an exemplary ET power amplifier circuit configured to reduce output impedance in the conventional ET power amplifier circuit of FIG. 1A to help reduce a voltage error between the ET modulated output voltage and the ET modulated target voltage;

(5) FIG. 3 is a schematic diagram of an exemplary ET power amplifier circuit configured to support a first power amplifier circuit and a second power amplifier circuit with different current ratios;

(6) FIG. 4 is a schematic diagram of an exemplary ET power amplifier circuit including a differential power amplifier circuit; and

(7) FIG. 5 is a schematic diagram of an exemplary ET power amplifier circuit including the ET tracker circuitry of FIG. 2 and a differential power amplifier circuit according to a different configuration from the differential power amplifier circuit of FIG. 4.

DETAILED DESCRIPTION

(8) The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

(9) It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term and/or includes any and all combinations of one or more of the associated listed items.

(10) It will be understood that when an element such as a layer, region, or substrate is referred to as being on or extending onto another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being directly on or extending directly onto another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being over or extending over another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being directly over or extending directly over another element, there are no intervening elements present. It will also be understood that when an element is referred to as being connected or coupled to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being directly connected or directly coupled to another element, there are no intervening elements present.

(11) Relative terms such as below or above or upper or lower or horizontal or vertical may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.

(12) The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms a, an, and the are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms comprises, comprising, includes, and/or including when used herein specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

(13) Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

(14) Aspects disclosed in the detailed description include an envelope tracking (ET) power amplifier circuit. The ET power amplifier circuit includes ET tracker circuitry configured to output an ET modulated output voltage having an output voltage envelope that tracks a target voltage envelope of an ET modulated target voltage. In examples discussed herein, the ET tracker circuitry has an output impedance that can cause a voltage error between the output voltage envelope and the target voltage envelope, thus compromising performance of the ET power amplifier circuit. Impedance adjustment circuitry in the ET power amplifier circuit is provided between a first node and a second node coupled to a feedback voltage input and a voltage output of the ET tracker circuitry, respectively. A power amplifier circuit(s) includes a first amplifier and a second amplifier coupled respectively to the first node and the second node. As such, it is possible to configure the impedance adjustment circuitry to provide adjustment impedance to offset the output impedance of the ET tracker circuitry, thus helping to reduce the voltage error in the ET power amplifier circuit.

(15) Before discussing the ET power amplifier circuit of the present disclosure, a brief discussion of a conventional ET power amplifier circuit and potential issues related to the conventional RF power amplifier circuit are first provided with reference to FIGS. 1A-1B. The discussion of specific exemplary aspects of an ET power amplifier circuit starts below with reference to FIG. 2.

(16) FIG. 1A is a schematic diagram of a conventional ET power amplifier circuit 10 including ET tracker circuitry 12 configured to generate an ET modulated output voltage V.sub.CC based on an ET modulated target voltage V.sub.TARGET. The ET tracker circuitry 12 includes at least one ET tracker 14 having a voltage input 16, a voltage output 18, and a feedback voltage input 20. The ET tracker 14 is configured to receive the ET modulated target voltage V.sub.TARGET at the voltage input 16 and generate the ET modulated output voltage V.sub.CC at the voltage output 18 based on the ET modulated target voltage V.sub.TARGET. The ET modulated target voltage V.sub.TARGET is modulated according to a target voltage envelope 22. The ET modulated output voltage V.sub.CC is modulated according to an output voltage envelope 24 that tracks the target voltage envelope 22. The ET tracker 14 includes a feedback path 26 configured to provide a feedback voltage V.sub.CCFB, which may be a snapshot or mirrored copy of the ET modulated output voltage V.sub.CC, from the voltage output 18 to the feedback voltage input 20. The ET tracker 14 is configured to compare the feedback voltage V.sub.CCFB against the ET modulated target voltage V.sub.TARGET and adjust the ET modulated target voltage V.sub.TARGET accordingly. The ET tracker 14 has an output end 28 coupled to the voltage output 18 via an offset capacitor 30. The offset capacitor 30 is configured to raise an ET modulated voltage at the output end 28 to the ET modulated output voltage V.sub.CC at the voltage output 18.

(17) The conventional ET power amplifier circuit 10 includes at least one power amplifier circuit 32. The power amplifier circuit 32 includes a first amplifier 34 and a second amplifier 36. The first amplifier 34 includes a first signal input 38 and a first signal output 40. The second amplifier 36 includes a second signal input 42 and a second signal output 44. In a non-limiting example, the power amplifier circuit 32 is configured to be a serial power amplifier circuit. In this regard, the first signal output 40 of the first amplifier 34 is coupled to the second signal input 42 of the second amplifier 36. Accordingly, the first amplifier 34 functions as a driver stage amplifier and the second amplifier 36 functions as an output stage amplifier. The first amplifier 34 receives a radio frequency (RF) signal 46 at the first signal input 38 and outputs the RF signal 46 at the first signal output 40. The second amplifier 36, in turn, receives the RF signal 46 at the second signal input 42 and outputs the RF signal 46 at the second signal output 44.

(18) The first amplifier 34 has a first supply voltage input 48 coupled to the voltage output 18 to receive the ET modulated output voltage V.sub.CC as a first ET modulated supply voltage V.sub.CC1. The first ET modulated supply voltage V.sub.CC1 induces a first current I.sub.STAGE1 flowing through the first amplifier 34. The second amplifier 36 has a second supply voltage input 50 also coupled to the voltage output 18 to receive the ET modulated output voltage V.sub.CC as a second ET modulated supply voltage V.sub.CC2. The second ET modulated supply voltage V.sub.CC2 induces a second current I.sub.STAGE2 flowing through the second amplifier 36. A sum of the first current I.sub.STAGE1 and the second current I.sub.STAGE2 equals a current I.sub.SUM generated by the ET tracker 14. The first current I.sub.STAGE1 and the second current I.sub.STAGE2 determine a current ratio K, which can be expressed in equation (Eq. 1) below. In a non-limiting example, the current ratio K is greater than one (1), an indication that the second current I.sub.STAGE2 is greater than the first current I.sub.STAGE1.
K=I.sub.STAGE2/I.sub.STAGE1(Eq. 1)

(19) The ET tracker circuitry 12 has inherent impedance, which can present at the voltage output 18 as output impedance Z.sub.OUT. If not properly controlled, the output impedance Z.sub.OUT can cause a voltage error V.sub.ERROR between the target voltage envelope 22 and the output voltage envelope 24. As a result, the ET modulated voltage V.sub.CC at the voltage output 18 may deviate from the target voltage V.sub.TARGET, thus compromising RF performance of the conventional ET power amplifier circuit 10. Notably, the output impedance Z.sub.OUT tends to increase with modulation frequency. In this regard, when the conventional ET power amplifier circuit 10 is used to support such advanced wireless communication technologies as fifth-generation new radio (5G-NR), which typically operate in millimeter wave frequency spectrums, the voltage error V.sub.ERROR caused by the output impedance Z.sub.OUT may become more severe and acute. Hence, it may be desired to suppress the output impedance Z.sub.OUT to help reduce the voltage error V.sub.ERROR and thus improve the RF performance of the conventional ET power amplifier circuit 10, especially for supporting the 5G-NR technologies.

(20) In a non-limiting example, the output impedance Z.sub.OUT can be modeled as being primarily determined by an output inductance I.sub.ZOUT, as shown in FIG. 1B. FIG. 1B is a schematic diagram showing that the output impedance Z.sub.OUT of the ET tracker circuitry 12 of FIG. 1A can be modeled by the output inductance L.sub.ZOUT. Impact of the output inductance L.sub.ZOUT on the ET modulated output voltage V.sub.CC can be expressed in equation (Eq. 2) below.
V.sub.CC=V.sub.TARGETL.sub.ZOUT*dI.sub.SUM/dt
=V.sub.TARGETL.sub.ZOUT*d(I.sub.STAGE1+I.sub.STAGE2)/dt(Eq. 2)

(21) As shown in equation (Eq. 2) above, the output inductance L.sub.ZOUT contributes to the voltage error V.sub.ERROR between the ET modulated target voltage V.sub.TARGET and the ET modulated output voltage V.sub.CC. Thus, to reduce the voltage error V.sub.ERROR, it is necessary to reduce the output inductance L.sub.ZOUT of the ET tracker circuitry 12.

(22) In this regard, FIG. 2 is a schematic diagram of an exemplary ET power amplifier circuit 52 configured to reduce the output impedance Z.sub.OUT in the conventional ET power amplifier circuit 10 of FIG. 1A to help reduce the voltage error V.sub.ERROR between the ET modulated output voltage V.sub.CC and the ET modulated target voltage V.sub.TARGET. In a non-limiting example, the ET power amplifier circuit 52 can be created based on the conventional ET power amplifier circuit 10 with minimum hardware changes to save cost and provide backward compatibility. As such, the ET power amplifier circuit 52 reuses many of the components and/or circuitries in the conventional ET power amplifier circuit 10. Common elements between FIGS. 1A and 2 are shown therein with common element numbers and will not be re-described herein.

(23) The ET power amplifier circuit 52 includes impedance adjustment circuitry 54 having a first node 56 and a second node 58. The first node 56 is coupled to the feedback voltage input 20 and the second node 58 is coupled to the voltage output 18. The impedance adjustment circuitry 54 is configured to provide adjustment impedance Z.sub.ADJ between the first node 56 and the second node 58 to offset the output impedance Z.sub.OUT of the ET tracker circuitry 12 and thus to reduce the voltage error V.sub.ERROR between the ET modulated output voltage V.sub.CC and the ET modulate target voltage V.sub.TARGET.

(24) In the power amplifier circuit 32, the first supply voltage input 48 of the first amplifier 34 is coupled to the first node 56 of the impedance adjustment circuitry 54. The second supply voltage input 50 of the second amplifier 36 is coupled to the second node 58 of the impedance adjustment circuitry 54 and thus the voltage output 18.

(25) As previously discussed in FIGS. 1A and 1B, the output impedance Z.sub.OUT of the ET tracker circuitry 12 can be modeled by the output inductance L.sub.ZOUT. In this regard, for the impedance adjustment circuitry 54 to offset the output impedance Z.sub.OUT, the impedance adjustment circuitry 54 should be configured to offset the output inductance L.sub.ZOUT of the ET tracker circuitry 12. As such, in a non-limiting example, the impedance adjustment circuitry 54 includes at least one inductor 60 configured to generate an adjustment inductance L.sub.ADJ to offset the output inductance L.sub.ZOUT of the ET tracker circuitry 12.

(26) As is discussed in details below, the adjustment inductance L.sub.ADJ can be determined and configured to vary in proportion to the output inductance L.sub.ZOUT and the current ratio K between the second current I.sub.STAGE2 and the first current I.sub.STAGE1. Thus, by controlling the adjustment inductance L.sub.ADJ of the impedance adjustment circuitry 54 based on the output inductance L.sub.ZOUT and the current ratio K, it is possible to offset the output inductance L.sub.ZOUT and thus the output impedance Z.sub.OUT to help reduce the voltage error V.sub.ERROR. As a result, the ET power amplifier circuit 52 can support 5G-NR technologies in the millimeter wave frequency spectrums without compromising the RF performance.

(27) In the power amplifier circuit 32, the first amplifier 34 receives the first ET modulated supply voltage V.sub.CC1 from the first node 56 and the second amplifier 36 receives the second ET modulated supply voltage V.sub.CC2 from the second node 58. Since the second node 58 is coupled to the voltage output 18, the second ET modulated supply voltage V.sub.CC2 equals the ET modulated output voltage V.sub.CC. The relationship between the first ET modulated supply voltage V.sub.CC1 and the second ET modulated supply voltage V.sub.CC2 can be expressed by equation (Eq. 3) below.
V.sub.CC2=V.sub.CC1+L.sub.ADJ*d(I.sub.STAGE1)/dt(Eq. 3)

(28) As shown in equation (Eq. 3), the second ET modulated supply voltage V.sub.CC2 is greater than the first ET modulated supply voltage V.sub.CC1. Further, according to equation (Eq. 1), I.sub.STAGE1 can be expressed as I.sub.STAGE2/K. As such, the second ET modulated supply voltage V.sub.CC2 can be further expressed in equation (Eq. 4) below.
V.sub.CC2=V.sub.TARGET+V.sub.ERROR+(L.sub.ADJ/K)*d(I.sub.STAGE2)/dt(Eq. 4)

(29) The voltage error V.sub.ERROR, in the meantime, can be expressed in equation (Eq. 5) below.
V.sub.ERROR=L.sub.ZOUT*d(I.sub.SUM)/dt
=L.sub.ZOUT*d(I.sub.STAGE1+I.sub.STAGE2)/dt
=L.sub.ZOUT*(1/K+1)*d(I.sub.STAGE2)/dt(Eq. 5)

(30) Accordingly, the second ET modulated supply voltage V.sub.CC2 can be further expressed in equation (Eq. 6) below.
V.sub.CC2=V.sub.TARGETL.sub.ZOUT*(1/K+1)*d(I.sub.STAGE2)/dt+(L.sub.ADJ/K)*d(I.sub.STAGE2)/dt
=V.sub.TARGET[L.sub.ZOUT*(1/K+1)L.sub.ADJ/K]*d(I.sub.STAGE2)/dt(Eq. 6)

(31) Thus, to offset the output inductance L.sub.ZOUT and thus the output impedance Z.sub.OUT, it is necessary for L.sub.ZOUT*(1/K+1)L.sub.ADJ/K to be to zero. Accordingly, it is possible to determine the adjustment inductance L.sub.ADJ according to equation (Eq. 7) below.
L.sub.ADJ=(1+K)*L.sub.ZOUT(Eq. 7)

(32) The equation (Eq. 7) above shows that the adjustment induction L.sub.ADJ is proportionally related to the output inductance L.sub.ZOUT and the current ratio K. For example, if the output inductance L.sub.ZOUT is 1 nH and K equals 4, the adjustment inductance L.sub.ADJ of the inductor 60 can be determined based on equation (Eq. 7) as being 5 nH. As a result, the adjustment inductance L.sub.ADJ can substantially offset (e.g., at least 90%) the output inductance L.sub.ZOUT and thus the output impedance Z.sub.OUT to significantly reduce the voltage error V.sub.ERROR.

(33) Notably, the ET power amplifier circuit 52 can be configured to support more than one power amplifier circuit having different current ratios K. Hence, it may be necessary to vary the adjustment inductance L.sub.ADJ in accordance to equation (Eq. 7) for the different current ratios K. In this regard, FIG. 3 is a schematic diagram of an exemplary ET power amplifier circuit 52A configured to support a first power amplifier circuit 32A with a first current ratio K.sub.1 and a second power amplifier circuit 32B with a second current ratio K.sub.2. Common elements between FIGS. 2 and 3 are shown therein with common element numbers and will not be re-described herein.

(34) The ET power amplifier circuit 52A includes ET tracker circuitry 12A that has the output inductance L.sub.ZOUT equivalent to the output inductance L.sub.ZOUT of the ET tracker circuitry 12 of FIG. 2. In a non-limiting example, the second current ratio K.sub.2 of the second power amplifier circuit 32B is greater than the first current ratio K.sub.1 of the first power amplifier circuit 32A. Thus, according to equation (Eq. 7), it would require a higher adjustment inductance L.sub.ADJ to offset the output inductance L.sub.ZOUT for the second power amplifier circuit 32B. As such, in a non-limiting example, the ET power amplifier circuit 52A includes impedance adjustment circuitry 54A. The impedance adjustment circuitry 54A includes a first inductor 62 and a second inductor 64 provided in a serial arrangement between the first node 56 and the second node 58. More specifically, the first inductor 62 is provided between the first node 56 and an intermediate node 66 and the second inductor 64 is provided between the intermediate node 66 and the second node 58.

(35) The first power amplifier circuit 32A, which has the first current ratio K.sub.1 smaller than the second current ratio K.sub.2, includes a respective first amplifier 34A and a respective second amplifier 36A. The respective first amplifier 34A has a respective first voltage input 48A coupled to the intermediate node 66. The respective second amplifier 36A has a respective second voltage input 50A coupled to the second node 58. As such, the second inductor 64 provides the adjustment inductance L.sub.ADJ to offset the output inductance L.sub.ZOUT for the first power amplifier circuit 32A. Notably, inductance of the second inductor 64 can be so determined based on the first current ratio K.sub.1 and in accordance to equation (Eq. 7).

(36) The second power amplifier circuit 32B includes a respective first amplifier 34B and a respective second amplifier 36B. The respective first amplifier 34B has a respective first voltage input 48B coupled to the first node 56. The respective second amplifier 36B has a respective second voltage input 50B coupled to the second node 58. As such, the first inductor 62 and the second inductor 64 provide the adjustment inductance L.sub.ADJ to offset the output inductance L.sub.ZOUT for the second power amplifier circuit 32B. Notably, inductances of the first inductor 62 and the second inductor 64 can be so determined based on the second current ratio K.sub.2 and in accordance to equation (Eq. 7).

(37) The ET tracker circuitry 12A includes a mux 68. The mux 68 is configured to selectively provide the feedback voltage V.sub.CCFB from the intermediate node 66 when the first power amplifier circuit 32A is in use or from the first node 56 when the second power amplifier circuit 32B is in use.

(38) The impedance adjustment circuitry 54 of FIG. 2 can be further configured to offset the output inductance L.sub.ZOUT of the ET tracker circuitry 12 when the power amplifier circuit 32 is provided as a differential power amplifier circuit. In this regard, FIG. 4 is a schematic diagram of an exemplary ET power amplifier circuit 52B including the ET tracker circuitry 12 of FIG. 2 and a differential power amplifier circuit 70. Common elements between FIGS. 2 and 4 are shown therein with common element numbers and will not be re-described herein.

(39) The differential power amplifier circuit 70 includes a plus amplifier 72P and a minus amplifier 72M. The plus amplifier 72P has a plus supply voltage input 74P coupled to the second node 58 to receive a plus ET modulated supply voltage V.sub.CCP. The minus amplifier 72M has a minus supply voltage input 74M coupled to the first node 56 to receive a minus ET modulated supply voltage V.sub.CCM. The plus ET modulated supply voltage V.sub.CCP creates a plus current I.sub.STAGE.sub._.sub.P in the plus amplifier 72P. Likewise, the minus ET modulated supply voltage V.sub.CCM creates a minus current I.sub.STAGE.sub._.sub.M in the minus amplifier 72M.

(40) Assuming that the plus current I.sub.STAGE.sub._.sub.P equals the minus current I.sub.STAGE.sub._.sub.M and further equals the second current I.sub.STAGE2 as previously shown in FIG. 2, the plus ET modulated supply voltage V.sub.CCP and the minus ET modulated supply voltage V.sub.CCM can be expressed in equation (Eq. 8) below.
V.sub.CCM=V.sub.TARGETL.sub.ZOUT*d(2*I.sub.STAGE2)/dt
V.sub.CCP=V.sub.TARGETL.sub.ZOUT*d(2*I.sub.STAGE2)/dt+L.sub.ADJ*d(I.sub.STAGE2)/dt(Eq. 8)

(41) If the adjustment inductance L.sub.ADJ is selected to equal four times the output inductance L.sub.ZOUT, then the equation (Eq. 8) can be rewritten as equation (Eq. 8.1) below.
V.sub.CCM=V.sub.TARGET2*L.sub.ZOUT*d(I.sub.STAGE2)/dt
V.sub.CCP=V.sub.TARGET+2*L.sub.ZOUT*d(I.sub.STAGE2)/dt(Eq. 8.1)

(42) As shown in equation (Eq. 8.1), the output inductance L.sub.ZOUT will induce an opposite ripple on the minus ET modulated supply voltage V.sub.CCM and the plus ET modulated supply voltage V.sub.CCP. The opposite ripple will cancel out at an RF output 76, thus helping to reduce the voltage error V.sub.ERROR.

(43) FIG. 5 is a schematic diagram of an exemplary ET power amplifier circuit 52C including the ET tracker circuitry 12 of FIG. 2 and a differential power amplifier circuit 78 according to a different configuration from the differential power amplifier circuit 70 of FIG. 4. Common elements between FIGS. 2, 4, and 5 are shown therein with common element numbers and will not be re-described herein.

(44) As shown in FIG. 5, the plus amplifier 72P and the minus amplifier 72M are provided in parallel between a first voltage node 80 coupled to the second node 58 and a second voltage node 82 coupled to the first node 56.

(45) Those skilled in the art will recognize improvements and modifications to the embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.