OPTOELECTRONIC ARRANGEMENT AND METHOD FOR PRODUCING AN OPTOELECTRONIC ARRANGEMENT

Abstract

An optoelectronic arrangement is specified, including a moulded body having a base surface, a first pixel group with a multiplicity of pixels assigned thereto, each having a first semiconductor region, a second semiconductor region and an active region, a multiplicity of separating structures arranged between the pixels, and at least one first contact structure having a first contact plane and a first contact location, which is freely accessible at the base surface, wherein the pixels of the first pixel group are arranged alongside one another at the top surface, the first semiconductor regions and/or the second semiconductor regions of adjacent pixels of the first pixel group are electrically insulated from one another by means of the separating structures, a first contact structure is assigned one-to-one to the first pixel group, and the first semiconductor regions of the pixels of the first pixel group are electrically conductively connected to one another by means of the first contact plane and are electrically contactable by means of the first contact location.

Claims

1. A method for producing an optoelectronic arrangement, comprising the following steps: providing a semiconductor layer sequence comprising a first semiconductor layer, a second semiconductor layer and an active layer on a growth substrate, producing separating structures and pixels by removing the semiconductor layer sequence in some locations using an etching process such that the pixels are spatially separated in pixels of a first pixel group and pixel of a second pixel group, producing an electrical insulating body at a side of the semiconductor layer sequence facing away from the growth substrate, and detaching the growth substrate.

2. The method according to claim 1, wherein applying the electrical insulating body and detaching the growth substrate are carried out before producing the separating structure and the pixels.

3. The method according to claim 1, wherein the electrical insulating body is applied by a potting method.

4. The method according to claim 1, wherein the electrical insulating body is produced at a side of the semiconductor layer sequence facing away from the growth substrate.

5. The method according to claim 1, wherein trenches are produced in the semiconductor layer sequence, which trenches form the separating structures between the pixels.

6. The method according to claim 1,wherein the pixels of the first pixel group are arranged alongside one another at a top surface of the optoelectronic arrangement, and the first semiconductor regions and/or the second semiconductor regions of adjacent pixels of the first pixel group are spatially separated from one another by the separating structures.

7. The method according to claim 1, wherein before the production of the electrical insulating body, a first contact structure and a second contact structure are deposited onto the semiconductor layer sequence.

8. The method according to claim 7, wherein the first contact structure has a first contact plane, a first plated-through hole extending through the electrical insulating body and a first contact location, which is freely accessible at a bottom surface of the electrical insulating body facing away from a top surface.

9. The method according to claim 8, wherein the first contact plane is directly connected to the first plated-through hole.

10. The method according to claim 8, wherein the first semiconductor regions of the pixels of the first pixel group are electrically conductively connected to one another exclusively by the first contact plane and are electrically contactable by the first contact location.

11. The method according to claim 1, wherein the first semiconductor regions and the active regions of adjacent pixels are spatially completely separated from one another by the separating structures, and the second semiconductor regions of adjacent pixels are connected to one another via intermediate regions formed with the material of the second semiconductor regions.

12. The method according to claim 1, wherein each pixel is individually drivable.

13. The method according to claim 1, wherein the electrical insulating body is a mechanically stabilizing component of the arrangement.

Description

[0055] The optoelectronic arrangement described here and the method for producing an optoelectronic arrangement described here are explained in greater detail below on the basis of exemplary embodiments and the associated figures.

[0056] FIGS. 1A, 1B, and 1C show exemplary embodiments of optoelectronic arrangements described here on the basis of schematic plan views and sectional illustrations.

[0057] FIGS. 2A, 2B, 2C, and 2D show exemplary embodiments of optoelectronic arrangements described here on the basis of schematic plan views and sectional illustrations.

[0058] FIG. 3 shows exemplary embodiments of optoelectronic arrangements described here on the basis of schematic plan views and sectional illustrations.

[0059] FIG. 4 shows exemplary embodiments of optoelectronic arrangements described here on the basis of schematic plan views and sectional illustrations.

[0060] FIGS. 5A-5B show exemplary embodiments of optoelectronic arrangements described here on the basis of schematic plan views and sectional illustrations.

[0061] FIGS. 6A-6B show exemplary embodiments of optoelectronic arrangements described here on the basis of schematic plan views and sectional illustrations.

[0062] FIG. 7 shows exemplary embodiments of optoelectronic arrangements described here on the basis of schematic plan views and sectional illustrations.

[0063] FIGS. 8A-8B show an exemplary embodiment of a method for producing an optoelectronic arrangement described here on the basis of schematic sectional illustrations.

[0064] Elements that are identical, of identical type or act identically are provided with the same reference signs in the figures. The figures and the size relationships of the elements illustrated in the figures among one another should not be regarded as to scale. Rather, individual elements may be illustrated with exaggerated size in order to enable better illustration and/or in order to afford a better understanding.

[0065] An exemplary embodiment of an optoelectronic arrangement described here is explained in greater detail on the basis of the schematic sectional illustration in FIG. 1A and the schematic plan views in FIGS. 1B and 1C. The section through the arrangement as illustrated in FIG. 1A is taken along a first sectional line AB. FIG. 1B shows a plan view from above, while FIG. 1C shows a plan view from below. Here and hereinafter, a plan view “from above” denotes a plan view of radiation passage surfaces 1a of the pixels 1 of the optoelectronic arrangement, while a plan view “from below” denotes a plan view of a side of the arrangement facing away from the radiation passage surfaces 1a.

[0066] The optoelectronic arrangement comprises a moulded body 2 having a top surface 2a and a bottom surface 2b facing away from the top surface 2a. The bottom surface 2b is freely accessible. The moulded body 2 serves for mechanically stabilizing the arrangement. The moulded body 2 extends along two lateral directions x, y spanning a main extension plane of the moulded body. The top surface 2a and the bottom surface 2b each form a principal plane of the moulded body.

[0067] A multiplicity of pixels 1 are fitted at the top surface 2a. The pixels 1 are assigned to a first pixel group 41. Furthermore, a second pixel group 42 is assigned to each pixel 1. The optoelectronic arrangement of the exemplary embodiment shown in FIGS. 1A, 1B and 1C comprises – purely by way of example – a single first pixel group 41, wherein all pixels 1 of the arrangement in FIGS. 1A, 1B and 1C are assigned to the first pixel group 41. Each of the second pixel groups 42 is then assigned a single pixel 1.

[0068] Each pixel 1 comprises a first semiconductor region 11, an active region 10 and a second semiconductor region 12. The first semiconductor region 11 can be formed with an n-conducting semiconductor material, for example. The second semiconductor region 12 can be formed with a p-conducting semiconductor material.

[0069] Furthermore, each pixel 1 has the radiation passage surface 1a facing away from the moulded body 2. The second semiconductor region 12 is roughened at the radiation passage surface 1a. The roughenings serve as coupling-out and/or coupling-in structures used to improve the transmission of the electromagnetic radiation through the radiation passage surface 1a.

[0070] Separating structures 3 are situated between two adjacent pixels 1. Side surfaces 1b of the pixels 1 directly adjoin the separating structures 3. In the exemplary embodiment illustrated in FIGS. 1A, 1B and 1C, the separating structures 3 are embodied as trenches, wherein the first semiconductor regions 11, the active regions 10 and the second semiconductor regions 12 are completely separated by the trenches.

[0071] The optoelectronic arrangement comprises a first contact structure 51, 52, 53, which is assigned one-to-one to the first pixel group 41. Furthermore, the arrangement comprises a multiplicity of second contact structures 61, 62, 63, wherein a second contact structure 61, 62, 63 is assigned one-to-one to each of the second pixel groups 42 of the arrangement.

[0072] The first contact structure 51, 52, 53 comprises a first contact plane 51, a second contact location 52 and at least one first plated-through hole 53. The first contact plane 51 is embodied in a continuous fashion. In particular, an outer surface of the first contact plane 51 is embodied in a multiply connected fashion in a plan view from the vertical direction z. The first contact plane 51 is freely accessible within the trenches of the separating structures 3. Alternatively, it is possible for a dielectric to be applied to the first contact plane 51 within the trenches of the separating structures 3. In this case, the first contact plane 51 is not freely accessible in the region of the trenches of the separating structures 3. The first contact plane 51 can be electrically conductively connected to the first semiconductor regions 11 of the pixels 1, and in particular can be in direct contact therewith. By way of example, the first semiconductor regions 11 of the pixels 1 can be at a common electrical potential.

[0073] The first contact plane 51 can be embodied in a radiation-reflecting fashion. The first contact plane 51 can be formed with a metal, such as silver or aluminium, for example, or consist of a metal.

[0074] The first contact plane 51 is electrically conductively connected to the first contact location 52 by means of the first plated-through hole 53. By way of example, the first plated-through hole 53 is formed with the same material as the first contact plane 51. The first plated-through hole 53 can be applied to the first contact plane 51 electrolytically. By way of example, the first plated-through hole 51 may have been electrodeposited in a production method in a method step carried out before the production of the moulded body 2. In particular, the first plated-through hole 53 can extend completely through the moulded body 2 in the vertical direction z.

[0075] The first contact location 52 is freely accessible and in particular electrically contactable at the bottom surface 2b (cf. FIGS. 1A and 1C). The first contact location 52 can be formed with at least one electrically conductive material, such as, for example aluminium, silver, palladium, gold, platinum, titanium, tin, copper or nickel, or consist of at least one of these materials.

[0076] An insulation layer 71 formed with an electrically insulating material, such as silicon nitride or oxide, for example, is fitted between the moulded body 2 and the first contact plane 51 and between the moulded body 2 and the pixels 1. The insulation layer 71 can serve for electrical insulation between the material of the pixels 1, such that an electrical connection is produced only by means of the first contact structure 51, 52 and 53 and the second contact structure 61, 62, 63. In particular, the insulation layer 71 can completely cover the top surface 2a of the moulded body 2 and be in direct contact with the top surface 2a. Furthermore, it is possible for locations of an outer surface of the first semiconductor region 11 facing the moulded body 2 which are not covered by the first contact plane 51 to be covered by the insulation layer 71 and be in direct contact therewith.

[0077] The second contact structure 61, 62, 63 comprises a second contact plane 61, a second contact location 62 and a second plated-through hole 63. The second plated-through hole 63 extends in the vertical direction z completely through the moulded body 2. The second plated-through hole 63 is additionally electrically conductively connected to the second contact location 62. The second contact location 62 is freely accessible and in particular electrically contactable at the bottom surface 2b (cf. FIGS. 1A and 1C).

[0078] In the present case, the second contact plane 61 is likewise embodied as an electrical plated-through hole, wherein the second contact plane 61 proceeding from the second plated-through hole 63 extends through the insulation layer 71, the first semiconductor region 11 and the active region 10 into the second semiconductor region 12 of the pixel 1 assigned to the second plated-through hole 63, The second contact plane 62 and the second plated-through hole 63 can be embodied integrally with one another. The second contact plane 61 can be electrically insulated from the first semiconductor region 11 and the active region 10 by means of a further insulating material (not shown in the figures).

[0079] The first contact plane 51 surrounds the second plated-through holes 63 in each case in a framelike fashion. In other words, in a plan view, the second plated-through holes 63 are enclosed by the first contact plane 51 in the lateral directions x, y at least in some locations, preferably completely. Furthermore, the first plated-through hole 53 is arranged laterally at a distance from one of the second plated-through holes 63.

[0080] The moulded body 2 completely surrounds the first plated-through hole 53 and the second plated-through holes 63 in lateral directions x, y. In particular, the first and second plated-through holes 53, 63 are laterally embedded by the moulded body 2.

[0081] Further exemplary embodiments of an optoelectronic arrangement described here are explained in greater detail on the basis of the schematic plan views in FIGS. 2A, 2B, 2C and 2D. A plan view from above is shown in each case. The exemplary embodiments illustrated may have along the first sectional line AB for example the construction discussed in association with FIG. 1A.

[0082] The optoelectronic arrangements illustrated in FIGS. 2A, 2B, 2C and 2D in each case comprise a multiplicity of pixels 1 which are assigned in each case to at least one first pixel group 41 and at least one second pixel group 42. The pixels 1 are arranged alongside one another in the lateral directions x, y. In this case, the construction of the exemplary embodiments of the optoelectronic arrangement in FIGS. 2A, 2B, 2C and 2D differs as follows.

[0083] In the exemplary embodiment in FIG. 2A, the pixels 1 have the same size and in particular the same extents in the lateral directions x, y. The pixels 1 are arranged in a matrixlike fashion in rows 43 and columns 44. The first contact location 51 extends across a plurality of pixels 1 of a column 44. It is alternatively possible for the arrangement to comprise a plurality of first contact locations 51. In this case, the pixels 1 can be assigned to a plurality of first pixel groups 41, wherein a first contact location 51 is assigned one-to-one to each first pixel group 41.

[0084] The pixels 1 of the exemplary embodiment in FIG. 2B are likewise arranged in a matrixlike fashion, wherein the pixels 1 of different rows 43 of the matrix have different extents in one of the lateral directions x, y.

[0085] In the exemplary embodiment in FIG. 2C, the pixels 1 are arranged in rows, wherein the number of pixels 1 from at least two rows 43 differs and the pixels 1 of different rows 43 have different extents in the lateral directions x, y.

[0086] The pixels 1 of the exemplary embodiment in FIG. 2D have different shapes and different extents in the lateral directions x, y. At least one of the pixels 1 can be embodied in an elliptical fashion, in particular in a circular fashion, in a plan view. The pixels 1 adjoining the elliptical pixels 1 have at least one curved side surface 1b.

[0087] A further exemplary embodiment of an optoelectronic arrangement described here is explained in greater detail on the basis of the schematic plan view from above shown in FIG. 3. The arrangement comprises a multiplicity of pixels 1 which are arranged in a matrixlike fashion in rows 43 and columns 44. Purely by way of example, all pixels 1 are assigned to a single first pixel group 41. The dashed lines between the pixels indicate that the number of rows 43 and columns 44 and in particular the number of pixels 1 can be scaled arbitrarily. In particular, the number of rows 43 and columns 44 can be adapted to the respective technical requirement. All the pixels 1 are applied on the common moulded body 2. The moulded body 2 can project beyond the pixels 1 in the lateral directions x, y.

[0088] A further exemplary embodiment of an optoelectronic arrangement described here is explained in greater detail on the basis of the schematic plan view from above shown in FIG. 4. The pixels 1 of the arrangement are once again arranged in a matrixlike fashion in rows 43 and columns 44. In contrast to the exemplary embodiment shown in FIG. 3, the pixels 1 are assigned to a respective row 43 of a first pixel group 41 and the pixels are assigned to a respective column 44 of a second pixel group. A first pixel group 41 and a second pixel group 42 are assigned to each pixel 1.

[0089] The electrical contacting of the pixels 1 of the first pixel group 41 is effected in each case by means of a first contact structure 51, 52, 53 having in each case a first contact plane 51 and a contact location 52. Furthermore, the electrical contacting of the pixels 1 of the second pixel group 42 is effected in each case by means of a second contact structure 61, 62, 63 having in each case a second contact plane 61 and a second contact location 62. The second semiconductor regions 12 of the pixels 1 of a respective one of the second pixel groups 42 are electrically conductively connected to one another by means of the second contact plane 62 assigned to the second pixel group 42.

[0090] Such a division into first pixel groups 41 assigned to a respective row 43 and second pixel groups 42 assigned to a respective column 44 makes it possible for the pixels 1 to be electrically driven in each case individually by means of a small number of first and second contact locations 52, 62, respectively.

[0091] Further exemplary embodiments of an optoelectronic arrangement described here are explained in greater detail on the basis of the sectional illustrations in FIGS. 5A, 5B, 6A, 6B and 7. The illustrated sections through the arrangement are taken along a second sectional line CD illustrated in FIG. 4, or along a third sectional line C‘D'.

[0092] An electrical contacting of the pixels 1 of one exemplary embodiment of the arrangement described here is explained in greater detail on the basis of the sectional illustration in FIG. 5A running along the third sectional line CD. The separating structures 3 between the pixels 1 are embodied as in the exemplary embodiment shown in FIG. 1A. A second contact structure 61, 62, 63 having a second contact location 62, a second contact plane 61 and at least one second plated-through hole 63 is assigned one-to-one to each second pixel group 42.

[0093] The second semiconductor regions 12 of the pixels 1 of the respective second pixel group 42 are electrically conductively connected to one another by means of the second contact plane 61. In the case of a plurality of pixels 1 per second pixel group 42, the second contact plane 61 can comprise the electrical plated-through hole through the pixels 1 as explained in association with FIG. 1A and can comprise, in addition, an electrically conductive layer embodied in an integral fashion and formed with a metal, for example. The second contact plane 61 can be embodied in a radiation-reflecting fashion at least in some locations. The first semiconductor regions 11 of the pixels 1 can furthermore be electrically conductively connected in each case to further pixels 1 of the first pixel group 41 by means of a plurality of first contact planes 51.

[0094] An electrical contacting of the pixels 1 of an exemplary embodiment of the arrangement described here is explained in greater detail on the basis of the sectional illustration in FIG. 5B running along the third sectional line C'D'. The second semiconductor regions 12 are electrically contacted and connected by means of the second contact structure 61, 62, 63. The construction of the second contact structure 61, 62, 63 corresponds to that in FIG. 5A. The first semiconductor regions 11 are electrically contactable by means of first contact structures 51, 52, 53, wherein a first contact structure 51, 52, 53 is assigned one-to-one to each first pixel group 41. The first plated-through holes 53 of the first contact structures 51, 52, 53 are in each case arranged laterally at a distance from the second plated-through holes 63 of the second contact structure 61, 62, 63.

[0095] A further exemplary embodiment of the arrangement described here is explained in greater detail on the basis of the sectional illustration in FIG. 6A taken along the second sectional line CD and the sectional illustration in FIG. 6B taken along the third sectional line C'D'. In contrast to the exemplary embodiments described in association with FIGS. 1A, 5A and 5B, only the first semiconductor regions 11 and the active regions 12 of adjacent pixels 1 are completely separated from one another by the separating structures 3 embodied as trenches. The second semiconductor regions 12 are connected to one another via intermediate regions 31. The moulded body 2 extends into the separating structures 3 embodied as trenches. The separating structures 3 are thus formed by the moulded body 2. Furthermore, the insulation layer 71 is arranged partly in the trenches of the separating structures 3. Such an embodiment of the separating structures 3 is possible for all exemplary embodiments of the optoelectronic arrangement described here.

[0096] A further exemplary embodiment of the arrangement described here is explained in greater detail on the basis of the sectional illustration in FIG. 7 taken along the second sectional line CD. The exemplary embodiment shown substantially corresponds to that in FIG. 6A, wherein the separating structures 3 are now formed by a degenerate semiconductor material 32. By way of example, for this purpose, regions of the first semiconductor layer 111 are backsputtered in a production method. The backsputtering can be carried out for example by means of a treatment of the first semiconductor layer with a plasma, such as, for example, an argon plasma, a hydrogen plasma and/or an oxygen plasma. The treatment results in an at least partial destruction of the conductivity of the material of the first semiconductor layer 111 and thus a redoping to form the degenerate semiconductor material 32. The degenerate semiconductor material 32 is embodied in particular in a non-conducting fashion.

[0097] Exemplary embodiments of a method for producing an optoelectronic arrangement described here are explained in greater detail on the basis of the schematic sectional illustrations in FIGS. 8A and 8B. In the first method step in FIG. 8A, a semiconductor layer sequence 111, 101, 121, comprising a first semiconductor layer 111, an active layer 101 and a second semiconductor layer 121, is provided on a growth substrate 8. The moulded body 2 has already been produced at a side of the semiconductor layer sequence 111, 101, 121 facing away from the growth substrate 8. Before the production of the moulded body 2, a first contact structure 51, 52, 53 and a second contact structure 61, 62, 63 can be deposited onto the semiconductor layer sequence 111, 101, 121 for example by electrodeposition.

[0098] In the method step illustrated in FIG. 8B, the growth substrate 8 is detached. Separating structures 3 have been introduced into the semiconductor layer sequence 111, 101, 121 by means of etching. In particular, introducing separating structures 3 can be carried out after applying the moulded body 2.

[0099] As an alternative to the method shown in FIGS. 8A and 8B, producing the moulded body 2 can also be carried out after structuring the pixels 1. The growth substrate 8 is then detached after the pixels 1 have been produced.

[0100] The present application claims the priority of the German application DE 102015111574.3 the disclosure content of which is hereby incorporated by reference.

[0101] The invention is not restricted to the exemplary embodiments by the description on the basis of said exemplary embodiments. Rather, the invention encompasses any novel feature and also any combination of features, which in particular includes any combination of features in the patent claims, even if this feature or this combination itself is not explicitly specified in the patent claims or exemplary embodiments.