Materials and methods for fabricating superconducting quantum integrated circuits

Abstract

Materials and methods are disclosed for fabricating superconducting integrated circuits for quantum computing at millikelvin temperatures, comprising both quantum circuits and classical control circuits, which may be located on the same integrated circuit or on different chips of a multi-chip module. The materials may include components that reduce defect densities and increase quantum coherence times. Multilayer fabrication techniques provide low-power and a path to large scale computing systems. An integrated circuit system for quantum computing is provided, comprising: a substrate; a kinetic inductance layer having a kinetic inductance of at least 5 pH/square; a plurality of stacked planarized superconducting layers and intervening insulating layers, formed into a plurality of Josephson junctions having a critical current of less than 100 μA/μm.sup.2; and a resistive layer that remains non-superconducting at a temperature below 1 K, configured to damp the plurality of Josephson junctions.

Claims

1. An integrated circuit system for quantum computing, comprising: a substrate having at least one surface; a kinetic inductance layer over the at least one surface of the substrate having a kinetic inductance of at least 5 pH/square; a plurality of stacked planarized superconducting layers and intervening insulating layers, over the at least one surface of the substrate, formed into a plurality of Josephson junctions, at least one Josephson junction having a critical current of less than 100 μA/μm.sup.2, at least one Josephson junction having a bias dependent on the kinetic inductance layer; and a resistive layer over the at least one surface of the substrate, that remains non-superconducting at a temperature below 1 K, patterned into damping elements to damp the plurality of Josephson junctions.

2. The integrated circuit system according to claim 1, wherein the kinetic inductance layer has a kinetic inductance of at least 8 pH/square.

3. The integrated circuit system according to claim 1, wherein the plurality of Josephson junctions each have a critical current of less than 50 μA/μm.sup.2.

4. The integrated circuit system according to claim 1, wherein the intervening insulating layers comprise a nitride.

5. The integrated circuit system according to claim 1, further comprising at least one bump bond comprising indium.

6. The integrated circuit system according to claim 1, further comprising at least one bump bond comprising a micron-scale copper post and indium adhesive bond.

7. The integrated circuit system according to claim 1, further comprising deuterium diffused into the Josephson junction.

8. The integrated circuit system according to claim 1, further comprising at least one hydrogen diffusion stop layer.

9. The integrated circuit system according to claim 1, further comprising a second substrate, the substrate and the second substrate being bonded together in alignment.

10. The integrated circuit system according to claim 9, wherein the second substrate comprises a plurality of superconducting qubits, and at least one of the qubits is electromagnetically coupled to a superconducting circuit comprising at least one of the plurality of Josephson junctions.

11. The integrated circuit system according to claim 9, wherein the substrate and the second substrate have protruding posts and corresponding trenches, wherein the protruding posts and corresponding trenches assure alignment of the substrate and the second substrate.

12. A method of forming an integrated circuit system for quantum computing, comprising: providing a substrate having a surface; forming a kinetic inductance layer having a kinetic inductance of at least 5 pH/square over the surface of the substrate; depositing a plurality of stacked superconducting layers and intervening insulating layers over the kinetic inductance layer; patterning the plurality of superconducting layers and intervening insulating layers into Josephson junctions, at least one Josephson junction having a critical current of less than 100 μA/μm.sup.2; planarizing the patterned plurality of superconducting layers and intervening insulating layers; and forming a resistive layer that remains non-superconducting at a temperature below 1 K over the planarized patterned plurality of superconducting layers, patterned to damp the Josephson junctions.

13. The method according to claim 12, wherein the substrate comprises a silicon substrate, and the intervening insulating layers comprise silicon nitride.

14. The method according to claim 12, wherein the kinetic inductance layer has a kinetic inductance of at least 8 pH/square.

15. The method according to claim 12, wherein the Josephson junctions have a critical current of less than 50 μA/μm.sup.2.

16. The method according to claim 12, further comprising bonding the substrate using at least one bump bond comprising indium.

17. The method according to claim 12, further comprising bonding the substrate using at least one bump bond comprising a micron-scale copper post and an indium adhesive bond.

18. The method according to claim 12, further comprising diffusing deuterium into the Josephson junction.

19. The method according to claim 12, further comprising forming at least one hydrogen diffusion stop layer over the substrate.

20. An integrated circuit system for quantum computing, comprising: a substrate which is non-superconducting at a temperature below 1 K; a patterned kinetic inductance layer, formed over the substrate, having a kinetic inductance of at least 5 pH/square; a plurality of stacked planarized superconducting layers and intervening insulating layers, formed over the kinetic inductance layer, and patterned into a plurality of Josephson junctions, at least one Josephson junction having a critical current of less than 100 μA/μm.sup.2; and a patterned resistive layer, that remains non-superconducting at a temperature below 1 K, formed over the plurality of stacked planarized superconducting layers and intervening insulating layers, and having a pattern to form Josephson junction damping elements for damping the plurality of Josephson junctions.

21. The integrated circuit according to claim 20, wherein: the substrate comprises a silicon substrate; the superconducting layers comprise niobium and are superconducting at 1 K; the intervening insulating layers comprise silicon nitride; and the kinetic inductance layer comprises niobium nitride.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 shows a cross-sectional view of a High Kinetic Inductance Layer.

(2) FIG. 2 shows a cross-sectional view of a Josephson Junction layer.

(3) FIG. 3 shows a cross-sectional view of a top ground layer.

(4) FIG. 4A shows a cross-sectional view of a control chip near a qubit chip.

(5) FIG. 4B shows a cross-sectional view of a control chip near the qubit chip, with lowered participation ratio than that shown in FIG. 4A.

(6) FIG. 5 shows a cross-sectional view of a control chip bonded to a qubit chip.

(7) FIG. 6A shows a top view of an exemplary circuit of section of a control chip.

(8) FIG. 6B shows a cross section across line 6B-6B of a portion of the control chip.

(9) FIG. 7A shows a quantum chip and control chip aligned using mating post and trench technology.

(10) FIG. 7B shows a quantum chip and control chip with copper pedestals aligned using mating post and trench technology.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

(11) FIG. 1 shows a cross-sectional view of the lowest layers of wiring on the silicon substrate. The vertical dimensions are not necessarily to scale, and the horizontal dimensions here are arbitrary.

(12) The silicon substrate is a high-resistance silicon wafer (typically 15 cm in diameter), with the native oxide removed. Note the presence of a patterned High-Kinetic Inductance (HKI) layer directly on the substrate, comprising a NbNx superconducting film with a kinetic inductance here of 8.5 pH/square. This is also called the MN1 layer, for metal nitride. This might be used as an inductor in a memory loop or a bias line, for example. The M0 layer is the superconducting ground plane, which could be Nb or NbN.

(13) The IN1 layer is the low-loss silicon nitride insulator layer that separates MN1 from M0, unless a via is needed to connect the two wiring layers. Silicon nitride is also used for the I0 layer above M0. The I0 layer is planarized (using a form of chemical-mechanical polishing or CMP) to form a flat substrate for a subsequent Josephson junction layer.

(14) FIG. 2 shows a cross-sectional view of the middle layers of the superconducting IC, focusing on the Josephson junction. This is labeled J1, and lies between Nb wiring layers M1 and M2, with the junction area defined with an anodization ring A1 around the junction. The junction layer itself comprises a trilayer with Nb base and counter-electrode, and a very thin layer of Al which is mostly oxidized to form the tunnel barrier between the two Nb layers. The critical current density of the junction is designed to be Jc=1 kA/cm.sup.2 (10 μA/μm.sup.2) in the relevant mK regime. The R2 layer is the resistor layer, here comprising a Pd—Au alloy film with a resistance 4 ohms/square down to the mK range. Note that here the R2 layer provides a resistive shunt for the Josephson junction, which critically damps the junction so that it may generate a picosecond SFQ voltage pulse. Layers M1 and M2 are 135 and 300 nm thick, respectively.

(15) FIG. 3 shows the cross section of the top layers of the superconducting circuit, including a 500 nm thick M3 layer of Nb, with a 100 nm top capping layer of Ta or NbNx. I2 is the silicon nitride insulating layer separating M2 from M3. The M3 layer may be a tantalum layer, or a niobium layer capped with tantalum, which forms a thinner native oxide layer than niobium.

(16) FIG. 4A shows the cross-section of the patterned control chip, with a section etched away where it would be close to a qubit chip. FIG. 4B shows a cross-section of the patterned control chip, with a section etched away where it would be close to a qubit chip, having a lowered participation ratio. The flip-chip assembly is shown in FIG. 5, where the qubit control loop is shown on top. FIG. 4A is a detail of FIG. 5, as indicated. It may be inductively coupled to SFQ pulses from the control chip below. Note the spacing between the two chips provided by the 5 μm Cu posts and Indium pressed bumps, where the indium provides a superconducting link between the two chips at the mK operating temperature.

(17) FIG. 6A shows a top view and FIG. 6B shows a corresponding cross-section for a section of a superconducting circuit of a control chip along section 6B-6B, showing multiple Josephson junctions, shunt resistors, inductors, and bias lines.

(18) FIG. 7A shows a first embodiment of how precision alignment may be assured between the control chip 4 (digital logic) and the quantum chip 3 (qubits). Known anisotropic silicon wafer etching techniques using chlorine-based etches may be used to create silicon posts 1 on the quantum chip and matching silicon trenches 2 on the control chip. The interlocking pairs can be strategically placed around the two chips to minimize the tilt between the two chips. The resulting micron-scale alignment can be used both for galvanic electrical contact (via the Cu/In bumps 5) and non-contact capacitive and inductive coupling between the classical control chip and the quantum chip.

(19) FIG. 7B shows a second embodiment which employs a copper pedestal for improved planarity with respect to the embodiment of FIG. 7A. While the control chip 4 (digital logic) and the quantum chip 3 (qubits) are not self-aligned, the copper pedestals can be planarized to ensure that the surfaces are parallel.

(20) The indium on the bumps is superconductive at the operating temperatures of the device, below 3.4 K, and make contact with a superconducting surface of the adjacent chip. In some cases, the adjacent chip surface is subject to oxidation or otherwise needs protection, and advantageously, a thin gold film may be formed on top of a superconducting surface, which itself will be induced into superconductivity under operating conditions.

(21) A) Exemplary Design Rules for Superconducting Quantum Control Circuit Electronics Fabrication: Process #QC1000A

1.0 General Description

(22) 1.1 This integrated circuit fabrication process uses only refractory materials, with the exception of a Pd/Au metallization layer used for contact pads. Niobium is used as the superconducting material due to its comparably high critical temperature, electrical and thermal stability, and ability to be thermally cycled many times without degradation. Niobium/Aluminum-Oxide/Niobium Josephson tunnel junctions are made by depositing an in-situ trilayer across the entire wafer and subsequently defining junction areas by deep-UV photolithography and etching. This method yields good uniformity and reproducibility of junction parameters.

(23) 1.2 The critical current density of Nb/AlO.sub.x/Nb trilayer associated with QC1000A is 1 kA/cm.sup.2 (10 μA/μm.sup.2).

(24) 1.3 The Josephson junctions can be interconnected into circuit configurations using four superconducting layers: junction base electrode (layer M1), two Nb wiring layers (layers M2 and M3), superconducting NbNx ground plane (layer M0) and a NbNx high kinetic inductance layer below the ground plane (MN1)

(25) 1.4 The sheet resistance of the resistive layer (R2) is a Ti/PdAu/Ti resistive material with sheet resistance of 2.0 ohms/sq and a thickness of 100±10 nm.

(26) 1.5 Low loss SiNx is deposited to provide insulation between the conducting layers. Anodization of the base electrode of trilayer provides additional insulation to Josephson junctions.

(27) 1.6 QC1000A is fabricated on a 150-mm diameter (6-inch) high resistivity Si wafer.

(28) 1.7 QC1000A Process Flow Overview is shown in the table below.

(29) TABLE-US-00001 GDS Mask # Layer # polarity Description Al/NbNx deposition 1 MN1 34 + MN1 layer patterning Low loss SiN.sub.x deposition 2 IN1 32 − Contact (via) between MN1 and M0 patterning NbNx deposition 3 M0 30 − M0 patterning (holes in niobium ground plane) Low loss SiN.sub.x deposition CMP “Caldera” planarization 4 I0 31 − Contact (via) between M1 and ground plane patterning Nb/Al/AlO.sub.x/Nb trilayer deposition (see 1.2) 5 J1 4 + Counter-electrode (junction area) definition Base electrode anodization 6 A1 5 + Anodization layer patterning 7 M1 1 + Trilayer base electrode patterning Low loss SiN.sub.x deposition 8 R2 9 + Resistive layer patterning Resistive layer deposition (see 1.4) Low loss SiN.sub.x deposition 9 I1 3 − Contact (via) between M2 and (J1/J2, R2, or M1) Nb deposition 10 M2 6 + M2 layer patterning Low loss SiN.sub.x deposition 11 I2 8 − Contact (via) between M2 and M3 Nb deposition 12 M3 10 + M3 layer patterning 13 I3 13 − I3 (Dielectric removal from Qubit interface) patterning 14 R3 11 + Contact pad patterning Pd/Au contact metallization deposition 15 BMP-Cu 12 + “bump” layer for MCM, Copper 16 BMP-In 15 + “bump” layer for MCM, Indium

(30) Layout Design Rules

(31) 2.1 Minimal size, spacing, and surround for each layer are specified in the following table:

(32) TABLE-US-00002 # Layer Rule μm Comment 1 MN1 Positive MN1 wiring layer 1.1 MN1 minimal size 0.8 1.2 MN1 minimal spacing 1.0 1.3 MN1 surround IN1 0.3 2 IN1 Negative Contact (via) between MN1 and M0 2.1 IN1 minimal size 0.8 2.2 IN1 surrounded by 0.3 MN1 2.3 IN1 spacing to M0 0.3 A via should always be covered with metal. M0 is a negative layer, -“spacing” instead of “surrounded by” 2.4 IN1 edge spacing to J1 0.5 Crossing IN1 pattern with JJs is possible but not recommended 3 M0 Negative Holes in ground plane 3.1 M0 minimal size 0.5 3.2 M0 minimal spacing 0.5 3.3 M0 spacing to I0 0.3 A hole in insulation should always be over metal. M0 is a negative layer, - so, the rule is “spacing to”. 4 I0 Negative Contact (via) between M1 and ground plane 4.1 I0 minimal size 1.0 4.2 I0 spacing to J1 1.0 J1 patterns should not overlap with I0 patterns. A hole in insulation layer must be completely 4.3 I0 surrounded by M1 0.3 covered by two adjacent metal layers (from top and bottom) 4.4 I0 edge spacing to R2 0.3 5 J1 Positive Trilayer counter electrode (junction area) definition 5.1 J1 minimal size 0.6 5.2 J1 minimal spacing 1.0 5.3 J1 surrounded by A1 0.5 A JJ must be covered by anodization layer 5.4 J1 surrounded by M1 1.0 5.5 M0 edge spacing to J1 0.5 5.6 I0 edge spacing to J1 1.0 J1 patterns should not overlap with I0 patterns. 5.7 IN1 edge spacing to J1 0.5 Crossing J1 patterns with IN1 is not recommended. 6 A1 Positive M1 anodization layer patterning 6.1 A1 minimal size 1.0 6.2 A1 surrounded by M1 0.3 6.3 A1 edge spacing to R2 0.3 6.4 A1 edge spacing to I1 0.5 If hole in I1 is surrounded by A1, no galvanic contact to M1 is possible (except for via JJ) 7 M1 Positive Trilayer base electrode patterning 7.1 M1 minimal size 0.8 7.2 M1 minimal spacing 1.0 7.3 M1 edge spacing to R2 0.3 7.4 M1 surround I1.sup.(7) 0.5 8 R2 Positive Resistive layer patterning 8.1 R2 minimal size 0.8 8.2 R2 minimal spacing 1.0 8.3 R2 surround I1 0.5 A simultaneous contact to both R2 and M1 layers is possible. The overlap area of I1 hole with each layer (R2 and M1) should satisfy rule 8.1 8.4 M0, M1, I0, or A1 edge 0.3 R2 pattern may not cover steps in I0, A1 or M1. spacing to R2 Placing R2 object inside M0, I0, A1 or M1 area is allowed. 9 I1 Negative Contact (via) between M2 and (J1/J2, R2, or M1) 9.1 I1 minimal size 1.0 9.2 I1 surrounded by M2 0.5 10 M2 Positive M2 wiring layer 10.1 M2 minimal size 0.8 10.2 M2 minimal spacing 1.0 10.3 M2 surround I2 0.5 11 I2 Negative Contact (via) between M2 and M3 11.1 I2 minimal size 1.8 11.2 I2 surrounded by M3 0.5 12 M3 Positive M3 wiring layer 12.1 M3 minimal size 2.0 12.2 M3 minimal spacing 2.0 12.3 M3 minimal contact 5.0 R3 layer is deposited directly on M3 (without with R3 insulation). To provide a reliable electrical contact between objects in R3 and M3 layers, the overlap should be no less than 5 microns. 13 I3 Negative Di-electric removal from selected area 13.1 I3 minimal size 1.8 13.2 I2 surrounded by M3 0.5 14 R3 Negative Pd/Au contact metallization 14.1 R3 minimal size 5.0 14.2 R3 minimal spacing 3.0 14.3 R3 surrounded by M3 0.5 15 BMP1 Negative Copper bumps layer for MCM 15.1 BMP minimal size 10 15.2 BMP minimal spacing 30 16 BMP2 Negative Indium bumps layer for MCM 16.1 BMP minimal size 15 16.2 BMP minimal spacing 30 16.3 BUM2 surround BNP1 2.5

3.0 Physical Layer Process Specifications

(33) 3.1 Since the fabrication process involves projection photolithography and etching, the size of features (e.g., linewidth) on the wafer may systematically differ somewhat from the designed feature size. This change in size is called “bias”. In the table below, the bias is defined as the shift of the object's edge due to its enlargement/reduction relative to its intended position in the design. It is often called single-side bias. A positive bias means that the digitized areas become larger on the wafer than in the design. The biases shown below for all layers, except J1/J2, are applicable to relatively extended objects with sizes larger that the minimal feature size for a given layer. In most cases, sharp corners will be rounded up.

(34) TABLE-US-00003 Bias (3.1) Physical layer properties: resistance, Thickness Layer Material μm capacitance, etc. nm MN1 NbN.sub.x 0.0 ± 0.1 Nb, superconductor. Penetration depth λ.sub.L = 40 ± 4  250 nm ± 5% IN1 SiN.sub.x 0.0 ± 0.1 SiN.sub.x, insulator. Capacitance: 0.24 fF/μm.sup.2 ± 75 ± 7  20% M0 NbN.sub.x 0.0 ± 0.1 Nb, superconductor. Penetration depth λ.sub.L = 200 ± 10  250 nm ± 5% I0 SiN.sub.x 0.0 ± 0.1 SiN.sub.x, insulator. Capacitance: 0.31 fF/μm.sup.2 ± 150 ± 15  10% M1 Nb 0.0 ± 0.1 Trilayer base electrode, superconductor. λ.sub.L = 135 ± 10  100 nm ± 5% J1 Nb  0.0 ± 0.02 Josephson tunnel junction counter electrode 50 ± 5  (see 3.2 and 3.3) A1 Nb.sub.2O.sub.5/Al.sub.2O.sub.3 0.0 ± 0.1 Layer of the anodized surface of base 40 ± 5  electrode (i.e., surrounding a Josephson junction). Capacitance: 5.0 fF/μm.sup.2 ± 20% SiN.sub.x SiN.sub.x, insulator. Capacitance: 0.52 fF/μm.sup.2 ± 100 ± 10  10% R2 Ti/PdAu/Ti 0.0 ± 0.1 2.0 ± 0.2 Ohm per square 40 ± 6  SiN.sub.x SiN.sub.x, insulator. Capacitance: 0.52 fF/μm.sup.2 ± 100 ± 10  10% I1 0.0 ± 0.1 Contact hole through the above two SiO.sub.2 layers M2 Nb −0.1 ± 0.05 Nb, superconductor. Penetration depth λ.sub.L = 300 ± 20  80 nm ± 5% SiN.sub.x SiN.sub.x insulator. Capacitance: 0.08 fF/μm.sup.2 ± 500 ± 40  10% I2 0.0 ± 0.1 Contact hole through the above insulator M3 Nb −0.3 ± 0.1  Nb, superconductor. Penetration depth: λ.sub.L = 500 ± 50  Capped with 80 nm ± 5% 100 ± 10  Ta/NbNx I3 di-electric removal R3 Pd/Au 0.0 ± 1.0 Contact pads metallization 350 ± 60  BMP- Cu/Au 0.0 ± 1.0 Copper Layer for MCM bump 6000 ± 600  Cu BMP- NbNx/In 0.0 ± 1.0 Indium Layer for MCM bump 3000 ± 300  In

(35) 3.2 Josephson junctions of circular shape are recommended. The deviation of the radius of the circle in J1 layer is within ±20 nm. If such a deviation is critical, use “digitized circular shape”, i.e., a polygon with vertices of 135 degrees placed on 20-nm grid.

(36) 3.3 The C.sub.s is the specific capacitance in fF/μm.sup.2 and j.sub.c is the critical current density in μA/μm.sup.2, and plasma voltage in mV.

(37) TABLE-US-00004 J.sub.c (μA/μm.sup.2) 0.3 1.0 10.0 45.0 100.0 200.0 Cs (fF/μm.sup.2) 37 40 50 59 65 71 Vp (μV) 52 91 257 501 711 962

(38) 3.4 The critical current per micron width for superconducting films is given in the following table

(39) TABLE-US-00005 Nb Layer MN1 M0 M1 M2 M3 I.sub.c (mA/μm) 2.5 20.0 30.0 50.0 70.0

(40) If the wire crosses over steps, its I.sub.c may drop by more than 50%. The minimal width of a wire is shown in table 2.1 and its bias in table 3.0 before designing current transmitting lines.

(41) 3.5 The specific inductance of the superconducting films is given in the following table

(42) TABLE-US-00006 Layer MN1-M0 M0-M1-M3 M0-M2-M3 M0-M2 Ls (pH/sq) 8.50 0.40 0.38 0.63

(43) TABLE-US-00007 Lithography features Mask Grid Grid Size Size Layer Polarity [μm] MN1 Clear field 0.1 IN1 Dark field 0.1 M0 Dark field 0.1 I0 Dark field 0.1 M1 Clear field 0.1 J1 Clear field 0.02 J2 Clear field 0.02 A1 Clear field 0.1 R2 Clear field 0.1 I1 Dark field 0.1 M2 Clear field 0.1 I2 Dark field 0.1 M3 Clear field 0.1 I3 Dark field 0.1 R3 Dark field 0.1 BMP-Cu Dark field 0.1 BMP-In Dark field 0.1

(44) 4.2 Layer J1 have grid size of 20 nm. All remaining layers must use grid size of 100 nm. Every pixel coordinate is rounded up to a multiple of grid.

(45) 4.3 All layouts will be printed on wafers as you see them on your computer screen (no mirroring).

5.0 Designs Submission Formats

(46) The format of layout file is GDS-II. The active chip area for the design is limited to 5,000 μm×5,000 μm. On the wafer, it will be surrounded by a dicing channel. Dicing channels between chips are 150 μm wide. No objects are allowed inside a dicing channel (extending beyond the 5,000 μm×5,000 μm area). In the case of 1-cm chips, the design area is 10,150 μm×10,150 μm. No objects are allowed beyond the 10,150 μm×10,150 μm area.

(47) B. Substitution of Deuterium for Hydrogen to Reduce Noise in Quantum Circuits

(48) This provides a method of manufacturing quantum devices where deuterium is incorporated into the devices either as an additional component or as a replacement of light hydrogen within the molecules of the component materials of the integrated circuits in order to reduce quasiparticles and intrinsic losses.

(49) A basic challenge towards the creation of qubits is developing devices whose quantum coherence lasts long enough to enable control and measurement with error rates below the bounds requisite for quantum error correction.

(50) For example, lossy materials within the mode volume of superconducting resonant structures impose a limit on how long such systems can store energy. Reducing the participation ratio of energy-storing non-vacuum materials (inclusive of surfaces, interfaces, thin films, and bulk matter) within the mode volume increases this limit. In particular, two-level systems present at surfaces and interfaces of superconducting qubits are believed to be a significant source of decoherence. The substrate to metal interface and substrate to air interface are believed to be a source of loss.

(51) Deuterium is an isotope of hydrogen with a nuclear spin=1, unlike hydrogen which has a spin=½. The manipulation of nuclear spin by radiofrequency waves is important in chemical spectroscopy and medical imaging. When placed in a magnetic field, active nuclei absorb electromagnetic radiation at a frequency characteristic to the isotope. The resonant frequency, energy of the radiation absorbed, and the intensity of the signal are proportional to the strength of the magnetic field. Such a signal, although beneficial for chemical spectroscopy and medical imaging is a potential source of quasiparticles and losses in quantum devices.

(52) Deuterium is most commonly used in hydrogen nuclear magnetic resonance spectroscopy (proton-NMR). NMR ordinarily requires compounds of interest to be analyzed as dissolved in solution. Because of deuterium's nuclear spin properties which differ from the light hydrogen usually present in organic molecules, NMR spectra of hydrogen/protium are highly differentiable from that of deuterium, and in practice deuterium is not seen by an NMR instrument tuned for light hydrogen. Deuterated solvents (including heavy water, but also compounds like deuterated chloroform, CDCl.sub.3) are therefore routinely used in NMR spectroscopy, in order to allow only the light hydrogen spectra of the compound of interest to be measured, without solvent signal interference.

(53) Exemplary embodiments include a qubit system, including a substrate layer, where the substrate surface is treated with a deuterated hexamethyldisilane (HMDS) immediately prior to metal deposition to reduce losses associated with the metal-substrate interface.

(54) Additional exemplary embodiments include a method of fabricating a qubit system, where a crystalline silicon layer is grown epitaxially on the substrate using a deuterated silane source gas. The deuterated silane may also consist of an isotopically pure silicon-28 isotope for the formation of spin silicon qubits.

(55) Further exemplary embodiments include a method of fabricating a qubit system, where superconducting quantum circuits containing Josephson junctions are employed for qubits on a quantum device which is bonded as a multi-chip module (MCM) to a classical superconducting electronic control circuit. The classical superconducting electronic control circuit consists of deuterated dielectric materials as insulators (i.e., deuterated tetraethyl orthosilicate glass (TEOS), silicon nitride with a deuterium impurity) that may be formed by employing plasma enhanced chemical vapor deposition (PECVD) with deuterated source gases (i.e., deuterated silane, deuterated ammonia).

(56) C. Chemical-Mechanical Polishing (CMP) for Very Large Scale Integration of Classical and Quantum Superconducting Electronic Integrated Circuits

(57) Conventionally, in the superconducting electronics field, a wiring pattern comprising a dense array of superconductive lines is formed by depositing a metal layer and etching to form a superconductive pattern. An insulating layer, typically formed of a dielectric material, is then applied to the wiring pattern and planarization of the dielectric material is achieved by chemical mechanical planarization.

(58) Typically, the chemical mechanical planarization process for superconducting integrated circuits involves either planarizing the dielectric above or below the metal pattern without exposing the metal pattern, allowing for more wiring layers, but fails to provide stacked vias and high density VLSI chips. Another process, called the caldera process, also provides a planarized and exposed metal pattern. In the caldera process, the dielectric material is etched, exposing the metal pattern, then a silica-based slurry is utilized wherein the remaining dielectric material is planarized. The limitations of the caldera process are that it requires many processing steps, and has not yet been proven to provide stacked vias and other components on all microdevice layers. Currently, it is extremely difficult to planarize layers with both small and large structures while providing a highly uniform wafer surface, let alone in a reproducible manner while exposing a superconducting pattern.

(59) According to a preferred embodiment, the surface of the integrated circuit is planarized in a pattern-independent manner comprising chemical-mechanical polishing, to selectively remove materials so as to leave an exposed Damascene pattern. Preferably, excess insulating material (e.g., silicon nitride) is removed from the metallic wiring. The conventional Damascene process is limited when the metal is removed at a low selectivity to the insulating material. When the metal removal rate is not selective enough to the insulating material, then the process severely erodes the insulator. The present approach addresses such a limitation, by enabling the use of a reverse Damascene process.

(60) The reverse Damascene process also provides a planar surface with a wiring pattern embedded in an insulating layer. The embedded wiring pattern is formed by first etching a deposited metal or other conductive and/or superconductive material. Once the pattern is formed, a conformal insulating layer is deposited onto the patterned surface. The conformal insulating layer is chemically-mechanically polished to remove all insulator above the patterned layer. After polishing, the top surface of the patterned metallic, conductive and/or superconductive material is exposed but remains embedded in the insulating layer.

(61) Currently, chemical-mechanical polishing (CMP) using a ceria-based slurry is adopted to achieve the formation of shallow trench isolation (STI) for element isolation in the manufacturing of semiconductor devices. STI is formed by providing a groove to a semiconductor substrate comprising a CMP stopper film, forming a silicon oxide film thereon, and removing the excess silicon oxide film by CMP. The stopper film is then removed in a subsequent processing step. Typically, the stopper film is a nitride such as silicon nitride.

(62) According to the present technology, a novel application of silicon nitride and ceria-based slurries has been achieved, wherein the silicon nitride is the main dielectric used for insulation without the need for silicon oxide, and a stopper film is not required when either silicon oxide or silicon nitride dielectric insulation is used.

(63) Alternatively, instead of ceria, other abrasives can be utilized such as silica or alumina. If the patterned metallic, conductive and/or superconductive material is a niobium-based material, then it is possible for a corrosive slurry to stop on the niobium-based material regardless of abrasive type.

(64) Additives such as polymers, surfactants, inhibitors, and/or oxidizers may be added into the slurry for known purposes.

(65) The superconductive material, dielectric material, slurry pH and abrasive type are not limited to the preferred embodiments.

(66) The chemical-mechanical polishing may be performed in two or more steps rather than in one step provided in the preferred embodiment.

(67) The polishing pad can be any of those which are conventionally employed in CMP, such as those comprising a cellular polyurethane pad. The polishing pad utilized in the preferred embodiment consists of a hard pad over a soft base pad. The hard pad consists of a cellular material while the soft base pad consists of a felt material.

(68) The polishing parameters (i.e., slurry flow rate, down-force, table rotation) are optimized for maximum uniformity. The polishing parameters may also be set slightly above or below that of the preferred embodiment. The conditioning of the pad during CMP (i.e., in-situ or ex-situ) is preferred but not required.

(69) The polishing process may be timed and calculated based on the rate of removal of the insulating material. The polishing process does not require the detection of an endpoint, through the use of metrology (i.e., ellipsometry, profilometry) or by any other means. Endpoint detection may also be employed. In addition, stopping the chemical-mechanical polishing process before the endpoint is reached and then reaching the endpoint in a second processing step (i.e., reactive ion etching, wet etching) is another embodiment.

(70) Depositing a liner material (i.e., silicon nitride, tantalum nitride) as a stopping material over the metal, conductor and/or superconductor, to be later removed in a subsequent step is yet another embodiment.

(71) These examples are not to be understood as limiting the invention, but rather as examples that illustrate the wide range of systems and applications that may become clear to those skilled in the art. The scope of the present invention includes the various combinations, subcombinations and permutations of the elements disclosed herein either expressly or through incorporation. No element shall be deemed critical or required unless specified as being a universally necessary element.

(72) Each reference cited herein is expressly incorporated herein in its entirety, for its respective descriptions and teachings.