Circuits for switched capacitor receiver front-ends

Abstract

Switched capacitor radio frequency receiver front-ends are provided, comprising: a plurality of banks, each comprising: a first switch connected to a RF input signal; a sampling capacitor connected to the first switch and to ground; a second switch connected in parallel to the sampling capacitor; and a Gm cell coupled to the sampling capacitor and an output; wherein: the output of the Gm cell of each of the plurality on banks are coupled together; and the first switch and the second switch are controlled by a multi-phase signal that causes, for each of the plurality of banks, the first switch to be turned ON at a first point in time and the second switch to be turned ON at a second point in time, wherein the first point in time for a first bank is not the same as the first point in time for a second bank.

Claims

1. A circuit for a switched capacitor radio frequency (RF) receiver front-end, comprising: a plurality of banks, each comprising: a first switch having a first side connected to a RF input signal and a second side; a sampling capacitor having a first side connected to the second side of the first switch and a second side connected to ground; a second switch having a first side connected to the first side of the sampling capacitor and a second side connected to the second side of the sampling capacitor; and a Gm cell having a first input coupled to the first side of the sampling capacitor and an output; wherein: the output of the Gm cell of each of the plurality on banks are coupled together; and the first switch and the second switch are controlled by a multi-phase signal that causes, for each of the plurality of banks, the first switch to be turned ON at a first point in time and the second switch to be turned ON at a second point in time, wherein the first point in time for a first of the plurality of banks is not the same as the first point in time for a second of the plurality of banks.

2. The circuit of claim 1, wherein: the first input of the Gm cell is coupled to the first side of the sampling capacitor by a third switch; the third switch is controlled by the multi-phase signal; and the third switch is turned ON at a third point in time.

3. The circuit of claim 1, wherein: the first input of the Gm cell is coupled to the first side of the sampling capacitor by a connection; each of the plurality of banks further comprises a fourth switch at the output of the Gm cell that couples the output of the Gm cell to the output of the Gm cell of other bank(s) of the plurality of banks; the fourth switch is controlled by the multi-phase signal; and the fourth switch is turned ON at a fourth point in time.

4. The circuit of claim 1, wherein: each of the plurality of banks further comprises: a fifth switch having a first side connected to the RF input signal and a second side; and a second capacitor having a first side connected to the second side of the fifth switch and a second side connected to the ground; the fifth switch is controlled by the multi-phase signal; and the fifth switch is turned ON at a fifth point in time.

5. The circuit of claim 1, wherein: each of the plurality of banks further comprises: a sixth switch having a first side connected to the second side of the first switch and a second side; and a third capacitor having a first side connected to the second side of the sixth switch and a second side connected to the ground; the sixth switch is controlled by the multi-phase signal; and the sixth switch is turned ON at a sixth point in time.

6. The circuit of claim 5, wherein: each of the plurality of banks further comprises: a seventh switch having a first side connected to the second side of the first switch and a second side; and a fourth capacitor having a first side connected to the second side of the seventh switch and a second side connected to the ground; the seventh switch is controlled by the multi-phase signal; and the seventh switch is turned ON at a seventh point in time.

7. The circuit of claim 6, wherein: each of the plurality of banks further comprises: an eighth switch having a first side connected to the second side of the first switch and a second side; and a fifth capacitor having a first side connected to the second side of the eighth switch and a second side connected to the ground; the eighth switch is controlled by the multi-phase signal; and the eighth switch is turned ON at an eighth point in time.

8. The circuit of claim 1, further comprising a transimpedance amplifier having an input coupled to the output of the Gm cell.

9. The circuit of claim 1, wherein each of the plurality of banks further comprises sixth capacitor that is in parallel with the sampling capacitor during a sampling phase of the multi-phase signal and in series with the sampling capacitor during at least one other phase of the multi-phase signal.

10. The circuit of claim 1, wherein the sampling capacitor is implemented using a PMOS transistor.

11. The circuit of claim 1, wherein the sampling capacitor is implemented using an NMOS transistor.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a block diagram of an example of an architecture of a single-ended version of a switched capacitor (SC) radio frequency (RF) receiver front-end in accordance with some embodiments.

(2) FIG. 2 is a timing diagram of an example of a multi-phase control signal for controlling switches in a front-end in accordance with some embodiments.

(3) FIG. 3 is a timing diagram of an example of sequential time intervals of a front-end in accordance with some embodiments.

(4) FIG. 4 is a block diagram of an example of a SC front-end without filtering in accordance with some embodiments.

(5) FIG. 5 is a block diagram of an example of Gm cells modeled as a discrete time (DT) mixer with a reconstruction circuit in accordance with some embodiments.

(6) FIG. 6 is a block diagram of an example of a sampler in accordance with some embodiments.

(7) FIG. 7 is a block diagram of a model of a sampler in accordance with some embodiments.

(8) FIG. 8 is a block diagram of an example of a sampler over multiple banks in accordance with some embodiments.

(9) FIG. 9 is a block diagram of sampler modeled as a continuous time (CT) filter and an ideal sampler in accordance with some embodiments.

(10) FIG. 10 is an illustration of an example of G(f) and H(f) curves in accordance with some embodiments.

(11) FIG. 11 is an illustration of an example of the charging of a sampling capacitor in accordance with some embodiments.

(12) FIG. 12 is a block diagram of an example of a DT infinite-impulse response (IIR) filter in accordance with some embodiments.

(13) FIG. 13 is an illustration of an example of calculated IIR filter transfer curves in accordance with some embodiments.

(14) FIG. 14 is a block diagram of an example of noises sources in the front-end without filtering in accordance with some embodiments.

(15) FIG. 15 is an illustration of an example of white noise from multiple banks be merged into one representation in accordance with some embodiments.

(16) FIG. 16 is a block diagram for analyzing noise in accordance with some embodiments.

(17) FIG. 17 is an illustration of graphs of noise transfer functions in accordance with some embodiments.

(18) FIG. 18 is a block diagram of a model to calculate the propagation of noise in a front-end in accordance with some embodiments.

(19) FIG. 19 is a block diagram of example of a CMOS switch in accordance with some embodiments.

(20) FIG. 20 is a schematic of an example of a SC RF receiver front-end in accordance with some embodiments.

(21) FIG. 21 is a block diagram of an example of a clock divider circuit in accordance with some embodiments.

(22) FIG. 22 is a block diagram of an example of a clock driver circuit in accordance with some embodiments.

(23) FIG. 23 is a block diagram of an example of a chopping SC receiver front-end in accordance with some embodiments.

(24) FIG. 24 is a block diagram of an example of a chopping SC receiver front-end with merged choppers in accordance with some embodiments.

(25) FIG. 25 is a schematic diagram of an example of a chopping SC receiver front-end with merged choppers in accordance with some embodiments.

(26) FIG. 26 is a block diagram of an example of a blocker envelope detector in accordance with some embodiments.

(27) FIG. 27 is a block diagram of an example of a Gm cell in accordance with some embodiments.

(28) FIG. 28 is a block diagram of an example of a variable capacitor in accordance with some embodiments.

(29) FIG. 29 is a block diagram of an example of a SC RF receiver front-end using stacked sampling capacitors in accordance with some embodiments.

(30) FIG. 30 is an illustration of the operation of a SC RF receiver front-end using stacked sampling capacitors in accordance with some embodiments.

(31) FIG. 31 is a block diagram of an example of a SC RF receiver front-end using transistors as sampling capacitors in accordance with some embodiments.

(32) FIG. 32 is an illustration of the operation of a SC RF receiver front-end using transistors as sampling capacitors in accordance with some embodiments.

(33) FIG. 33 is a block diagram of PMOS and NMOS capacitors in parallel in accordance with some embodiments.

DETAILED DESCRIPTION

(34) In accordance with some embodiments, switched capacitor (SC) RF receiver front-ends are provided. In some embodiments, high-order filtering is achieved by linear passive SC circuits to attenuate out-of-band (OB) blockers before they reach the nonlinear active baseband amplifier of the receiver front-end. In some embodiments, the SC RF receiver front-end can also perform RF input impedance matching, N-path filtering, high-order discrete-time infinite-impulse response (IIR) filtering, and down conversion. In some embodiments, the front-end can be implemented in 40 nm CMOS, 65 nm CMOS, and/or any other suitable technology.

(35) Turning to FIG. 1, an example 100 of an architecture of a single-ended version of a SC RF receiver front-end in accordance with some embodiments is shown. Architecture 100 includes eight RF SC banks 102 (which each include an in-phase section 108 and a quadrature section 110 each having the same circuitry as illustrated in section 108) followed by baseband Gm cells 104 and trans-impedance amplifiers (TIAs) 106.

(36) Although eight banks 102 are illustrated herein, any suitable number of banks can be used in some embodiments.

(37) As shown in FIG. 1, each of sections 108 and 110 can include switches s.sub.0 112, s.sub.1 114, s.sub.2 116, s.sub.3 118, s.sub.4 120, s.sub.5 122, and s.sub.6 124. These switches can be implemented in any suitable manner. For example, in some embodiments, as described below in connection with FIG. 19, these switches can be implemented using PMOS transistors, NMOS transistors, CMOS transmission gates, etc.

(38) As also shown, each of sections 108 and 110 can include capacitors C.sub.s 126, C.sub.h0 128, C.sub.h1 130, C.sub.h2 132, and C.sub.h3 134. These capacitors can be implemented in any suitable manner. For example, in some embodiments, these capacitors can be implements using metal-oxide-metal (MoM) layers.

(39) In some embodiments, capacitor C.sub.s 126 can be variable. This can be implemented in any suitable manner. For example, in some embodiments, capacitor C.sub.s 126 can be implemented using a bank of parallel series-switch-capacitor pairs that can enable capacitors to be switched in and out of the bank as shown in FIG. 28. Any suitable number of pairs can be provided in the bank in some embodiments.

(40) In some embodiments, the series-switch-capacitor pair formed by switch s.sub.0 112 and capacitor C.sub.h0 128 can be replaced with any suitable number of parallel series-switch-capacitor pairs. In such a scenario, the switches can be controlled by a common signal, or by separate signals.

(41) In accordance with some embodiments, capacitors C.sub.h0i 128 and switches s.sub.0i 112 in all eight banks (i=1 . . . 8) can be used to form an RF N-path filter (NPF) (where N equals 8 based on the eight banks) to attenuate the OB signals.

(42) In some embodiments, capacitors C.sub.si 126 and switches s.sub.1i 114 and s.sub.6i 124 can be used to perform impedance matching. Also, the RF signal can be sampled on C.sub.si, and the continuous-time (CT) signal converted to the discrete-time (DT) domain.

(43) After sampling, history capacitors C.sub.h1i 130, C.sub.h2i 132, and C.sub.h3i 134 and switches s.sub.2i 116, s.sub.3i 118, and s.sub.4i 120, as well as capacitors C.sub.si 126 and switches s.sub.6i 124, realize a high-order DT infinite-impulse-response (IIR) filter, and switches s.sub.5i 122 propagate the signal to the input nodes of Gm cells 104.

(44) The Gm cells receiving inputs from the in-phase (I) paths 108 and quadrature (Q) paths 110 combine the signal from all eight SC banks and achieve harmonic rejecting down-conversion. Also, here the DT signal is converted back to the CT domain.

(45) In some embodiments, switches s.sub.0 112, s.sub.1 114, s.sub.2 116, s.sub.3 118, s.sub.4 120, s.sub.5 122, and s.sub.6 124 can be driven by a multi-phase, non-overlapping clock signal pi as shown in FIG. 2. More particularly, for example, for Bank #1, as shown, switch s.sub.0 112 can be driven by p.sub.1, switch s.sub.1 114 can be driven by p.sub.1, switch s.sub.2 116 can be driven by p.sub.2, switch s.sub.3 118 can be driven by p.sub.3, switch s.sub.4 120 can be driven by p.sub.4, switch s.sub.5 122 can be driven by p.sub.5, and switch s.sub.6 124 can be driven by p.sub.7.

(46) As also shown in FIG. 2, when there are eight phases, the sampling frequency is f.sub.s, and the equivalent local oscillator (LO) frequency of this zero-intermediate-frequency receiver is f.sub.lo=f.sub.s/8.

(47) Although eight phases p.sub.1, . . . , p.sub.8 are illustrated herein, any suitable number of phases can be used in some embodiments.

(48) The SC front-end achieves different circuit functions in sequential time intervals as shown in FIG. 3. These functions are shifted in time (interleaved) for each bank.

(49) For example, for SC Bank #1, the RF signal is sampled on Cs in phase p.sub.1, propagated to the Gm input node in phase p.sub.5, and dumped to ground in phase p.sub.7. From phases p.sub.2 to p.sub.4, the signal is filtered with increasing order.

(50) For example, for SC Bank #2, the RF signal is sampled on Cs in phase p.sub.2, propagated to the Gm input node in phase p.sub.6, and dumped to ground in phase p.sub.8. From phases p.sub.3 to p.sub.5, the signal is filtered with increasing order.

(51) For example, for SC Bank #3, the RF signal is sampled on Cs in phase p.sub.3, propagated to the Gm input node in phase p.sub.7, and dumped to ground in phase p.sub.1. From phases p.sub.4 to p.sub.6, the signal is filtered with increasing order.

(52) For example, for SC Bank #4, the RF signal is sampled on Cs in phase p.sub.4, propagated to the Gm input node in phase p.sub.8, and dumped to ground in phase p.sub.2. From phases p.sub.5 to p.sub.7, the signal is filtered with increasing order.

(53) For example, for SC Bank #5, the RF signal is sampled on Cs in phase p.sub.5, propagated to the Gm input node in phase p.sub.1, and dumped to ground in phase p.sub.3. From phases p.sub.6 to p.sub.8, the signal is filtered with increasing order.

(54) For example, for SC Bank #6, the RF signal is sampled on Cs in phase p.sub.6, propagated to the Gm input node in phase p.sub.2, and dumped to ground in phase p.sub.4. From phases p.sub.7 to p.sub.1, the signal is filtered with increasing order.

(55) For example, for SC Bank #7, the RF signal is sampled on Cs in phase p.sub.7, propagated to the Gm input node in phase p.sub.3, and dumped to ground in phase p.sub.5. From phases p.sub.8 to p.sub.2, the signal is filtered with increasing order.

(56) For example, for SC Bank #8, the RF signal is sampled on Cs in phase p.sub.8, propagated to the Gm input node in phase p.sub.4, and dumped to ground in phase p.sub.6. From phases p.sub.1 to p.sub.3, the signal is filtered with increasing order.

(57) The blank time intervals (e.g., phases p.sub.6 and p.sub.8 for Bank #1) relax the timing constraints.

(58) FIG. 4 shows an example of a representation of the SC front-end without filtering. Because the switches s.sub.1i in the eight banks are turned ON one after another in phases p.sub.1 through p.sub.8, respectively, the input signal is consecutively sampled on the capacitors C.sub.si in the eight banks. Those sampled voltages, V.sub.sp[k] to V.sub.sp[k+7] (k=8.Math.l, l is an integer), can be considered as one time-interleaved signal V.sub.sp[n] with sampling frequency f.sub.s.

(59) As shown in FIG. 5, in some embodiments, the sampler can be mathematically modeled as an ideal sampler with a CT anti-aliasing filter G(f). The signal V.sub.sp[n] is propagated to the inputs of the Gm cells after a delay of 4/f.sub.s. As also shown in FIG. 5, the Gm cells can be modeled as a DT mixer with a reconstruction circuit converting the DT voltage to a CT current.

(60) Turning to FIG. 6, RF input impedance matching can be achieved in the SC front-end by charging and discharging C.sub.si. Because V.sub.in=Z.sub.in/(Z.sub.in+R.sub.s).Math.V.sub.s, the input impedance can be calculated from V.sub.in and V.sub.s. To analyze V.sub.in, a linear periodically time varying (LPTV) approach can be used since the matching circuit is a CT SC system. In an LPTV system, the frequency domain input voltage V.sub.in(f) is a summation of filtered source voltage V.sub.s(f) with frequency shifts:
V.sub.in(f)=.sub.n=.sup.H.sub.n(f)V.sub.s(fnf.sub.s)(1)

(61) To calculate the input impedance Z.sub.in(f), H.sub.0(f) in (1) is needed. The input impedance can be calculated by Z.sub.in(f)=H.sub.0(f)/(1H.sub.0(f)).Math.R.sub.s. H.sub.0 can be represented by:

(62) $\begin{array}{cc}{H}_0\left(f\right)=\frac{1}{1+\mathrm{jf}/f_{\mathrm{rc}}}\left[1-\frac{f_s/2f_{\mathrm{rc}}}{1+\mathrm{jf}/f_{\mathrm{rc}}}\left(1-e^{-2\left(f_{\mathrm{rc}}+\mathrm{jf}\right)/\mathrm{fs}}\right)\right]& \left(2\right)\end{array}$
where f.sub.rc=1/(2R.sub.sC.sub.s), and f.sub.s is the sampling frequency. The input admittance (Y.sub.in(f)=1/Z.sub.in(f)) can now be expressed as:

(63) $\begin{array}{cc}{Y}_{in}\left(f\right)=\frac{\mathrm{jf}/f_{\mathrm{rc}}-{\left(f/f_{\mathrm{rc}}\right)}^2+f_s/2f_{\mathrm{rc}}\left(1-e^{-2\left(f_{\mathrm{rc}}+\mathrm{jf}\right)/f_s}\right)}{1+\mathrm{jf}/f_{\mathrm{rc}}-f_s/2f_{\mathrm{rc}}\left(1-e^{-2\left(f_{\mathrm{rc}}+\mathrm{jf}\right)/f_s}\right)}.Math.\frac{1}{R_s}& \left(3\right)\end{array}$

(64) The admittance is a function of f.sub.rc. To match the DC input admittance to 1/R.sub.s, Y.sub.in(0)=1/R.sub.s. Evaluating (3) at DC and equating it to 1/R.sub.s, the equation for f.sub.rc is

(65) $\begin{array}{cc}{e}^{-2f_{\mathrm{rc}}/f_s}+\frac{2f_{\mathrm{rc}}/f_s}{2}-1=0& \left(4\right)\end{array}$

(66) Solving this transcendental equation, results in f.sub.rc0.25f.sub.s and C.sub.s0.63/f.sub.sR.sub.s, so the C.sub.s needs to be tuned with different LO frequencies. Using (4) and given that exp(2f.sub.rc/f.sub.s) is small, the input admittance can now be simplified to:

(67) $\begin{array}{cc}{Y}_{in}\left(f\right)=\left(\frac{1+2{\left(f/f_{\mathrm{rc}}\right)}^2}{1+4{\left(f/f_{\mathrm{rc}}\right)}^2}+j\frac{4{\left(f/f_{\mathrm{rc}}\right)}^3}{1+4{\left(f/f_{\mathrm{rc}}\right)}^2}\right).Math.\frac{1}{R_s}& \left(5\right)\end{array}$

(68) At low frequencies (f<<f.sub.rc), the real part is dominant and equal to 1/R.sub.s. At high frequencies (f>>f.sub.rc), the imaginary part becomes larger, which can be modeled as a capacitor equal to C.sub.s. The input impedance of the SC front-end can thus be modeled as a resistor R.sub.m=R.sub.s in parallel with a capacitor C.sub.m=C.sub.s as shown in FIG. 7. Considering f.sub.rc0.25f.sub.s, Y.sub.in(f) can be normalized by f.sub.s.

(69) Turning to FIG. 8, as set forth above, the RF sampler includes switches s.sub.1 and s.sub.6 and capacitor C.sub.s, and can be modeled as a CT filter G(f) and an ideal sampler, as shown in FIG. 9. In some embodiments, the G(f) can be represented by the following equation:

(70) $\begin{array}{cc}G\left(f\right)=\frac{1}{1+\mathrm{jf}/f_{\mathrm{rc}}}.Math.\left[1-e^{-2\left(f_{{\mathrm{rc}}_{\mathrm{jf}}}\right)/f_s}\right]& \left(6\right)\end{array}$

(71) The first part of the right side of equation (6) (that is, the part to the left of the .Math.) is a first-order low-pass filter with a constant of R.sub.sC.sub.s (f.sub.rc=1/(2R.sub.sC.sub.s)) while the second part of the right side of equation (6) (that is, the part to the right of the .Math.) is a FIR filter with a delay of 1/f.sub.s. Considering f.sub.rc0.25f.sub.s, G(f) can be normalized by f.sub.s.

(72) FIG. 10 shows an example of G(f) and H(f) (=V.sub.in/V.sub.s) transfer curves in accordance with some embodiments. Because the input impedance is matched to R.sub.s in this example, the gain of H(f) at the LO frequency (f.sub.s/8) is 6 dB as in resistive matching, while G(f) is 2.2 dB. This means that the sampler provides a 3.8 dB passive gain (V.sub.s/V.sub.in) (in this example) because, when the switch s.sub.1 is turned ON, the C.sub.s voltage is charged from zero to V.sub.sp, while V.sub.in is the average voltage of the whole charging period as shown in the example V.sub.in transient wave form for a DC (0 Hz) source voltage V.sub.s in FIG. 11.

(73) During operation, the sampler exhibits characteristics of both a voltage sampler and an integration sampler.

(74) In a voltage sampler, a sampling capacitor voltage follows the source voltage when the switch is turned ON, and the high-frequency signals around the sampling frequency (and its harmonics) are folded into the desired signal band. In an integration sampler, when the switch is turned ON, a sampling capacitor voltage is the integral of the source current (I.sub.s=V.sub.s/R.sub.s). The integration sampler has intrinsic anti-aliasing filtering with nulls at n.Math.f.sub.f (where n is a non-zero integer).

(75) A difference between a voltage sampler and an integration sampler is that the integration sampler incorporates a FIR filter (e.g., like the second part of the right side of equation (6) (that is, the part to the right of the .Math.)). This is because, in a voltage sampler, the RC constant is relatively small (R.sub.sC.sub.s<<1/f.sub.s) and thus the FIR part in G(f) can be ignored. In an integration sampler, however, the RC constant is large (R.sub.sC.sub.s>>1/f.sub.s) and thus the FIR filter generates deep nulls at the sampling frequency (and its harmonics) which reduces aliasing.

(76) Because, in some embodiments of the front-end described herein, the RC constant is close to the sampling period, the sampler of the described front-end can exhibit characteristics of both a voltage sampler and an integration sampler. Using f.sub.rc0.25f.sub.s, the bandwidth of the RC-filtering part in G(f) is around 0.25f.sub.s. Also, the FIR filtering part in G(f) provides more attenuation around the sampling frequency and its harmonics, although the attenuation is lower than in a typical integration sampler. The G(f) transfer function in accordance with some embodiments is shown in FIG. 10. The G(f) provides rejection to reduce the signal and noise folding from n.Math.f.sub.sf.sub.s/8.

(77) In some embodiments, Gm cells 104 (FIG. 1) can be modeled as a DT mixer with a reconstruction circuit.

(78) The DT mixing can be expressed as: I.sub.mix.sub._.sub.{I,Q}[n]=V.sub.gm[n].Math.gm.sub.{I,Q}[mod(n, 8)+1], where mod(.Math.) is the modulus function. By scaling gm[i] as a DT sine wave, a down-converted {I, Q} signal can be obtained at the mixer output. In some embodiments, the gm factors gm[1] to gm[8] in the I path (i.e., the gm corresponding to the I path for each of the i banks) need to be sized as sin((i1).Math.4/), which are 0, 1, {square root over (2)}, 1, 0, 1, {square root over (2)}, 1, 0, while the gm factors gm[1] to gm[8] in the Q path (i.e., the gm corresponding to the Q path for each of the i banks) need to be sized as cos((i1).Math.4/) (as in a harmonic rejecting mixer (HRM)), which are 0, 1, {square root over (2)}, 1, 0, 1, {square root over (2)}, 1, 0. So, only the signal around f.sub.s/8 in the Nyquist bandwidth f.sub.s/2 will be down-converted to baseband. Non-idealities, like gain and phase mismatches, will reduce the harmonic rejection ratio (HRR) as in other HRM.

(79) In some embodiments, besides performing down-conversion, the Gm cells also convert the signal from the DT to the CT domain. The reconstruction can be implemented as a zero-order hold with a hold time of 8T.sub.s (T.sub.s=1/f.sub.s); the output current can be expressed as:
I.sub.out.sub._.sub.{I,Q}(t)=.sub.n=.sup.I.sub.mix.sub._.sub.{I,Q}[n].Math.rect((t4T.sub.snT.sub.s)/8T.sub.s),
where rect(.Math.) is the rectangular function.

(80) Combining anti-aliasing filtering, sampling, DT mixing with harmonic rejection and reconstruction, the conversion gain of the front-end can be represented by:

(81) $\mathrm{CG}\left(f_{in}\right)=\frac{V_{\mathrm{out}}\left(f_{in}-\frac{f_s}{8}\right)}{V_s\left(f_{in}\right)}=G\left(f_{in}\right).Math.\frac{1}{T_s}.Math.\frac{1}{2}\mathrm{gm}.Math.8T_s\sin c\left(\frac{f_{in}-f_s/8}{f_s/8}\right).Math.R4G\left(f_{in}\right)\mathrm{gmR},$
where f.sub.in is the input RF frequency around LO frequency of f.sub.s/8, gm is the transconductance of the Gm cell with a size of {square root over (2)}, and R is the feedback resistor in the TIA. The sinc function approximates to 1 for f.sub.in close to f.sub.s/8.

(82) The DT IIR filter includes capacitors C.sub.s, C.sub.h1, C.sub.h2, and C.sub.h3 and switches s.sub.2, s.sub.3, s.sub.4, and s.sub.6 as shown in FIG. 12. In some embodiments, this filter can be implemented by charge rotating. For example, in each cycle n of 8/f.sub.s, after each capacitor C.sub.s is charged to the finite state V.sub.sp,0 during its sampling phase (e.g., phase p.sub.1 for Bank #1), the capacitor C.sub.s is sequentially connected to capacitors C.sub.h1, C.sub.h2, and C.sub.h3, the input node of the Gm cell, and ground (e.g., during phases p.sub.2, p.sub.3, p.sub.4, p.sub.5, and p.sub.7, respectively, for Bank #1). When C.sub.hi (e.g., C.sub.h1, C.sub.h2, or C.sub.h3) connects to C.sub.s, the C.sub.s voltage and C.sub.hi voltage after charge sharing are:
V.sub.sp,i[n]=V.sub.h,i[n]=V.sub.h,i[n8]+(1)V.sub.sp,i1[n1],(8)
where =C.sub.hi/(C.sub.hi+C.sub.s), i={1,2,3}, V.sub.h,i is the C.sub.hi voltage, V.sub.sp,i is the C.sub.s voltage after it connects to C.sub.hi. Writing (8) in the z domain with z=exp(j2f/f.sub.s), the C.sub.s voltage can be expressed as

(83) $\begin{array}{cc}{V}_{\mathrm{sp},i}\left(z\right)=\frac{1-}{1-z^{-8}}.Math.z^{-1}.Math.V_{\mathrm{sp},i-1}\left(z\right)& \left(9\right)\end{array}$

(84) This shows that each C.sub.hi provides a first-order IIR filtering. If C.sub.hi is not connected, the transfer function (9) is just a delay (z.sup.1). The filter order can thus be tuned by enabling or disabling the clock signal for s.sub.i connected to C.sub.hi. When the clock signal is disabled, its clock driver can be turned off to save power providing a trade-off between filter order and power consumption.

(85) Since V.sub.gm[n]=V.sub.sp,3[n1], the transfer function of the whole IIR filter can be represented by:

(86) $\begin{array}{cc}\frac{V_{\mathrm{gm}}\left(z\right)}{V_{\mathrm{sp}}\left(z\right)}={\left(\frac{1-}{1-z^{-8}}\right)}^n.Math.Z^{-4}& \left(10\right)\end{array}$
where V.sub.sp=V.sub.sp,0, and n is the number of C.sub.hn being connected, n={0,1,2,3}, which is also the IIR filter order. FIG. 13 shows an example of calculated IIR filter transfer curves in the Nyquist bandwidth for different filter orders with f.sub.s=4 GHz, C.sub.s0.63/f.sub.sR.sub.s, and C.sub.hn=50 pF, n={0,1,2,3}. The DC and even-order LO harmonic responses can be removed using differential circuits.

(87) In a DT IIR filter, the bandwidth changes with sampling frequency, since it is proportional to f.sub.sC.sub.s/8C.sub.hn. In some embodiments, C.sub.s is tuned to 0.63/f.sub.sR.sub.s to achieve the impedance matching. So, the bandwidth is proportional to 0.63/8(R.sub.sC.sub.hn) and independent of f.sub.s. Thus the filter bandwidth doesn't change when changing LO frequencies (f.sub.lo=f.sub.s/8) and can be tuned by C.sub.hn. In some embodiments, C.sub.hn is fixed.

(88) In the SC front-end, in some embodiments, the added noise is mainly the thermal noise of the switches. FIG. 14 shows an illustrative representation of the noise sources of the SC front-end without filtering in accordance with some embodiments. Switch s.sub.i is modeled as an ideal switch in series with a parasitic resistor R.sub.on,i and a noise voltage V.sub.ni. C.sub.h,gm is the parasitic capacitor of the Gm cell. Since there is no overlap between the clock signals driving s.sub.1i in the eight SC banks, all the white noise source V.sub.n1i can be merged into a single white noise source, V.sub.n1, as shown in FIG. 15. The sampling switch, s.sub.1, noise is thus added to the source noise V.sub.ns as shown in FIG. 18 since R.sub.on is in series with R.sub.s. The intrinsic antialiasing filter, G(f), reduces the high-frequency noise folding.

(89) The resetting-switch, s.sub.6, noise is first sampled on C.sub.s. Together, C.sub.s and s.sub.6 are a voltage sampler (R.sub.on,6C.sub.s<<1/f.sub.s) so that the high-frequency noise is folded into the signal band after sampling, resulting in a nearly white noise. The noise spectral density is the total mean-square (MS) noise voltage, kT/C.sub.s, divided by Nyquist bandwidth, f.sub.s/2. Then, this sampled noise voltage is partially dumped by R.sub.s when s.sub.1 is turned ON for a duration of 1/f.sub.s and the noise voltage is reduced by a factor of exp(2f.sub.rf/f.sub.s). After that, the noise voltage is added to the desired signal as shown in FIG. 18. The noise spectral density at the Gm input node in the signal band due to V.sub.n6 is:

(90) $\begin{array}{cc}\stackrel{\_}{V_{\mathrm{gm},n6}^2}=\frac{2\mathrm{kT}}{C_s{f}_s}{e}^{-1/f_s{C}_s{R}_s}.Math.f& \left(11\right)\end{array}$

(91) Since the noise analyses of the switch s.sub.5 and the switches in the IIR filter are related, the same equivalent schematic in FIG. 16 can be used to analyze the noise transfer functions of these switches; V.sub.n,i is the noise voltage source of switch s.sub.i, i={2,3,4,5}; for the s.sub.5 noise analysis, C.sub.h is C.sub.h,gm and for the noise analysis of the s.sub.j+1 in the IIR filter, C.sub.h is C.sub.hj, j={1,2,3}. When s.sub.i is turned ON, V.sub.n,i is sampled on C.sub.s in series with C.sub.h. Let V.sub.n,sp be the sampled noise voltage between node A and B in FIG. 16 with an MS value of kT/C.sub.s, where =C.sub.h/(C.sub.h+C.sub.s). The DT voltages on C.sub.h and C.sub.s are
V.sub.1[n]=(1)V.sub.n,sp[n]+V.sub.1[n1],V.sub.2[n]=V.sub.n,sp[n]+V.sub.1[n1](12)

(92) Solving (12), results in:

(93) 0$\begin{array}{cc}{H}_1\left(z\right)=\frac{V_1\left(z\right)}{V_{n,\mathrm{sp}}\left(z\right)}=-\frac{1-}{1-z^{-8}},H_2\left(z\right)=\frac{V_2\left(z\right)}{V_{n,\mathrm{sp}}\left(z\right)}=\frac{1-z^{-8}}{1-z^{-8}}.& \left(13\right)\end{array}$

(94) H.sub.1 is the s.sub.5 noise transfer function and is an IIR bandpass filter with a 0 dB in-band gain. H.sub.2 is the noise transfer function for the switches in the IIR filter and is a notch filter centered at the desired signal band. An example of the calculated H.sub.1 and H.sub.2, with f.sub.s=4 GHz and C.sub.h=50 pF, are shown in FIG. 17.

(95) The s.sub.5 noise is added to the desired signal at the Gm input node, as shown in FIG. 18 with an in-band-noise spectral density of

(96) $\begin{array}{cc}\stackrel{\_}{V_{\mathrm{gm},n5}^2}=\frac{2\mathrm{kT}}{{}_{\mathrm{gm}}{C}_s{f}_s}.Math.f& \left(14\right)\end{array}$
calculated using (13) where .sub.gm=C.sub.h,gm/(C.sub.h,gm+C.sub.s).

(97) The switch noise from the IIR filter is added to the desired signal when being sampled on C.sub.s with the transfer function H.sub.2. The in-band filter noise is first reduced by the IIR notch filtering H.sub.2, then propagated to the output as shown in FIG. 18. It can thus be ignored, and the noise factor (NF) will remain almost the same when increasing filter order.

(98) Including the Gm cell noise I.sub.n,gm.sup.2=4kT(2+2{square root over (2)})gm, the front-end's total double-sideband (DSB) noise factor at the target signal frequency (f.sub.lo=f.sub.s/8) is

(99) $\begin{array}{cc}F=1+\frac{R_{\mathrm{on},1}}{R_s}+\frac{1}{2R_s{.Math.G\left(f_s/8\right).Math.}^2}\left[\frac{e^{-1/f_s{R}_s{C}_s}}{f_s{C}_s}+\frac{1}{{}_{\mathrm{gm}}{f}_s{C}_s}+\frac{\left(1+\sqrt{2}\right)}{8\mathrm{gm}}\right]& \left(15\right)\end{array}$

(100) Using C.sub.s0.63/f.sub.sR.sub.s and G(f.sub.s/8) from equations (6) and (15) can be simplified as

(101) $\begin{array}{cc}F=1+\frac{R_{\mathrm{on},1}}{R_s}+0.27+1.32/{}_{\mathrm{gm}}+\frac{0.25}{{\mathrm{gmR}}_s}& \left(16\right)\end{array}$

(102) Since R.sub.on,1 is relatively small and .sub.gm<1, the front-end noise factor is dominated by fourth term (i.e., the noise from s.sub.5). The NF lower limit is 4.13 dB when R.sub.on,1=0, .sub.gm=1, and gm=+.

(103) In accordance with some embodiments, to improve blocker compression, CMOS switches (FIG. 19) can be used instead of NMOS switches or PMOS switches. NMOS and PMOS transistors in the CMOS switches can have the same size of W/L=150 m/40 nm. V.sub.SW=V.sub.DD and V.sub.SWb=V.sub.SS when the switch is turned on; V.sub.SW=V.sub.SS and V.sub.SWb=V.sub.DD when the switch is turned OFF.

(104) An example of a schematic of an SC RF front-end in accordance with some embodiments is shown in FIG. 20.

(105) As shown, the front-end includes SC circuits, baseband Gm cells, TIAs, and a clock generator. In a fully differential architecture, a differential NPF is used at the RF input and the two capacitors Cs with opposite phases can share the same C.sub.h in the ER filter to eliminate the DC and even-order LO harmonic responses. The corresponding two sections in FIG. 1 (e.g., sections 108 and 110) are merged into one bank in FIG. 20; as a result, eight capacitors are needed for C.sub.s and four capacitors are needed for each C.sub.h. The NMOS and PMOS in the CMOS switches are sized equally to reduce the charge injection and clock feedthrough. The R.sub.on of the sampling switches s.sub.1 and the output switches s.sub.5 is 14, while the other switches are sized for 20. The C.sub.s is implemented with a metal-oxide-metal (MoM) capacitor bank with switches to ground. The C.sub.s tuning range is 1-16 pF with a 1 pF step. The C.sub.hs are identical with an effective single-ended capacitance of 50 pF and are realized with a combination of differential MoM capacitors and MOS capacitors to ground.

(106) The Gm cells combine the four-phase output signals from the SC circuits; each two capacitors C.sub.s with opposite phases share a single Gm cell which changes the hold time to 4T.sub.s when converting the DT signal to CT.

(107) In some embodiments, the Gm cells can be realized by CMOS inverters with a tail current operating from a 1.6 V supply. The Gm input-common-mode voltage can be set by V.sub.CM in the reset phase. Common-mode feedback circuits can set the output common-mode voltage to 0.8 V. A 5:7 size ratio can be used to approximate the 1:{square root over (2)} ratio for the harmonic recombination to eliminate the harmonic down-conversion. Dummy Gm cells can be used to balance the load of the previous stage. The transconductance of the size-5 Gm cell can be 40 mS. To reduce the flicker noise, a large transistor can be used with a length equal to 1 m, resulting in 40 pF input-parasitic capacitance. Since the desired signal is already down-converted when it reaches the input of the Gm cell, this parasitic capacitance should not limit the front-end's frequency range.

(108) In some embodiments, each Gm cell can be tuned with a nine-bit control code to calibrate the harmonic rejection ratio (HRR). During the calibration, a harmonic signal can be provided at the RF input and the Gm cells can be externally tuned to minimize the baseband output power.

(109) In some embodiments, the clock divider can generate eight non-overlapping clock signals with a duty cycle and drive the switch drivers. The drivers for the switches in the NPF and IIR filter can be turned ON or OFF to change the filter order. The switch drivers can be DC coupled to the switches. In some embodiments, since the front-end's V.sub.CM is 0.8 V, and the rail-to-rail voltage is 1.2 V, the V.sub.DD and V.sub.SS of the clock generator can be chosen to be 1.4 V and 0.2 V respectively to make sure V.sub.CM=(V.sub.DDV.sub.SS)/2.

(110) FIG. 21 shows an example of a block diagram of the clock divider in accordance with some embodiments. The latch-based counter generates an 8-phase -duty-cycle clock signal X<7:0>. The latch output signals are combined by an array of AND gates to generate a -duty-cycle clock Y<7:0> for the retiming circuit. After retiming by the 2-phase non-overlapping clocks CA and CB, the 8-phase -dutycycle non-overlapping clock P<7:0> can be generated. The re-timing scheme relaxes the noise requirements of the counter and the AND-gate array. The complementary clocks for CMOS switches can be generated by clock drivers and can be enabled with the signal EN as shown in FIG. 22. LO.sub.p and LO.sub.n drive the PMOS transistor and the NMOS transistor in the switch respectively. The digital buffer in the LO.sub.n branch can be used to equalize the delay of LO.sub.p and LO.sub.n, and the delay mismatch can be smaller than the gap between two non-overlapping clocks.

(111) In accordance with some embodiments, a chopping SC receiver front-end with integrated blocker detector is provided. The integrated blocker detector detects the envelope of an unknown OB blocker, so that the filter order can be adapted to the blocker power.

(112) As shown in FIG. 23, in accordance with some embodiments, a chopping SC receiver front-end can include eight time-interleaved SC banks. As described above, RF impedance matching and sampling can be achieved by capacitors C.sub.s with switches s.sub.1 and s.sub.5. In each SC bank, the RF input signal can be down-converted to baseband during sampling, then amplified by eight Gm cells. The transconductances of the Gm cells can be scaled as a sine wave to achieve 3rd and 5th order LO harmonic rejection.

(113) Unlike what is shown in FIG. 1, however, the switch at the input to the Gm cells can be omitted in the chopping SC receiver front-end and moved to the output of the Gm cells. This can cause noise to be reduced. Also unlike what is shown in FIG. 1, to reduce in-channel flicker noise, input and output choppers can be provided in the chopping SC receiver front-end. Further unlike what is shown in FIG. 1, a blocker detector can be provided and attached to the last IIR filter capacitor C.sub.h2 to measure the filtered Gm input voltage swing.

(114) During operation, the choppers to the left of capacitors Cs can up-convert the desired signal with chopping frequency f.sub.chop, and the choppers to the right of the Gms can down-convert the desired signal back to baseband while up-converting the Gm flicker noise to f.sub.chop. The choppers attached to C.sub.h1 and C.sub.h2 ensure the IIR filter transfer function is maintained while chopping.

(115) In some embodiments, when driving the switches by 1/16 duty-cycle 16-phase non-overlapping clocks, the choppers can be merged with the SC circuits as shown in FIG. 24. In some embodiments, for example, chopping can then be achieved by sampling the RF input signal at each bank in phases p.sub.i (e.g., phase p.sub.1 for Bank #1, phase p.sub.2 for Bank #2, etc.) with one polarity and in phases p.sub.i+8 (e.g., phase p.sub.9 for Bank #1, phase p.sub.9 for Bank #2, etc.) with the opposite polarity. For a sampling frequency f.sub.s, the LO frequency is f.sub.lo=f.sub.s/8 and f.sub.chop=f.sub.s/16.

(116) An example of a more detailed schematic for the implementation in FIG. 24 is illustrated in FIG. 25 in accordance with some embodiments. As shown, Cs capacitor pairs with sampling phase p.sub.i and p.sub.i+4 share the same C.sub.hs in the N-path filters and the IIR filters to eliminate the DC and even-order LO harmonic responses.

(117) In some embodiments, the switches can be implemented with CMOS transmission gates, as illustrated in FIG. 19.

(118) The Gm cells with output switches act as switched Gm cells and the DC current of the Gm cells can be cut off when the switches are OFF to save power. As example of a Gm cell in accordance with some embodiments is shown in FIG. 27.

(119) The on-chip LO divider can be used to generate the 16-phase non-overlapping clock signals.

(120) An example of a blocker envelope detector in accordance with some embodiments is shown in FIG. 26. The blocker envelope detector includes eight AC coupled common-source transistors operating in weak inversion with resistor and off-chip capacitor loads and a replica.

(121) In accordance with some embodiments, a SC RF front-end can be implemented with capacitor stacking. An example of a schematic of a Bank #1 of such a front-end in accordance with some embodiments is illustrated in FIG. 29. As shown, capacitor C.sub.S is divided into two capacitors, each labelled C.sub.s/2 and having half of the capacitance of C.sub.s. MoM and MiM capacitors can be used in some embodiments. Switches s.sub.7-s.sub.9 are added for capacitor stacking. s.sub.8 is driven by clock signal p.sub.5, while s.sub.7 and s.sub.9 are driven by inverted p.sub.5 clock.

(122) FIG. 30 shows an example of the operation of a capacitor stacking SC RF front-end in accordance with some embodiments. As shown, in sampling phase (p.sub.1), the RF signal is sampled on two the sampling capacitors C.sub.s/2. The sampled voltage is V.sub.sp. In the passive gain phase (p.sub.5), the two capacitors are stacked up, the signal is doubled; the voltage propagated to the Gm input node is 2V.sub.sp. The passive gain reduces the noise contribution of the following stages. In the reset phase (p.sub.7), the sampling capacitor voltage is reset to the ground voltage.

(123) In some embodiments, NMOS and PMOS transistors can be used as sampling capacitor Cs as shown in FIG. 31. The capacitance of these MOS capacitors is changed with source voltage to achieve a parametric amplification. Both NMOS and PMOS are used to make sure the common mode voltage does not change when changing source voltage. The source node of NMOS M1 is connected to clock signal p.sub.5, and the source node of PMOS M2 is connected to inverted clock signal p.sub.5. The source and the drain of the MOS transistors are shorted.

(124) An example of the operation of the front-end illustrated in FIG. 32 is now described in connection with FIG. 31 in accordance with some embodiments. In the sampling phase (p.sub.1), the source voltage of M1 is V.sub.GND, while the source voltage of M2 is V.sub.DD. Both of the two MOS transistors are in inversion mode. The capacitance is C.sub.s. The RF signal is sampled on the MOS capacitor; the sampled voltage is V.sub.sp. In parametric gain phase (p.sub.5), the source voltages of M1 and M2 are switched to V.sub.DD and V.sub.GND respectively. The MOS transistors are working in depletion mode in which the capacitance is smaller than inversion mode, which is C.sub.s/a (a>0). Since the charge on the sampling capacitor should be a constant, the voltage propagated to Gm input is a.Math.V.sub.sp.

(125) In some embodiments, to compensate for non-linear behavior in the transistor capacitors of FIG. 31, complementary transistor capacitors can be put in parallel with the transistor capacitors of FIG. 31, as shown in FIG. 33. For example, a PMOS M3 can be put in parallel with M1 and the source voltage in sampling, filtering, and reset phases can be set to V.sub.THN+V.sub.THP to compensate non-linear behavior of M1, where V.sub.THN and V.sub.THP are the threshold voltages of the NMOS and PMOS transistors. Likewise, NMOS M4 can be put in parallel with M2 to compensate the non-linear behavior of M2 and the source voltage can be set to V.sub.DDV.sub.THNV.sub.THP. The source nodes of the NMOS transistor capacitors (M1 and M4) can be connected to V.sub.DD and source nodes of PMOS transistor capacitors (M2 and M3) can be connected to V.sub.GND in parametric gain phase.

(126) The provision of the examples described herein (as well as clauses phrased as such as, e.g., including, and the like) should not be interpreted as limiting the claimed subject matter to the specific examples; rather, the examples are intended to illustrate only some of many possible aspects. It should also be noted that, as used herein, the term mechanism can encompass hardware, software, firmware, or any suitable combination thereof.

(127) Although the invention has been described and illustrated in the foregoing illustrative embodiments, it is understood that the present disclosure has been made only by way of example, and that numerous changes in the details of implementation of the invention can be made without departing from the spirit and scope of the invention, which is limited only by the claims which follow. Features of the disclosed embodiments can be combined and rearranged in various ways.