INTEGRATED CAPACITANCE MEASUREMENT

Abstract

An apparatus for measuring the capacitance to be measured is proposed. It comprises a first sine-wave oscillator, the measuring oscillator, and a second sine-wave oscillator, the reference oscillator. The frequency of the output signal of the measuring oscillator, hereinafter also referred to as measuring frequency, is dependent on the capacitance to be measured. The frequency of the output signal of the reference oscillator, hereinafter also referred to as reference frequency, is dependent on a reference capacitance. The apparatus comprises a sub-apparatus which produces the ratio of the frequency value of the frequency of the output signal of the reference oscillator and the frequency value of the frequency of the output signal of the measuring oscillator and subsequently squares this ratio to provide the result of this squaring as a measured value.

Claims

1.-8. (canceled)

9. An apparatus for measuring a capacitance to be measured, comprising: a sine-wave measuring oscillator adapted to be coupled with the capacitance to be measured; a sine-wave reference oscillator adapted to be coupled with a reference capacitance; wherein a measuring frequency of a measuring oscillator output signal of the sine-wave measuring oscillator is determined at least in part by the capacitance to be measured, wherein a reference frequency of a reference oscillator output signal of the sine-wave reference oscillator is determined at least in part by the reference capacitance; and an evaluation unit which produces a ratio of the reference frequency of the reference oscillator output signal and the measuring frequency of the measuring oscillator output signal and squares the ratio, wherein a result of squaring the ratio represents a value of the capacitance to be measured.

10. The apparatus according to claim 9, wherein the sine-wave measuring oscillator and the sine-wave reference oscillator respectively comprise same component parts except for the capacitance to be measured and the reference capacitance.

11. The apparatus according to claim 9, wherein each of the sine-wave measuring oscillator and the sine-wave reference oscillator are respectively configured as one of a ring oscillator and a state-variable oscillator.

12. The apparatus according to claim 9, wherein each of the sine-wave measuring oscillator and the sine-wave reference oscillator respectively comprise a control of an amplitude of a signal available at the capacitance to be measured and at the reference capacitance for preventing an overdrive.

13. The apparatus according to claim 12, wherein an overdrive of the control of the amplitude of the respective signal is adapted to be used for recognizing external sources of interference.

14. The apparatus according to claim 9, wherein the apparatus is adapted to be operated at one of (1) more than one reference frequency of the reference oscillator output signal, (2) more than one measuring frequency of the measuring oscillator output signal, and (3) more than one reference frequency of the reference oscillator output signal and more than one measuring frequency of the measuring oscillator output signal.

15. The apparatus according to claim 14, wherein: the measuring frequency of the measuring oscillator output signal of the sine-wave measuring oscillator is dependent on a first resistor and a first second resistor within the sine-wave measuring oscillator; the reference frequency of the reference oscillator output signal of the sine-wave reference oscillator is dependent on a second first resistor and a second resistor within the sine-wave reference oscillator; the first resistor and second first resistor have a first same value; the first second resistor and second resistor have a second same value; and at least (1) both of the first resistor and second first resistor or (2) both of the first second resistor and second resistor in the respective sine-wave measuring oscillator and the sine-wave reference oscillator are adapted to be switched over or changed in a same manner.

16. A method for determining a value of a capacitance to be measured, comprising: generating a sinusoidal first oscillator signal by means of a measuring oscillator whose measuring frequency is dependent on the value of the capacitance to be measured; generating a sinusoidal second oscillator signal by means of a reference oscillator whose reference frequency is dependent on a reference capacitance; generating a first digital or binary data flow from the sinusoidal first oscillator signal, by means of a first analog-to-digital converter, wherein the first digital or binary data flow assumes one of a first and a second logic state; generating a second digital or binary data flow from the sinusoidal second oscillator signal, by means of a second analog-to-digital converter wherein the second digital or binary data flow assumes one of a first and a second logic state; generating high-frequency counting pulses, by means of a high-frequency oscillator; resetting a first counter for counting a first number of high-frequency counting pulses during a second logic state of the first digital flow; resetting a second counter for counting a second number of high-frequency counting pulses during a second logic state of the second digital flow; incrementing, once per each high-frequency counting pulse, during a first time when the first digital flow is in the second logic state, the first counter to generate a first counting value; incrementing, once per each high-frequency counting pulse, during a second time when the second digital flow is in the second logic state, the second counter to generate a second counting value; setting a first result value to be equal to the first counting value when the logic state of the first digital or binary data flow changes from the second logic state to the first logic state; setting a second result value to be equal to the second counting value when the logic state of the second digital or binary data flow changes from the second logic state to the first logic state; dividing, by a division block, the second result value by the first result value to generate a result of the division; squaring, by a squaring block, the result of the division, to generate a result of the squaring; and outputting or using the result of the squaring as a measured value.

17. The method of claim 16, further comprising: resetting the first counting value in the first counter subsequent to setting the first result value to be equal to the first counting value; and resetting the second counting value in the second counter subsequent to setting the second result value to be equal to the second counting value.

Description

LIST OF THE FIGURES

[0128] FIG. 1 shows a schematic simplified view of the proposed apparatus for determining the capacitance (C.sub.var) to be measured.

[0129] FIG. 2 shows a schematic simplified view of a suitable sine-wave oscillator as a measuring oscillator (Q.sub.MEAS).

[0130] FIG. 3 shows a schematic simplified view of a suitable sine-wave oscillator as a reference oscillator (Q.sub.REF).

[0131] FIG. 4 shows a schematic simplified view of the proposed apparatus for determining the capacitance ratio of a pair of capacitances (C.sub.var1, C.sub.var2) to be measured.

[0132] FIG. 5 shows a schematic simplified view of a suitable sine-wave oscillator (Q.sub.MEAS) matching FIG. 4.

[0133] FIG. 6 shows a schematic simplified view of a suitable sine-wave oscillator (Q.sub.REF) matching FIG. 4.

[0134] FIG. 7 corresponds to FIG. 1 with additional amplitude controls (AC.sub.REF, AC.sub.MEAS).

[0135] FIG. 8 shows a schematic simplified view of a suitable measuring oscillator (Q.sub.MEAS) matching FIG. 7 as an example of a possible amplitude-controllable sine-wave oscillator.

[0136] FIG. 9 shows a schematic simplified view of a suitable reference oscillator (Q.sub.REF) matching FIG. 7 as an example of a possible amplitude-controllable sine-wave oscillator.

[0137] FIG. 10 shows a suitable amplitude control (AC.sub.MEAS) for the measuring oscillator (Q.sub.MEAS) corresponding to FIG. 7.

[0138] FIG. 11 shows a suitable amplitude control (AC.sub.REF) for the reference oscillator (Q.sub.REF) corresponding to FIG. 7.

[0139] FIG. 12 shows a schematic simplified view of a suitable sine-wave oscillator using the example of the measuring oscillator (Q.sub.MEAS) having an additional fourth resistor (R4).

[0140] FIG. 13 shows a schematic simplified view of a suitable sine-wave oscillator using the example of the reference oscillator (Q.sub.REF) having an additional adjustable fifth resistor (R5) and an additional capacitance (C3).

[0141] FIG. 14 shows the sensitivity curve of the oscillator circuits (y-axis) as a function of the interfering frequency (f.sub.s) (x-axis).

[0142] FIG. 15 serves for elucidating the frequency hopping.

LIST OF REFERENCE NUMERALS

[0143] / Division block. The division block divides the second counter reading of the second output register of the second counter preferably by the first counter reading in the first output register of the first counter (CNT1) and outputs the result. This function can also be performed by a computer, in particular a microcomputer. This computer may be the computer which can possibly perform the function of the squaring block (2). [0144] 2 Squaring block. The squaring block squares the result signal of the division block (/) to provide the capacitance result (Out). This function can also be performed by a computer, in particular a microcomputer. This computer may be the computer which can possibly perform the function of the division block (2). [0145] A Frequency range (approximate representation) in which an interference leads to the amplitude control leaving its operating range; [0146] AC.sub.MEAS Amplitude control of the measuring oscillator (Q.sub.MEAS); [0147] AC.sub.REF Amplitude control of the reference oscillator (Q.sub.REF); [0148] B Frequency range (approximate representation) in which the measuring signal is strongly changed (snapped onto the interfering frequency) but no interference can be directly detected. [0149] C2 Second capacitance. The second capacitance is preferably integrated into the integrated microelectronic circuit (IC). [0150] C3 Third capacitance; [0151] CNT1 First counter. The first counter counts the high-frequency counting pulses of the high-frequency oscillator (HF-OSC) as long as the third digital or binary data flow (dsR3) has a first logic level. When a second logic level appears at the third digital or binary data flow (dsR3) the first counter stops counting and the first counting result appears at the output of the first counter. When a first logic level appears again at the third digital or binary data flow (dsR3) the first counter starts counting again, preferably at zero. Preferably, the preceding first counting result is continued to be output. [0152] CNT2 Second counter. The second counter counts the high-frequency counting pulses of the high-frequency oscillator (HF-OSC) as long as the fourth digital or binary data flow (ds4) has a first logic level. When a second logic level appears at the fourth digital or binary data flow (ds4) the second counter stops counting and the second counting result appears at the output of the second counter. When a first logic level appears again at the fourth digital or binary data flow (ds4) the second counter starts counting again, preferably at zero. Preferably, the preceding second counting result is continued to be output. [0153] ck Clock input of a sample-and-hold circuit (S&H); [0154] coeff Coefficient; [0155] C.sub.ref Reference capacitance; [0156] C.sub.ref1 First reference capacitance; [0157] C.sub.ref2 Second reference capacitance; [0158] C.sub.var Capacitance to be measured; [0159] C.sub.var1 First capacitance to be measured; [0160] C.sub.var2 Second capacitance to be measured; [0161] D1 First divisor. The first divisor divides the frequency of the first digital or binary data flow (ds1) by a factor n and generates the third digital or binary data flow (dsR3). [0162] D2 Second divisor. The second divisor divides the frequency of the second digital or binary data flow (ds2) by a factor m and generates the fourth digital or binary data flow (ds4). [0163] Det Second terminal of the measuring oscillator (Q.sub.MEAS); [0164] ds1 First digital or binary data flow. The first digital or binary data flow is preferably generated by the first analog-to-digital-converter (INV1). [0165] ds2 Second digital or binary data flow. The second digital or binary data flow is preferably generated by the second analog-to-digital-converter (INV2). [0166] ds3 Third digital or binary data flow. The third digital or binary data flow is preferably generated by the first divisor (D1). [0167] ds4 Fourth digital or binary data flow. The fourth digital or binary data flow is preferably generated by the second divisor (D2). [0168] f.sub.MEAS Frequency of the first oscillator signal (S.sub.MEAS); [0169] f.sub.MEAS1 First frequency of the first oscillator signal (S.sub.MEAS) and first measuring frequency; [0170] f.sub.MEAS2 Second frequency of the first oscillator signal (S.sub.MEAS) and second measuring frequency; [0171] f.sub.MEAS3 Third frequency of the first oscillator signal (S.sub.MEAS) and third measuring frequency; [0172] f.sub.REF Frequency of the second oscillator signal (S.sub.REF); [0173] f.sub.REF1 First frequency of the second oscillator signal (S.sub.REF) and first reference frequency; [0174] f.sub.REF2 Second frequency of the second oscillator signal (S.sub.REF) and second reference frequency; [0175] f.sub.REF3 Third frequency of the second oscillator signal (S.sub.REF) and third reference frequency; [0176] f.sub.s Interfering frequency; [0177] GC1 Amplitude control of the measuring oscillator (Q.sub.MEAS); [0178] GC2 Amplitude control of the reference oscillator (Q.sub.REF); [0179] HF-OSC High-frequency oscillator which generates high-frequency counting pulses. Preferably, the frequency of the high-frequency counting pulses exceeds the measuring frequency (f.sub.MEAS) and the reference frequency (f.sub.REF) many times over. [0180] INV1 First analog-to-digital converter. It is particularly preferred that the first analog-to-digital converter is an inverter. [0181] INV2 Second analog-to-digital converter. It is particularly preferred that the second analog-to-digital converter is an inverter. [0182] LSB Least significant bit; [0183] LPF1 First low pass filter; [0184] LPF2 Second low pass filter; [0185] NA Desired useful amplitude; [0186] N1 First terminal of the reference oscillator (Q.sub.REF); [0187] N1a First terminal of the reference oscillator (Q.sub.REF); [0188] N1b Third terminal of the reference oscillator (Q.sub.REF); [0189] N2 Second terminal of the reference oscillator (Q.sub.REF); [0190] NR1 Adjustable virtual negative resistor; [0191] Q.sub.MEAS Measuring oscillator; [0192] Q.sub.REF Reference oscillator; [0193] R1 First resistor; [0194] R2 Second resistor; [0195] R3 Third resistor; [0196] R4 Fourth resistor; [0197] R5 Fifth resistor; [0198] R6 Controlled sixth resistor; [0199] SA Interfering amplitude at the internal reference voltage grid; [0200] S&H Sample-and-hold circuit; [0201] S.sub.MEAS First oscillator signal. The first oscillator signal is the output signal of the measuring oscillator (Q.sub.MEAS). [0202] S.sub.REF Second oscillator signal. The second oscillator signal is the output signal of the reference oscillator (Q.sub.REF). [0203] V1 First amplifier; [0204] V2 Second amplifier; [0205] V3 Third amplifier; [0206] V4 Fourth amplifier; [0207] V5 Fifth amplifier; [0208] V6 Sixth amplifier; [0209] Vamp Intermediate value signal; [0210] Var First terminal of the measuring oscillator (Q.sub.MEAS); [0211] Van First terminal of the measuring oscillator (Q.sub.MEAS); [0212] Var2 Third terminal of the measuring oscillator (Q.sub.MEAS); [0213] vin Input of the sample-and-hold circuit (S&H); [0214] vsh Output signal (vsh) of the sample-and-hold circuit; [0215] Vsoll_amp Setpoint value.