Long-term implantable silicon carbide neural interface device using the electrical field effect

Abstract

Field effect devices, such as capacitors and field effect transistors, are used to interact with neurons. Cubic silicon carbide is biocompatible with the neuronal environment and has the chemical and physical resilience required to withstand the body environment and does not produce toxic byproducts. It is used as a basis for generating a biocompatible semiconductor field effect device that interacts with the brain for long periods of time. The device signals capacitively and receives signals using field effect transistors. These signals can be used to drive very complicated systems such as multiple degree of freedom limb prosthetics, sensory replacements, and may additionally assist in therapies for diseases like Parkinson's disease.

Claims

1. An implantable neural interface device, the device comprising: a control unit; at least one substantially planar neural probe coupled to the control unit, each of the at least one substantially planar neural probes comprising; at least one neural tissue stimulation device comprising at least one electrolyte insulator semiconductor capacitor (EISCap) having a cubic silicon carbide (3CSiC) base and a biocompatible and chemically resistant gate insulator, wherein neural tissue in contact with the electrolyte insulator semiconductor capacitor (EISCap) forms a gate conductor to generate an electric field to stimulate the neural tissue at least partially surrounding the at least one substantially planar neural probe; and at least one neural tissue stimulation receiving device comprising at least one field effect transistor having a cubic silicon carbide (3CSiC) base, wherein neural tissue in contact with the at least one field effect transistor forms a gate conductor and wherein the at least one neural tissue stimulation receiving device receives ionic changes generated by the neural tissue resulting from the electric field stimulation by the at least one neural tissue stimulation device.

2. The device of claim 1, wherein the control unit is hermetically sealed.

3. The device of claim 2, wherein the conductive network is formed of graphene or pyrolized polymers.

4. The device of claim 1, wherein the control unit comprises circuitry selected from the group consisting of control circuitry, routing circuitry, signal generation circuitry, signal processing circuitry, wireless communication system circuitry and power system circuitry.

5. The device of claim 4, wherein the power system circuitry comprises a power supply selected from the group consisting of a rechargeable battery supply and a wireless power reception supply.

6. The device of claim 4, wherein the conductive network is formed of graphene or pyrolized polymers.

7. The device of claim 1, wherein the gate insulator is silicon carbide.

8. The device of claim 7, wherein the silicon carbide is selected from the group consisting of amorphous silicon carbide and polycrystalline amorphous silicon carbide.

9. The device of claim 1, wherein the electrolyte insulator semiconductor capacitor further comprises a conductive network.

10. The device of claim 1, wherein the field effect transistor further comprises a conductive network.

11. The device of claim 1, wherein the field effect transistor is a junction field effect transistor (JFET) and wherein the JFET does not include a gate insulator.

12. The device of claim 1, wherein the field effect transistor is an electrolyte insulator semiconductor field effect transistor (EISFET).

13. The device of claim 1, wherein the gate insulator is diamond.

14. The device of claim 13, wherein the diamond is selected from the group consisting of single crystalline diamond, polycrystalline diamond, nanocrystalline diamond and ultracrystalline diamond.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) For a fuller understanding of the nature and objects of the invention, reference should be made to the following detailed disclosure, taken in connection with the accompanying drawings, in which:

(2) FIG. 1 is a perspective view of the novel structure in accordance with an embodiment of the present invention.

(3) FIG. 2A depicts the first general processing stage for the primary neuronal action potential activation device, i.e., the electrolyte insulator semiconductor capacitor, in accordance with an embodiment of the present invention.

(4) FIG. 2B depicts the second general processing stage for the primary neuronal action potential activation device, i.e., the electrolyte insulator semiconductor capacitor, in accordance with an embodiment of the present invention.

(5) FIG. 2C depicts the third general processing stage for the primary neuronal action potential activation device, i.e., the electrolyte insulator semiconductor capacitor, in accordance with an embodiment of the present invention.

(6) FIG. 2D depicts the fourth general processing stage for the primary neuronal action potential activation device, i.e., the electrolyte insulator semiconductor capacitor, in accordance with an embodiment of the present invention.

(7) FIG. 2E depicts the fifth general processing stage for the primary neuronal action potential activation device, i.e., the electrolyte insulator semiconductor capacitor, in accordance with an embodiment of the present invention.

(8) FIG. 2F depicts the sixth general processing stage for the primary neuronal action potential activation device, i.e., the electrolyte insulator semiconductor capacitor, in accordance with an embodiment of the present invention.

(9) FIG. 2G depicts the seventh general processing stage for the primary neuronal action potential activation device, i.e., the electrolyte insulator semiconductor capacitor, in accordance with an embodiment of the present invention.

(10) FIG. 2H depicts the eighth general processing stage for the primary neuronal action potential activation device, i.e., the electrolyte insulator semiconductor capacitor, in accordance with an embodiment of the present invention.

(11) FIG. 2I depicts the ninth general processing stage for the primary neuronal action potential activation device, i.e., the electrolyte insulator semiconductor capacitor, in accordance with an embodiment of the present invention.

(12) FIG. 3A depicts the first general processing stage for making a field effect transistor for intercepting the ionic changes which are generated during a neuronal action potential in order to have a complete neural implantation device, in accordance with an embodiment of the present invention.

(13) FIG. 3B depicts the second general processing stage for making a field effect transistor for intercepting the ionic changes which are generated during a neuronal action potential in order to have a complete neural implantation device, in accordance with an embodiment of the present invention.

(14) FIG. 3C depicts the third general processing stage for making a field effect transistor for intercepting the ionic changes which are generated during a neuronal action potential in order to have a complete neural implantation device, in accordance with an embodiment of the present invention.

(15) FIG. 3D depicts the fourth general processing stage for making a field effect transistor for intercepting the ionic changes which are generated during a neuronal action potential in order to have a complete neural implantation device, in accordance with an embodiment of the present invention.

(16) FIG. 3E depicts the fifth general processing stage for making a field effect transistor for intercepting the ionic changes which are generated during a neuronal action potential in order to have a complete neural implantation device, in accordance with an embodiment of the present invention.

(17) FIG. 3F depicts the sixth general processing stage for making a field effect transistor for intercepting the ionic changes which are generated during a neuronal action potential in order to have a complete neural implantation device, in accordance with an embodiment of the present invention.

(18) FIG. 3G depicts the seventh general processing stage for making a field effect transistor for intercepting the ionic changes which are generated during a neuronal action potential in order to have a complete neural implantation device, in accordance with an embodiment of the present invention.

(19) FIG. 3H depicts the eighth general processing stage for making a field effect transistor for intercepting the ionic changes which are generated during a neuronal action potential in order to have a complete neural implantation device, in accordance with an embodiment of the present invention.

(20) FIG. 4A depicts the first general processing stage for making the second transistor, i.e., a 3CSiC EISFET, in accordance with an embodiment of the present invention.

(21) FIG. 4B depicts the second general processing stage for making the second transistor, i.e., a 3CSiC EISFET, in accordance with an embodiment of the present invention.

(22) FIG. 4C depicts the third general processing stage for making the second transistor, i.e., a 3CSiC EISFET, in accordance with an embodiment of the present invention.

(23) FIG. 4D depicts the fourth general processing stage for making the second transistor, i.e., a 3CSiC EISFET, in accordance with an embodiment of the present invention.

(24) FIG. 4E depicts the fifth general processing stage for making the second transistor, i.e., a 3CSiC EISFET, in accordance with an embodiment of the present invention.

(25) FIG. 4F depicts the sixth general processing stage for making the second transistor, i.e., a 3CSiC EISFET, in accordance with an embodiment of the present invention.

(26) FIG. 4G depicts the seventh general processing stage for making the second transistor, i.e., a 3CSiC EISFET, in accordance with an embodiment of the present invention.

(27) FIG. 4H depicts the eighth general processing stage for making the second transistor, i.e., a 3CSiC EISFET, in accordance with an embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

(28) This present invention provides for a long term biocompatible neural implant utilizing field effect devices. Each component of the invention may be formed of many related materials.

(29) FIG. 1 depicts an illustrative embodiment of the novel of the present invention, which is denoted as a whole by the reference numeral 10. The novel structure includes two (2) primary sections, as depicted in FIG. 1. The first section, labeled 20 in FIG. 1, contains the control and routing circuitry for the signals, the signal generation circuit, the signal processing circuit (amplifiers, filters, and analog to digital converters), the wireless communication system, and the power receiving or supply system. The power system may contain either a wireless power reception system or a rechargeable battery supply.

(30) The second section 30 in FIG. 1 is implanted into the tissue and interacts directly within the neural environment. Although the depicted device includes three (3) planar Michigan Probe style probes, there is no limit to how many multiple planar probes can be constructed in parallel. Nor is there a limit to the number of the comb like parallel devices which can be set into arrays to create a three dimensional device. This system is composed of a sharpened protrusion, which is attached to the first section 20 through wafer bonding techniques or connected using flexible wires coated with chemically resistant polymers. As the polymers will not penetrate the neural environment, they last longer than expected. The surface of the planar probe, which interacts with the neuronal environment, contains an assortment of up to three (3) types of FET devices. Cubic silicon carbide (3CSiC) is the base physical material for the generation of the FET devices. Graphene can be produced directly on 3CSiC, and diamond is a cubic structure and can also be grown on 3CSiC. All reference hereinafter to 3CSiC should be understood to include diamond and graphene as well since said materials may replace 3CSiC. The insulating materials and conducting materials are interchangeable as mentioned previously.

(31) More particularly, the field effect devices in this invention may be formed of three (3) different semiconductor materials: 3CSiC, diamond, and graphene. Although 3CSiC and diamond are materials known to have utility in the construction of field effect devices, graphene has utility as a transistor element as well. Each of these materials is physically and chemically robust, and has appreciable levels of biocompatibility. The devices within this invention include amorphous SiC (a-SiC), polycrystalline SiC (poly-SiC), and insulating diamond as insulator material to generate the gate fir the field effect devices. Diamond can be in single-, poly-, nano-, or ultracrystalline form. The same materials can be used for the isolation material, but nominally the material with the best deposition rate and insulating properties are used. Metal conductors are replaced with carbon conductors. The conductors are graphene and graphitized carbon from pyrolyzed polymers (i.e. photoresist). Specifically, a semiconductor based active device generates and receives electric fields for the communication with neurons, thereby replacing the non-biocompatible Si-based neural prosthetic devices.

(32) Due to the complexity of the circuitry required for the control circuitry 20 of the device 10, silicon is used as a base semiconductor material due to the level of processing technology necessary to complete complex circuits as well as the large array of processing techniques available. The Si derivative SiO.sub.2 is used for quality insulation (i.e. gate insulation) and Si.sub.3N.sub.4 is used for a device isolation material. Metals like Au, Pt, chrome, polysilicon, etc., have utility as the device conductors and interconnect feed-thrus to the devices on the implantable field effect devices 30.

(33) Si and its derivatives have biocompatibility and chemical resistivity issues, so the control circuitry 20 must be hermetically sealed to both protect its functionality, as well as protect the body from the possible deterioration of the device. Hermetic sealing in amorphous SiC (a-SiC) or nanocrystalline/ultracrystalline diamond are good hermetic sealing agents as they have physical and chemical robustness and they have been used in long term implants before.

(34) The primary neuronal action potential activation device is the 3CSiC EIScap, or electrolyte insulator semiconductor capacitor. The general processing stages for this device are shown with reference to FIG. 2. In an exemplary embodiment, at stage 2A, the process consists of growing a homoepitaxial film 40 onto the surface of a cubic substrate 45. Si is the cheapest method of the heteroepitaxial growth for 3CSiC, and it also provides additional processing benefits through its chemical susceptibility. Single crystal diamond and hexagonal forms of SiC (4H and 6HSiC) can also be used as substrates for 3CSiC growth, but are considerably harder to remove.

(35) N-type 3CSiC 40 may be grown on Si 45 through the introduction of nitrogen gas during intrinsic epitaxial growth during the first stage of processing. For stage 2B, photolithographic methodology is employed to generate a protective mask 50 on the 3CSiC 20. Neurons require a high level of charge transfer, and the doping is increased by the ion implantation of aluminum ions (Al.sup.+3). 3CSiC domains grow at different rates, so the surface has a mesa like appearance.

(36) To ensure that there are no charge irregularities due to surface geometry, the 3CSiC wafer is CMP (chemically mechanically polished) polished flat, chemically cleaned, and etched in a high temperature hydrogen ambient to reveal an atomically flat surface.

(37) For stage 2C, a thin layer of high quality insulation material 50 is grown or deposited to generate the gate of the device. The deposition method depends on the materials selected.

(38) Stage 2D requires the deposition of the device isolation material 60, which may be of lower quality than the gate insulator due to the trade-off in deposition speed and thickness.

(39) Stage 2E uses lithography to generate the protective mask, and a window 65 is etched in the isolation material 60 down to the gate insulation 50. Unlike Si, there are no convenient chemical etching processes for SiC, so DRIE or RIE are regularly employed instead.

(40) At Stage 2F the Si substrate wafer 45 is removed to create a free-standing device. This removal can be achieved using one of many methods of dry or wet chemical etching. At the end of stage 2F, the released 3CSiC film is cleaned, and the 3CSiC interface defects are etched away by DRIE/RIE etching. Etching a few microns into the 3CSiC material removes many of the defects generated during heteroepitaxial crystal growth.

(41) After careful CMP planarization, polishing, and H.sub.2 etching, stage 2G is used to deposit/grow a thin film of one of the novel conductors 70 onto the backside of the 3CSiC wafer.

(42) The conductor network 75 is generated in stage 2H through lithography and etching. An alternative for the masking followed by the etching performed in stages 20 and 2H is the lift-off process. In the lift-off process, starting in stage 20, but perform the lithography first, and the conductor 70 is deposited on top of the lithographic mask and the exposed surfaces. In stage 2H, the polymer mask is dissolved away, taking the excess conductor with it and revealing the completed conductor network 75 for the device. This alternative lift-off process is temperature dependent as most polymers cannot withstand the temperatures required to epitaxially generate graphene on the face of 3CSiC, but it is an alternative nonetheless.

(43) The last stage, stage 2I, requires cleaning the wafer and coating the conductor network 75 with a thick film of insulation material 80. This is followed by high temperature annealing in an ambient gas such as argon, Ar. This activates the doping ions within the 3CSiC crystal lattice, as well as repairs some of the crystal damage from the ion implantation.

(44) The EIScap sends signals to neural tissue (i.e., perform stimulation), but a field effect transistor (FET)) is needed to intercept the ionic changes which are generated during a neuronal action potential in order to have a complete neural implantation device (i.e., signal recording).

(45) The FET device used to intercept the ionic changes at the neural interface may be a junction field effect transistor (JFET). This is a simple transistor and does not require a gate insulator. The general processing stages for the JFET are illustrated with reference to FIG. 3.

(46) Stage 3A begins with the same processing stages used for the EIScap, as both of these devices are required to be eventually generated side by side and at the same time on the same interface.

(47) Stage 3B involves using photolithography to generate a mask for deep ion implantation of aluminum ions (Al.sup.+3) which will lay the foundation for the p-stop isolation 85 for the JFET. A second ion implantation of nitrogen ions (N.sup.3) generates the location of the n-channel 90 for the JFET.

(48) The surface is cleaned to remove the masks, and a final mask is generated for the implanting of the p-type gate junction 95 during stage 3C. The extra ion implantation is preferred because a p-channel 3CSiC JFET would not be as efficient as the n-channel due to a much lower hole mobility than electron mobility.

(49) Stage 3D consists of the generation of a thin film layer of the preselected conductor material 100, which is followed by a lithographic generated mask.

(50) The conductor network 110 is revealed through etching in stage 3E. As with the production of the EIScap, stages 3D and 3E could be accomplished using the lift-off method as an alternative to blanket film etching. The area above the junction 95 is conductor free, and the electrolyte metals (Na.sup.+, K.sup.+, Ca.sup.+2, Mg.sup.+2, Cl.sup.) are used to modulate the width of the depletion layer within the n-channel.

(51) Stage 3F coats the entire surface of the wafer with the electrical isolation material 115.

(52) Stage 3G uses photolithography to open the gate windows 95 through the insulation material 115.

(53) Stage 3H finishes the device by removing the Si substrate 45, and annealing the SiC 40 to allow activation of the dopant ions into the crystal lattice.

(54) The second transistor may be a 3CSiC EISFET, as depicted with reference to FIG. 4.

(55) Stage 4A is the same as the previous two devices with growth of n-type 3CSiC 40 on a Si substrate 45.

(56) At stage 4B, lithography is used to generate two masks. The first is for the ion implantation of the p-type source and drain wells 120, and a second mask provides the template for the n.sup. isolation wells 125.

(57) At stage 4C, the conductor 130 selected for the device manufacture is grown on, or deposited on, the surface of the 3CSiC, and lithography and etching are used to generate the conductive pathways 135 for the source and drain in stage 4D. Stages 4C and 4D can be interchanged with the liftoff method as previously described.

(58) In stage 4E, the development of the conductive pathways 135 is followed by the deposition of a high quality insulator material 140, used for the gate material.

(59) The 4E stage is followed by the deposition of the isolation material 145 in stage 4F.

(60) Stage 4G begins with lithographic generation of the mask, and subsequent etching of the window 150 for the buried gate material 40.

(61) Finally, in stage 4H, the Si substrate 45 is removed and the device is annealed to activate the dopant material.

(62) The devices described above are combined in pairs on the surface of the shank. They are distributed according to the target area within the brain to efficiently interact with the neurons/neural bundles. Bi-directional signaling is simply made by combining an EIScap device signal with either a JFET or EISFET device running in saturated mode. Much of the required wiring for the manipulation of the three terminal FET systems can be consolidated by generating a switching grid system within the first section of the device 20, and multiple emitters, or conductors, can be interlaced in the same way. Finally, to generate active layers on both sides of the planar device, a second round of processing is used on the opposite face of the 3CSiC shank after removal of the silicon base.

(63) The realization of two-sided devices could also be realized with wafer binding techniques, but the bonding material must possess biocompatibility at least as acceptable as the materials disclosed herein.

(64) It will thus be seen that the objects set forth above, and those made apparent from the foregoing disclosure, are efficiently attained and since certain changes may be made in the above construction without departing from the scope of the invention, it is intended that all matters contained in the foregoing disclosure or shown in the accompanying drawings shall be interpreted as illustrative and not in a limiting sense.

(65) It is also to be understood that the following claims are intended to cover all of the generic and specific features of the invention herein described, and all statements of the scope of the invention that, as a matter of language, might be said to fall therebetween.