System and method for detecting the presence and type of capacitive loads

Abstract

System and method for detecting the presence and type of capacitive load that may be coupled to a power driver. The system includes a detection circuit to determine the presence and type of load based on a measured characteristic of the load in response to a drive voltage. The characteristic may be the load capacitance as measured by the current flow between the driver and load. The circuit may include a differential amplifier to generate a current-related voltage, comparators to generate pulses when the voltage exceeds respective thresholds, registers to output logic levels in response to the comparators, and a microcontroller to make the determination based on the logic levels. Alternatively, the circuit includes a differential amplifier to generate a current-related voltage, a rectifier to rectify the voltage, a peak and hold circuit to hold the peak voltage, an ADC to digitize the peak voltage, and a microcontroller to make its determination based on the digitized voltage.

Claims

1. A system, comprising: a piezoelectric actuator comprising: a piezoelectric material configured to expand or contract in response to a drive voltage; and a rotor frictionally coupled to the piezoelectric material; a power diver configured to generate the drive voltage, wherein the drive voltage comprises a pulse with a first edge and a second edge, wherein a slope of the first edge is greater than a slope of the second edge to cause the rotor to rotate clockwise or counter-clockwise due to a coefficient of friction between the piezoelectric material and the rotor during the second edge being greater than a coefficient of friction between the piezoelectric material and the rotor during the first edge; an electrical connection configured to electrically couple the power driver to the piezoelectric actuator; and a detection circuit configured to determine whether the piezoelectric actuator is connected to the power driver by sensing a parameter associated with the electrical connection, and if connected, the type of the piezoelectric actuator connected to the power driver based on a measured characteristic of the piezoelectric actuator in response to the drive voltage.

2. The system of claim 1, wherein the measured characteristic comprises a capacitance of the piezoelectric actuator.

3. The system of claim 2, wherein the detection circuit is configured to measure the capacitance of the piezoelectric actuator by sensing a current flow between the power driver and the piezoelectric actuator.

4. The system of claim 3, wherein the detection circuit is configured to determine the type of the piezoelectric actuator connected to the power driver based on a positive or negative peak of the sensed current flowing between the power driver and the piezoelectric actuator.

5. The system of claim 1, wherein the measured characteristic is based only on the first edge among the first and second edges of the pulse.

6. The system of claim 5, wherein the measured characteristic comprises a capacitance of the piezoelectric actuator.

7. The system of claim 5, wherein the slope of the first edge comprises a negative slope.

8. The system of claim 5, wherein the slope of the first edge comprises a positive slope.

9. The system of claim 1, wherein the detection circuit comprises: a differential amplifier configured to generate a current-related voltage based on current flowing between the power driver and the piezoelectric actuator via the electrical connection in response to the drive voltage; a first circuit configured to produce a first logic voltage, wherein the first logic voltage is at an asserted level in response to the current-related voltage being above a first positive threshold if the first edge has a positive slope or below a first negative threshold if the first edge has a negative slope, and at a de-asserted level in response to the current-related voltage being below the first positive threshold if the first edge has a positive slope or above the first negative threshold if the first edge has a negative slope; and a second circuit configured to produce a second logic signal, wherein the second logic voltage is at an asserted level in response to the current-related voltage being above a second positive threshold or below a second negative threshold, and at a de-asserted level in response to the current-related voltage being below the second positive threshold or above the second negative threshold.

10. The system of claim 9, wherein the first or second logic voltage is asserted in response to the current-related voltage being respectively above the first or second positive threshold in further response to the first edge having a positive slope, and wherein the first or second logic voltage is asserted in response to the current-related voltage being respectively below the first or second negative threshold in further response to the first edge having a negative slope.

11. The system of claim 9, wherein the detection circuit comprises a microcontroller configured to: determine that the piezoelectric actuator connected to the power driver is of a first type in response to the first and second logic voltages being at the asserted levels; determine that piezoelectric actuator connected to the power driver is of a second type in response to the first logic voltage being at the de-asserted level and the second logic voltage being at the asserted level; and determine that the piezoelectric actuator is not connected to the power driver in response to the first and second logic voltages being at the de-asserted levels.

12. The system of claim 11, wherein the microcontroller is configured to: perform a first operation in response to determining that the first type of piezoelectric actuator is connected to the power driver; perform a second operation in response to determining that the second type of piezoelectric actuator is connected to the power driver; and perform a third operation in response to determining that no piezoelectric actuator is connected to the power driver.

13. The system of claim 12, wherein the microcontroller is configured to: control the power driver to send pulses to the piezoelectric actuator at a first rate in response to determining that the second type of piezoelectric actuator is connected to the power driver; and control the power driver to send pulses to the piezoelectric actuator at a second rate in response to determining that the first type of piezoelectric actuator is connected to the power driver, wherein the second rate is greater than the first rate.

14. The apparatus of claim 1, wherein the parameter comprises a current through the electrical connection.

15. The apparatus of claim 1, wherein the electrical connection comprises a sense resistor, and wherein the parameter comprises a voltage across the sense resistor.

16. An apparatus comprising: a piezoelectric actuator comprising: a piezoelectric material configured to expand or contract in response to a drive voltage; and a rotor frictionally coupled to the piezoelectric material; a power driver configured to generate the drive voltage, wherein the drive voltage comprises a pulse with a first edge and a second edge, wherein a slope of the first edge is greater than a slope of the second edge to cause the rotor to rotate clockwise due to a coefficient of friction between the piezoelectric material and the rotor during the second edge being greater than a coefficient of friction between the piezoelectric material and the rotor during the first edge, and wherein the measured characteristic is based only on the first edge among the first and second edges of the pulse; a differential amplifier configured to generate a current-related voltage based on current flowing between the power driver and the piezoelectric actuator in response to a drive voltage; a circuit configured to generate a first voltage related to an absolute value of the current-related voltage; a sample and hold circuit configured to generate a second voltage related to a peak of the first voltage; and a microcontroller configured to: determine that no piezoelectric actuator is connected to the power driver based on the second voltage; or determine a type of piezoelectric actuator connected to the power driver based on the second voltage.

17. The apparatus of claim 16, wherein the circuit comprises a rectifier.

18. The apparatus of claim 16, further comprising an analog-to-digital converter configured to generate a digital word based on the second voltage, wherein the microcontroller is configured to receive the digital word to make said determination.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 illustrates a block diagram of an exemplary system for detecting the presence and type of capacitive load that may be connected to a power driver in accordance with an aspect of the disclosure.

(2) FIGS. 2A-2B illustrate timing diagrams associated with exemplary operation of the system of FIG. 1 in accordance with another aspect of the disclosure.

(3) FIG. 3 illustrates a block diagram of another exemplary system for detecting the presence and type of capacitive load that may be connected to a power driver in accordance with another aspect of the disclosure.

(4) FIGS. 4A-4B illustrate timing diagrams associated with exemplary operation of the system of FIG. 3 in accordance with another aspect of the disclosure.

(5) FIG. 5A illustrates a block diagram of yet another exemplary system for detecting the presence and type of capacitive load that may be connected to a power driver in accordance with another aspect of the disclosure.

(6) FIG. 5B illustrates a timing diagram associated with exemplary operation of the system of FIG. 5A in accordance with another aspect of the disclosure.

(7) FIG. 6 illustrates a block diagram of still another exemplary system for detecting the presence and type of capacitive load that may be connected to a power driver in accordance with another aspect of the disclosure.

DETAILED DESCRIPTION OF THE EXEMPLARY EMBODIMENTS

(8) FIG. 1 illustrates a block diagram of an exemplary system 100 for detecting the presence and type of capacitive load 152 that may be connected to a power driver 150 in accordance with an aspect of the disclosure. The capacitive load 152 may comprise any type of capacitive loads including different types of piezoelectric actuators and different types of PICOMOTERS. In summary, the system 100 comprises a detection circuit 110 configured to sense the current I flowing between the power driver 150 and the capacitive load 152 by way of a resistor R.sub.S in response to a drive voltage V.sub.D generated by the power driver 150, and determine the type of capacitive load 152 or whether the capacitive load 152 is connected to the power driver 150 based on that measured current I.

(9) In this example, there are two possible types of capacitive loads. For example, the two types of capacitive load may include a standard PICOMOTER and a tiny PICOMOTER. More generically, the two types of capacitive loads may include a higher-capacitive load and a lower-capacitive load. However, it shall be understood that the detection circuit may be able to detect more than two types of capacitive loads, as will be discussed with reference to another exemplary embodiment described herein.

(10) In particular, the detection circuit 110 comprises a differential amplifier 112, a first window comparator 114-1, a first upper and lower threshold generator 116-1, a second window comparator 114-2, and a second upper and lower threshold generator 116-2. Additionally, the detection circuit 110 comprises a first register 118-1, a second register 118-2, and a microcontroller 120.

(11) The detection of the type or the presence of the capacitive load 152 operates as follows. The power driver 150 is operated to generate a drive voltage V.sub.D. For example, the drive voltage V.sub.D may be in the form of a defined pulse or waveform. In response to the drive voltage V.sub.D, a current I may be produced that flows between the power driver 150 and the capacitive load 152. If, for example, the capacitive load 152 is not present or is disconnected from the power driver 150 due to faulty wiring or other causes, no or little current I may be produced.

(12) If, on the other hand, a capacitive load 152 is present, the current I generated may have a magnitude or a peak that is related to the capacitance of the capacitive load 152. For example, assuming that the capacitance of the first type of capacitive load (e.g., a standard PICOMOTER) is greater than the capacitance of the second type of capacitive load (e.g., a tiny PICOMOTER), the magnitude or peak of the current I produced will be greater for the first type of capacitive load than for the second type of capacitive load.

(13) Additionally, the drive voltage V.sub.D may be configured to operate the capacitive load 152 in a certain manner, which results in a positive peak current I (e.g., a current flowing from the power driver 150 to the capacitive load 152), or operate the capacitive load 152 in another manner, which results in a negative peak current I (e.g., a current flowing from the capacitive load 152 to the power driver 150). This may be the case where the capacitive load 152 comprises a piezoelectric actuator or PICOMOTER that is operated to move in one direction (e.g., a forward or clockwise direction), which results in a negative peak current I, or operated to move in the opposite direction (e.g., a reverse or counter-clockwise direction), which results in a positive peak current I.

(14) The differential amplifier 112 generates a voltage V.sub.I that is proportional or related to the current I by sensing the voltage drop across the current-sensing resistor R.sub.S. The first window comparator 114-1 compares the current-related voltage V.sub.I to lower and upper thresholds V.sub.TH1-F and V.sub.TH1-R. The lower threshold V.sub.TH1-F applies to when the capacitive load 152 is operated in a particular manner (e.g., moved in a forward or clockwise direction) that produces a negative peak current I, and the upper threshold V.sub.TH1-R applies to when the capacitive load 152 is operated in another manner (e.g., moved in a reverse or counter-clockwise direction) that produces a positive peak current I.

(15) For instance, if the peak of the current-related voltage V.sub.I exceeds the lower threshold V.sub.TH1-F in the negative direction or exceeds the upper threshold V.sub.TH1-R in the positive direction, the first window comparator 114-1 generates a voltage V.sub.P1 that causes the register 118-1 to produce an output signal V.sub.R1 at a high logic level. Otherwise, if the peak of the current-related voltage V.sub.I does not exceed the lower threshold V.sub.TH1-F in the negative direction or does not exceed the upper threshold V.sub.TH1-R in the positive direction, the first window comparator 114-1 generates a voltage V.sub.P1 that does not cause the register 118-1 to output V.sub.R1 at the high logic level; and thus, the output signal V.sub.R1 of the register 118-1 remains at a low logic level.

(16) Similarly, the second window comparator 114-2 compares the current-related voltage V.sub.I to lower and upper thresholds V.sub.TH2-F and V.sub.TH2-R. The lower threshold V.sub.TH2-F applies to when the capacitive load 152 is operated in a particular manner (e.g., moved in a forward or clockwise direction) that produces a negative peak current I, and the upper threshold V.sub.TH2-R applies to when the capacitive load 152 is operated in another manner (e.g., moved in a reverse or counter-clockwise direction) that produces a positive peak current I. The lower and upper thresholds V.sub.TH2-F and V.sub.TH2-R of the second window comparator 114-2 are smaller in magnitude than the lower and upper thresholds V.sub.TH1-F and V.sub.TH1-R of the first window comparator 114-1. This is because the thresholds V.sub.TH2-F and V.sub.TH2-R are used for detecting a type 2 capacitive load that has a smaller capacitance than the type 1 capacitive load.

(17) Similarly, if the peak of the current-related voltage V.sub.I exceeds the lower threshold V.sub.TH2-F in the negative direction or exceeds the upper threshold V.sub.TH2-R in the positive direction, the second window comparator 114-2 generates a voltage V.sub.P2 that causes the second register 118-2 to produce an output signal V.sub.R2 at a high logic level. Otherwise, if the peak of the current-related voltage V.sub.I does not exceed the lower threshold V.sub.TH2-F in the negative direction or does not exceed the upper threshold V.sub.TH2-R in the positive direction, the second window comparator 114-2 generates a voltage V.sub.P2 that does not cause the second register 118-2 to output V.sub.R2 at a high logic level; and thus, the output signal V.sub.R2 of the register 118-2 remains at a low logic level.

(18) The respective output signals V.sub.R1 and V.sub.R2 of the registers 118-1 and registers 118-2 indicate whether a capacitive load is connected to the power driver 150 and if connected, the type of capacitive load 152. For instance, if the output signals V.sub.R1 and V.sub.R2 are both at low logic levels, this indicates that there is no capacitive load connected to the power driver 150. This is because the current I, as measured by the current-related voltage V.sub.I, does not exceed either both thresholds V.sub.TH1-F and V.sub.TH2-F in the negative direction or both thresholds V.sub.TH1-R and V.sub.TH2-R in the positive direction. In other words, the current I is below what is expected for type 1 and type 2 capacitive loads; and thus, this implies the absence of a capacitive load connected to the power driver 150.

(19) Considering another case, if the output signal V.sub.R1 of the first register 118-1 is at a low logic level, and the output signal V.sub.R2 of the second register 118-2 is at a high logic level, this indicates that a type 2 capacitive load (i.e., the load with lesser capacitance) is connected to the power driver 150. This is because the current I, as measured by the current-related voltage V.sub.I, exceeds the threshold V.sub.TH2-F in the negative direction or the threshold V.sub.TH2-R in the positive direction, but does not exceed the threshold V.sub.TH1-F in the negative direction or the threshold V.sub.TH1-R in the positive direction. In other words, the current I is at or above what is expected for a type 2 capacitive load, but below what is expected for a type 1 capacitive load; and thus, this implies that a type 2 capacitive load is connected to the power driver 150.

(20) Considering the last case, if the respective output signals V.sub.R1 and V.sub.R2 of the first and second registers 118-1 and 118-2 are both at high logic levels, this indicates that a type 1 capacitive load (i.e., the load with a greater capacitance) is connected to the power driver 150. This is because the current I, as measured by the current-related voltage V.sub.I, exceeds either both thresholds V.sub.TH1-F and V.sub.TH2-F in the negative direction or both thresholds V.sub.TH1-R and V.sub.TH2-R in the positive direction. In other words, the current I is at or above what is expected for a type 1 capacitive load; and thus, this implies that a type 1 capacitive load is connected to the power driver 150.

(21) The microcontroller 120 may read the outputs of the registers 118-1 and 118-2 at any time to ascertain whether there is a capacitive load 152 connected to the power driver 150, and if connected, the type of capacitive load. After reading the outputs of the registers 118-1 and 118-2, the microcontroller 120 may generate a reset signal to clear the first and second registers 118-1 and 118-2; or more specifically, to cause the outputs V.sub.R1 and V.sub.R2 of the registers 118-1 and 118-2 to be at low logic levels.

(22) Based on the outcome of the aforementioned measurement, the microcontroller 120 may perform any defined operation. For example, in the case where the measurement indicates an absence of a capacitive load, the microcontroller 120 may inform a user by way of a user interface device (e.g., display, speaker, etc.) of the absence of the capacitive load. Alternatively, or in addition to, the microcontroller 120 may inhibit certain operations like, for example, the generation of the drive voltage V.sub.D by the power driver 150. Similarly, in response to the measurement indicating that a type 2 capacitive load is connected to the power driver 150, the microcontroller 120 may inhibit and/or allow certain operations. For example, if the type 2 capacitive load is a tiny PICOMOTER that can only be driven with a certain maximum pulse rate (e.g., a rate below the specified pulse rate for the standard PICOMOTER), the microcontroller 120 may limit the pulse rate to the maximum pulse rate for the tiny PICOMOTER. It shall be understood that the microcontroller 120 may perform any operation based on the results of the measurement. The microcontroller 120 may reset the registers 118-1 and 118-1 after each measurement by generating a reset signal. The reset signal causes the output signals V.sub.R1 and V.sub.R2 of the registers 118-1 and 118-2 to be at low logic levels.

(23) As noted in FIG. 1, the detection circuit 110 may be separate from the power driver 150 and capacitive load 152. This facilitates the implementation of the detection circuit 110 in exiting systems that include a power driver 150 and a capacitive load 152. Often, in such systems, a resistor is coupled in series between the power driver 150 and the capacitive load 152 for current-limiting purpose or other purposes. Thus, in such cases, the differential amplifier 112 of the detection circuit 110 may be easily connected across such resistor in order to effectuate the measurement of the current and perform the detection of the presence and/or type of capacitive load.

(24) FIG. 2A illustrates a timing diagram associated with exemplary operation of the system 100 in accordance with another aspect of the disclosure. The timing diagram is used to summarize the operation discussed above when the capacitive load 152 is operated in a manner (e.g., moved in a forward or clockwise direction) that produces a negative peak current I. Additionally, the timing diagram addresses three cases: case I where a type 1 capacitive load is connected to the power driver; case II where a type 2 capacitive load is connected to the power driver; and case III where no capacitive load is connected to the power driver.

(25) The x- or horizontal axis for each case represents time, and the y- or vertical axis represents the different voltages or signals associated with the operation of the detection circuit 110. These voltages or signals include, from ascending to descending order, the drive voltage V.sub.D generated by the power driver 150, the current-related voltage V.sub.I generated by the differential amplifier 112, the voltage V.sub.P1 generated by the first window comparator 114-1, the voltage V.sub.P2 generated by the second window comparator 114-2, the signal V.sub.R1 generated by the first register 118-1, the signal V.sub.R2 generated by the second register 118-2, and the reset signal generated by the microcontroller 120.

(26) Considering case I where a type 1 capacitive load is connected to the power driver 150, the drive voltage V.sub.D shown may be configured to drive a PICOMOTER in a first direction (e.g., in a forward or clockwise direction) using the principle of stick and slip or static or dynamic friction. The leading edge of the drive voltage V.sub.D has a gradual rising slope in order to expand a piezoelectric material in a slow manner, which allows the piezoelectric material to rotate a wheel in contact therewith in one direction due to greater static friction. The trailing edge of the drive voltage V.sub.D has a fast falling slope in order to contract the piezoelectric material in a fast manner to cause slippage of the piezoelectric material along the wheel due to the lesser dynamic friction. Thus, using this waveform V.sub.D, the wheel turns in one direction and does not turn in the opposite direction.

(27) The current I produced in response to this drive voltage V.sub.D, as indicated by the current-related voltage V.sub.I, has a small positive rise/fall substantially coincidental with the leading edge of the drive voltage V.sub.D, and a large negative spike substantially coincidental with the trailing edge of the drive voltage V.sub.D. In the example of case I, the negative peak V.sub.PK exceeds both lower thresholds V.sub.TH1-F and V.sub.TH2-F of the first and second window comparators 114-1 and 114-2, respectively. This causes both the first and second window comparators 114-1 and 114-2 to generate voltages V.sub.P1 and V.sub.P2 in the form of positive pulses substantially coincidental with the negative peak V.sub.PK of the current-related voltage V.sub.I.

(28) The pulses generated by the first and second window comparators 114-1 and 114-2 cause the first and second registers 118-1 and 118-2 to generate voltages V.sub.R1 and V.sub.R2 at high logic levels. As previously discussed, the outputs of the registers 118-1 and 118-2 at high logic levels indicate that a type 1 capacitive load (e.g., a standard PICOMOTER) is connected to the power driver 150. The microcontroller 120 then reads the outputs of the registers 118-1 and 118-2 and then issues a reset (e.g., an inverted pulse) to both registers to bring their outputs to low logic levels. The microcontroller 120 may then perform one or more functions based on the detection of the type 1 capacitive load connected to the power driver 150.

(29) Considering case II where a type 2 capacitive load is connected to the power driver 150, the same or similar drive voltage V.sub.D is generated by the power driver 150. In response to the drive voltage V.sub.D, the current-related voltage V.sub.I generated has a positive rise/fall substantially coincidental with the leading edge of the drive voltage V.sub.D, and a negative peak V.sub.PK substantially coincidental with the trailing edge of the drive voltage V.sub.D. In this case, the negative peak V.sub.PK does not exceed the threshold V.sub.TH1-F in the negative direction, but exceeds the threshold V.sub.TH2-F in the negative direction. As a result, the first window comparator 118-1 does not generate a signal V.sub.P1 with a pulse, but the second window comparator 118-2 does generate a signal V.sub.P2 with a pulse substantially coincidental with the negative peak V.sub.PK of the current-related voltage V.sub.I.

(30) Because of the absence of a pulse in the signal V.sub.P1, the first register 118-1 continues to generate the signal V.sub.R1 at a low logic level. However, due to a pulse in the signal V.sub.P2, the second register 118-2 generates the signal V.sub.R2 at a high logic level. As previously discussed, the outputs of the registers 118-1 and 118-2 being at low and high logic levels, respectively, indicate that a type 2 capacitive load (e.g., a tiny PICOMOTER) is connected to the power driver 150. The microcontroller 120 then reads the outputs of the registers 118-1 and 118-2 and issues a reset (e.g., an inverted pulse) to both registers to ensure that their outputs are both at low logic levels. The microcontroller 120 may then perform one or more functions based on the detection of a type 2 capacitive load connected to the power driver 150.

(31) Finally, considering case III where there is no capacitive load connected to the power driver 150, the same or similar drive voltage V.sub.D is generated by the power driver 150. Since there is no load, no current I is generated in response to the drive voltage V.sub.D. As a result, the current-related voltage V.sub.I remains at substantially zero (0) Volt, and accordingly, does not exceed both thresholds V.sub.TH1-F and V.sub.TH2-F. As a result, the first and second window comparators 118-1 and 118-2 do not generate signals V.sub.P1 and V.sub.P2 with pulses. Because of an absence of pulses in the signals V.sub.P1 and V.sub.P2, the first and second register 118-1 and 118-2 continue to generate signals V.sub.R1 and V.sub.R2 at low logic levels. As previously discussed, the outputs of the registers 118-1 and 118-2 being at low logic levels indicate the absence of a capacitive load connected to the power driver 150. The microcontroller 120 then reads the outputs of the registers 118-1 and 118-2 and issues a reset (e.g., an inverted pulse) to both registers to ensure that their outputs are at low logic levels. The microcontroller 120 may then perform one or more functions based on the detection of no capacitive load connected to the power driver 150.

(32) FIG. 2B illustrates another timing diagram associated with exemplary operation of the system 100 in accordance with another aspect of the disclosure. The timing diagram is similar to the timing diagram of FIG. 2A, except that the capacitive load 152 (e.g., a piezoelectric actuator or PICOMOTER) is driven in the opposite direction (e.g., in the reverse or counter-clockwise direction). In particular, the waveform of the drive voltage V.sub.D has a leading edge that rises relatively fast and a trailing edge that falls relatively slow. Thus, in the case of a PICOMOTER as the capacitive load 152, the PICOMOTER does not rotate during the leading edge due to slippage or lower dynamic friction, but rotates during the trailing edge due to the higher static friction. Nonetheless, the operation of the detection circuit 110 operates in a similar manner.

(33) Considering case I where a type 1 capacitive load 152 is connected to the power driver 150, the current I, as measured by the current-related voltage V.sub.I, has a positive peak V.sub.PK substantially coincidental with the leading edge of the drive voltage V.sub.D, and a small negative fall/rise substantially coincidental with the trailing edge of the drive voltage V.sub.D. Since the positive peak V.sub.PK of the current-related voltage V.sub.I is above both thresholds V.sub.TH1-R and V.sub.TH2-R, both first and second window comparators 114-1 and 114-2 generate signals V.sub.P1 and V.sub.P2 with pulses substantially coincidental with the peak V.sub.PK of the current-related voltage V.sub.I. In response to the pulses generated by the first and second comparators 114-1 and 114-2, the first and second registers 118-1 and 118-2 generate signals V.sub.R1 and V.sub.R2 at high logic levels, respectively. As previously discussed, the output signals V.sub.R1 and V.sub.R2 of the registers being at high logic levels indicate that a type 1 capacitive load 152 is connected to the power driver 150. The microcontroller 120 reads the outputs of the registers, and performs any number of operations based on a type 1 capacitive load being detected. The microcontroller 120 also issues a reset signal (e.g., an inverted pulse) to reset the registers 118-1 and 118-2 to ensure that they output low logic levels.

(34) Considering case II where a type 2 capacitive load 152 is connected to the power driver 150, the current I, as measured by the current-related voltage V.sub.I, has a positive peak V.sub.PK substantially coincidental with the leading edge of the drive voltage V.sub.D, and a small negative fall/rise substantially coincidental with the trailing edge of the drive voltage V.sub.D. In this case, the positive peak V.sub.PK of the current-related voltage V.sub.I is above threshold V.sub.TH2-R, but below threshold V.sub.TH1-R. Accordingly, the first window comparator 114-1 does not generate a signal V.sub.P1 with a pulse, but the second window comparator generates a signal V.sub.P2 with a pulse substantially coincidental with the peak V.sub.PK of the current-related voltage V.sub.I. In response to the pulse generated by the second window comparator 114-2, the second register 118-2 generates the signal V.sub.R2 at a high logic level. However, the output signal V.sub.R1 of the first register 118-1 remains at a low logic level due to a lack of pulse from the first window comparator 114-1. As previously discussed, the output signals V.sub.R1 and V.sub.R2 of the registers being at low and high logic levels respectively, indicate that a type 2 capacitive load 152 is connected to the power driver 150. The microcontroller 120 reads the outputs of the registers, and performs any number of operations based on a type 2 capacitive load being detected. The microcontroller 120 also issues a reset signal (e.g., an inverted pulse) to reset the registers 118-1 and 118-2 to ensure that they output low logic levels.

(35) Considering case III where no capacitive load 152 is connected to the power driver 150, the current I, as measured by the current-related voltage V.sub.I, is substantially zero (0), and accordingly, does not exceed both thresholds V.sub.TH1-R and V.sub.TH2-R. Thus, the first and second window comparators 114-1 and 114-2 generate signals V.sub.P1 and V.sub.P2 without pulses. As a result, the signals V.sub.R1 and V.sub.R2 of the first and second registers 118-1 and 118-2 remain at low logic levels. As previously discussed, the output signals V.sub.R1 and V.sub.R2 of the registers being at low logic levels indicate that no capacitive load 152 is connected to the power driver 150. The microcontroller 120 reads the outputs of the registers, and performs any number of operations based on detecting no capacitive load. The microcontroller 120 then issues a reset signal (e.g., an inverted pulse) to reset the registers 118-1 and 118-2 to ensure that they output low logic levels.

(36) FIG. 3 illustrates a block diagram of another exemplary system 300 for detecting the presence and type of capacitive load 352 that may be connected to a power driver 350 in accordance with another aspect of the disclosure. The system 300 is similar to the system 100, except that it comprises a detection circuit 310 that is able to detect N types of capacitive loads, instead of being limited to detecting two types of capacitive loads as in detection circuit 110. However, as discussed below, the principle of operations of detection circuit 310 is essentially the same as that of detection circuit 110.

(37) In particular, the detection circuit 310 comprises a differential amplifier 312, N window comparators 314-1, 314-2 to 314-N, N threshold generators 316-1, 316-2 to 316-N, N registers 318-1, 318-2 to 318-N, and a microcontroller 320. The differential amplifier 312 generates a current-related voltage V.sub.I that is proportional or related to the current I produced in response to a drive voltage V.sub.D generated by the power driver 350 by sensing the voltage drop across a current sensing resistor R.sub.S. The window comparators 314-1 to 314-N generate signals V.sub.P1 to V.sub.PN with pulses in response to the current-related voltage V.sub.I exceeding the upper thresholds V.sub.TH1-R to V.sub.THN-R in the positive direction, or the lower thresholds V.sub.TH1-F to V.sub.THN-F in the negative direction, respectively.

(38) In response to the signals V.sub.P1 and V.sub.PN having pulses or lack of pulses, the registers 318-1 to 318-N generates signals V.sub.R1 to V.sub.RN at high logic levels or low logic levels, respectively. The combined digital word generated by the registers 318-1 to 318-N indicates the type of capacitive load 352 connected to the power driver 350 or whether a capacitive load 152 is connected to the power driver 350.

(39) Considering some examples, if the signals V.sub.R1 to V.sub.RN are all at high logic levels, then a type 1 capacitive load 352 is connected to the power driver 350. If signal V.sub.R1 is at a low logic level and the remaining signals V.sub.R2 to V.sub.RN are at high logic levels, then a type 2 capacitive load 352 is connected to the power driver 350. If the signals V.sub.R1 to V.sub.RN-1 are all at low logic levels and signal V.sub.RN is at a high logic level, then a type N capacitive load 352 is connected to the power driver 350. If the signals V.sub.R1 to V.sub.RN are all at low logic levels, then no capacitive load is connected to the power driver 350. The microcontroller 320 reads the outputs of the registers 318-1 to 318-N, and performs any number of operations based on which type of capacitive load 352 is connected to the power driver 350 or an absence of a capacitive load connected to the power driver 350.

(40) FIGS. 4A-4B illustrate timing diagrams associated with exemplary operation of the system 300 in accordance with another aspect of the disclosure. The timing diagrams are similar to the timing diagrams of FIGS. 2A-2B, respectively, except that the instant timing diagrams are for N+1 cases, rather than three (3) cases. Similar to FIGS. 2A-2B, the timing diagram of FIG. 4A deals with the capacitive load 352 operated in a first manner (e.g., moving it in a forward or clockwise direction), and the timing diagram of FIG. 4B deals with the capacitive load 352 operated in a second manner (e.g., moving it in a reverse or counter-clockwise direction).

(41) Summarizing the timing diagrams of FIG. 4A-4B, case 1 deals with a type 1 capacitive load 352 (the load with the highest capacitance) connected to the power driver 350. In such a case, the current-related voltage V.sub.I has a negative peak coincidental with the trailing edge of the driving voltage V.sub.D and that exceeds all of the thresholds V.sub.TH1-F to V.sub.THN-F in the negative direction. This results in all of the window comparators 314-1 to 314-N generating signals V.sub.P1 to V.sub.PN with pulses. The pulses cause the registers 318-1 to 318-N to produce signals V.sub.R1 to V.sub.RN at high logic levels, respectively. The microprocessor 320 interprets the high logic levels at the outputs of the registers 318-1 to 318-N as a type 1 capacitive load 352 connected to the power driver 350. Once the outputs of the registers 318-1 to 318-N are read, the microprocessor 320 issues a reset (e.g., an inverted pulse) to reset the registers to ensure that they output signals V.sub.R1 to V.sub.RN at low logic levels. The microcontroller 320 then performs any number of operations based on detecting that the type 1 capacitive load 352 is connected to the power driver 350. The other cases operate in a similar manner as indicated in the timing diagrams.

(42) FIG. 5A illustrates a block diagram of yet another exemplary system 500 for detecting the presence and type of capacitive load 552 connected to a power driver 550 in accordance with another aspect of the disclosure. In summary, the system 500 comprises a detection circuit 510 that rectifies or generates the absolute value of the current-related threshold V.sub.I to eliminate having two values for consideration. The detection circuit 510 includes a peak and hold device to generate an output indicative of the peak current, and an analog-to-digital converter (ADC) to generate a digital word indicative of the peak current. Based on the digital word, a microprocessor determine whether a capacitive load is connected to the power driver and, if connected, the type of capacitive load.

(43) In particular, the detection circuit 510 comprises a differential amplifier 512, an absolute value amplifier 514, a peak and hold amplifier 516, an analog-to-digital converter (ADC) 518, and a microcontroller 520. The differential amplifier 512 generates a current-related voltage V.sub.I based on the current I flowing between the power driver 550 and the capacitive load 552 by sensing the voltage across the current-sensing resistor R.sub.S. The absolute value amplifier 514 rectifies the current-related voltage V.sub.I in order to generate an absolute-value or rectified current-related voltage V.sub.A.

(44) The peak and hold amplifier 516 detects the peak of the rectified current-related voltage V.sub.A and generates a signal V.sub.H with a constant amplitude at the peak value. The ADC 518 generates a digital word W.sub.H indicative of the amplitude of the signal V.sub.H from the peak and hold amplifier 516. The microcontroller 520 receives the digital word W.sub.H from the ADC 518, and determines the presence and the type of capacitive load 352 based on the digital word W.sub.H. Once the microcontroller 520 has performed the measurement, it sends a reset signal to the peak and hold amplifier 516 to cause the signal V.sub.H to be at substantially zero (0) Volt. The magnitude of the digital word W.sub.H is a function of the current I. The microcontroller 520 may use a table to map the digital word W.sub.H to the type of capacitive load 552 or to an entry indicating an absence of the capacitive load 552.

(45) FIG. 5B illustrates a timing diagram associated with exemplary operation of the system 500 in accordance with another aspect of the disclosure. In this example, the capacitive load 552 may comprise a PICOMOTER configured to rotate in a clockwise (CW) manner or a counter-clockwise (CCW) manner. However, as frequently mentioned herein, the capacitive load 552 may comprise any type of capacitive load including other types of piezoelectric actuators and other types of devices. The timing diagram is similar to the previously-discussed timing diagrams, and depicts two cases: (1) the CW case where the PICOMOTER is operated to rotate in a clockwise manner; and (2) the CCW case where the PICOMOTER is operated to rotate in a counter-clockwise manner.

(46) Considering the CW case, a drive voltage V.sub.D is generated by the power driver 550. The drive voltage V.sub.D has a relatively slow rising leading edge to cause the PICOMOTER to rotate in a clockwise manner, and has a relatively fast falling trailing edge to prevent the rotation of the PICOMOTER in a counter-clockwise manner. In response to the drive voltage V.sub.D, the current I, as indicated by the current-related voltage V.sub.I generated by the differential amplifier 512, has a small positive rise/fall substantially coincidental with the leading edge of the drive voltage V.sub.D, and a negative peak substantially coincidental with the trailing edge of the drive voltage V.sub.D.

(47) The absolute value amplifier 514 rectifies the current-related voltage V.sub.I to generate a rectified voltage V.sub.A to invert the negative peak into a positive peak V.sub.PK. The peak and hold amplifier 516 detects the positive peak V.sub.PK of the rectified voltage V.sub.A and generates a constant amplitude signal V.sub.H at the peak value. The ADC 518 generates a digital word W.sub.H with a value W.sub.PK (related to the amplitude V.sub.PK of the signal V.sub.D. The microcontroller 520 reads the value W.sub.PK (to determine the type of PICOMOTER, or more generally, the type of capacitive load 552 connected to the power driver 550 or whether there is a PICOMOTER or capacitive load connected to the power driver 550. The microcontroller 520 then generates a reset signal (e.g., an inverted pulse) to reset the peak and hold amplifier 516 so that it generates an inactive output (e.g., zero (0) Volt). Based on the determination, the microcontroller 520 may perform any number of operations.

(48) Considering the CCW case, a drive voltage V.sub.D is generated by the power driver 550. The drive voltage V.sub.D has a relatively fast rising leading edge to prevent the PICOMOTER from rotating in a clockwise manner, and has a relatively slow falling trailing edge to cause the PICOMOTER to rotate in a counter-clockwise manner. In response to the drive voltage V.sub.D, the current I, as indicated by the current-related voltage V.sub.I generated by the differential amplifier 512, has a positive peak substantially coincidental with the leading edge of the drive voltage V.sub.D, and a small negative fall/rise substantially coincidental with the trailing edge of the drive voltage V.sub.D.

(49) The absolute value amplifier 514 rectifies the current-related voltage V.sub.I to generate a rectified voltage V.sub.A. In this case, the signal of interest, the positive peak voltage, is already positive. The peak and hold amplifier 516 detects the peak V.sub.PK of the rectified voltage V.sub.A and generates a constant amplitude signal V.sub.H at the peak value. The ADC 518 generates a digital word W.sub.H with a value W.sub.PK related to the amplitude V.sub.PK of the signal V.sub.H. The microcontroller 520 reads the value W.sub.PK to determine the type of PICOMOTER or more generally, the type of capacitive load 552 connected to the power driver 550 or whether there is PICOMOTER or capacitive load is connected to the power driver 550. The microcontroller 520 then generates a reset signal (e.g., an inverted pulse) to reset the peak and hold amplifier 516 so that it generates an inactive output (e.g., zero (0) Volt). Based on the determination, the microcontroller 520 may perform any number of operations.

(50) FIG. 6 illustrates a block diagram of still another exemplary system 600 for detecting the presence and type of load 652 that may be connected to a power driver 650 in accordance with another aspect of the disclosure. The discussion of the system 600 summarizes the principles upon which all the previous embodiments operate. The system 600 comprises a power driver 650, a load 652 (if any) coupled to the power driver 650, and a detection apparatus 610.

(51) The detection principle operates as follows. The power driver 650 is operated to generate a drive signal S.sub.D, which could be a current or a voltage. In response to the drive signal S.sub.D, the detection apparatus 610 measures a characteristic of the load 652 in response to the drive signal S.sub.D by sensing a parameter responsive to the drive signal S.sub.D. The characteristic of the load 652 may relate to the capacitance of the load. Based on the sensed parameter or characteristic of the load 652, the detection apparatus 610 determines whether a load is in fact connected to the power driver 650, and if connected, the type of load connected to the power driver 650. The detection apparatus 610 may then perform any number of operations based on its determination.

(52) While the invention has been described in connection with various embodiments, it will be understood that the invention is capable of further modifications. This application is intended to cover any variations, uses or adaptation of the invention following, in general, the principles of the invention, and including such departures from the present disclosure as come within the known and customary practice within the art to which the invention pertains.