DISPLAY

Abstract

A device configuration designed to mitigate display defects resulting from voltage drops in current supply lines offers a display with better display quality. The display includes: a plurality of VOLETs arranged in arrays along a first direction and a second direction; a data line supplying a voltage for controlling gate electrodes of the plurality of VOLETs; TFTs each connected between a gate electrode of each of the VOLET and the data line and controlling voltage supply to the gate electrodes of the VOLETs; a gate line connected to gate electrodes of the TFTs and transmitting a signal that controls the TFTs; a plurality of current supply lines extending along the first direction and supplying a current to each of a group of VOLETs aligned along the first direction; and an auxiliary line extending along the second direction and connecting at least two of the plurality of current supply lines.

Claims

1. A plurality of vertical organic light emitting transistors arranged in arrays along a first direction and a second direction orthogonal to the first direction; a data line supplying a voltage for controlling gate electrodes of the plurality of vertical organic light emitting transistors; thin-film transistors each connected between a gate electrode of each of the vertical organic light emitting transistors and the data line and controlling voltage supply to the gate electrodes of the vertical organic light emitting transistors; a gate line connected to gate electrodes of the thin-film transistors and transmitting a signal that controls the thin-film transistors; a plurality of current supply lines extending along the first direction and supplying a current to each of a group of vertical organic light emitting transistors aligned along the first direction; and at least one auxiliary line extending along the second direction and connecting at least two of the plurality of current supply lines.

2. The display according to claim 1, wherein the auxiliary line is formed closer to a substrate than a source electrode of the vertical organic light emitting transistor.

3. The display according to claim 1, wherein the auxiliary line includes a wiring line made of a material that makes up the gate line and formed in a layer in which the gate line is provided.

4. The display according to claim 1, wherein the auxiliary line includes a wiring line made of a material that makes up the gate electrode of the vertical organic light emitting transistor and configured in a layer in which the gate electrode of the vertical organic light emitting transistor is provided.

5. A display comprising: a plurality of vertical organic light emitting transistors arranged in arrays along a first direction and a second direction orthogonal to the first direction; a data line supplying a voltage for controlling gate electrodes of the plurality of vertical organic light emitting transistors; thin-film transistors each connected between the gate electrode of each of the vertical organic light emitting transistors and the data line and controlling voltage supply to the gate electrodes of the vertical organic light emitting transistors; and a gate line connected to the gate electrodes of the thin-film transistors and transmitting a signal that controls the thin-film transistors, at least two of the plurality of vertical organic light emitting transistors adjacent each other having a source electrode layer continuously formed therebetween.

6. The display according to claim 5, further comprising a plurality of current supply lines extending along the first direction and supplying a current to each of a group of vertical organic light emitting transistors aligned along the first direction.

7. The display according to claim 6, further comprising at least one auxiliary line extending along the second direction and connecting at least two of the plurality of current supply lines.

8. The display according to claim 7, wherein the auxiliary line is formed closer to a substrate than a source electrode of the vertical organic light emitting transistor.

9. The display according to claim 7, wherein the auxiliary line includes a wiring line made of a material that makes up the gate line and formed in a layer in which the gate line is provided.

10. The display according to claim 7, wherein the auxiliary line includes a wiring line made of a material that makes up the gate electrode of the vertical organic light emitting transistor and configured in a layer in which the gate electrode of the vertical organic light emitting transistor is provided.

11. The display according to claim 2, wherein the auxiliary line includes a wiring line made of a material that makes up the gate line and formed in a layer in which the gate line is provided.

12. The display according to claim 2, wherein the auxiliary line includes a wiring line made of a material that makes up the gate electrode of the vertical organic light emitting transistor and configured in a layer in which the gate electrode of the vertical organic light emitting transistor is provided.

13. The display according to claim 3, wherein the auxiliary line includes a wiring line made of a material that makes up the gate electrode of the vertical organic light emitting transistor and configured in a layer in which the gate electrode of the vertical organic light emitting transistor is provided.

14. The display according to claim 8, wherein the auxiliary line includes a wiring line made of a material that makes up the gate line and formed in a layer in which the gate line is provided.

15. The display according to claim 8, wherein the auxiliary line includes a wiring line made of a material that makes up the gate electrode of the vertical organic light emitting transistor and configured in a layer in which the gate electrode of the vertical organic light emitting transistor is provided.

16. The display according to claim 14, wherein the auxiliary line includes a wiring line made of a material that makes up the gate electrode of the vertical organic light emitting transistor and configured in a layer in which the gate electrode of the vertical organic light emitting transistor is provided.

Description

BRIEF DESCRIPTION OF DRAWINGS

[0061] FIG. 1 is a schematic configuration diagram of a part of a display in one embodiment;

[0062] FIG. 2 is a circuit diagram of a light emitting part in region A1 of the display of FIG. 1;

[0063] FIG. 3 is a top plan view of a schematic device configuration of the light emitting part and its vicinity in one embodiment;

[0064] FIG. 4 is a cross-sectional view along A-A′ of FIG. 3;

[0065] FIG. 5 is a cross-sectional view along B-B′ of FIG. 3;

[0066] FIG. 6 is a top plan view of a schematic device configuration of the light emitting part and its vicinity in one embodiment;

[0067] FIG. 7 is a cross-sectional view along A-A′ of FIG. 6;

[0068] FIG. 8 is a cross-sectional view along B-B′ of FIG. 6;

[0069] FIG. 9 is a top plan view of a schematic device configuration of the light emitting part and its vicinity in one embodiment; and

[0070] FIG. 10 is a cross-sectional view along A-A′ of FIG. 9.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0071] Hereinafter, a configuration of a display of the present invention is described with reference to the drawings. The drawings referred to below each provide schematic illustrations. The dimensional ratios and numbers of elements in the drawings are not necessarily the same as the actual dimensional ratios and numbers of elements.

First Embodiment

[0072] FIG. 1 is a schematic configuration diagram of a part of a display 1 in one embodiment. As illustrated in FIG. 1, the display 1 of this embodiment includes arrays of light emitting parts 10, each including a vertical organic light emitting transistor, data lines 11 that supply a voltage to gate electrodes of the vertical organic light emitting transistors, current supply lines 12 that supply a current to source electrodes of the vertical organic light emitting transistors, gate lines 13 that transmit signals for controlling thin-film transistors, and auxiliary lines 14 that connect the current supply lines 12.

[0073] The display 1 also includes, in an outer peripheral part thereof, a source driver 15a that supplies a voltage to the data lines 11 to apply a voltage to the gate electrodes of the vertical organic light emitting transistors in accordance with image data to be displayed, a current supply part 15b that supplies a current to the current supply lines 12 so that a current is supplied to the source electrodes of the vertical organic light emitting transistors, and a gate driver 15c that outputs control signals for the thin-film transistors to the gate lines 13.

[0074] FIG. 2 is a detailed circuit diagram of light emitting parts 10 in region A1 of the display 1 of FIG. 1. As illustrated in FIG. 2, the light emitting part 10 includes a vertical organic light emitting transistor 20, a thin-film transistor 21 that controls voltage supply to the gate electrode of the vertical organic light emitting transistor 20, and a capacitor 23 connected between the source electrode and the gate electrode of the vertical organic light emitting transistor 20. In the description with reference to FIG. 1 and FIG. 2, a direction along which the current supply line 12 extends shall be referred to as the X direction (first direction), and a direction along which the auxiliary line 14 extends shall be referred to as the Y direction (second direction).

[0075] The data line 11 is a wiring line for applying a voltage output from the source driver 15a to the gate electrode of the vertical organic light emitting transistor 20 via the thin-film transistor 21 in order to adjust the emission luminance of the vertical organic light emitting transistor 20 in accordance with the image being displayed. While the data lines 11 are formed along the X direction in this embodiment, the data lines may be formed along the Y direction.

[0076] The current supply lines 12 are formed along the X direction to be connected to each of the group of vertical organic light emitting transistors 20 aligned along the X direction. Each current supply line 12 supplies a current output from the current supply part 15b to the source electrode of each vertical organic light emitting transistor included in the group of the vertical organic light emitting transistors 20.

[0077] The gate lines 13 are connected to the gate electrodes of the thin-film transistors 21 so that the control signals output from the gate driver 15c are transmitted to the gate electrodes of the thin-film transistors 21. Power application and control signal transmission between the gate electrodes of the vertical organic light emitting transistors 20 and the data lines 11 is thus controlled by the thin-film transistors 21 being switched on and off. While the gate lines 13 are formed along the Y direction in this embodiment, the gate lines may be formed along the X direction.

[0078] The auxiliary line 14 extends along the Y direction between the light emitting parts 10 aligned along the X direction. The auxiliary line 14 need not necessarily be formed between adjacent ones of all of the light emitting parts 10 aligned along the X direction. While the current supply lines 12 are formed along the X direction and the auxiliary lines 14 are formed along the Y direction in this embodiment, the current supply lines 12 may be formed along the Y direction and the auxiliary lines 14 may be formed along the X direction.

[0079] The capacitor 23 is a voltage retaining device between the gate electrode and the source electrode of the vertical organic light emitting transistor 20 disposed to maintain the image being displayed for a predetermined time during the off-state of the thin-film transistor 21.

[0080] Next, the structure of each device formed on a substrate will be described. FIG. 3 is a top plan view of a schematic device configuration of the light emitting part 10 and its vicinity in one embodiment. FIG. 4 is a cross-sectional view along A-A′ of FIG. 3. As illustrated in FIG. 3 and FIG. 4, the vertical organic light emitting transistor 20 and thin-film transistor 21 are provided in a region delineated by the data line 11, current supply lines 12, and gate line 13.

[0081] FIG. 5 is a cross-sectional view along B-B′ of FIG. 3. As illustrated in FIG. 3 and FIG. 5, the auxiliary line 14 is formed in the same layer as the gate line 13 that is connected to a gate electrode layer 21g of the thin-film transistor 21 and made of the same material as the gate line 13. Hereinafter, the auxiliary line 14 made of the same material and in the same layer as the gate line 13 shall be referred to as a wiring layer auxiliary line 14a.

[0082] The substrate 30 is transmissive to light and outputs the light emitted from the vertical organic light emitting transistor 20 to the outside. Specific materials will be described later.

[0083] In the following description, the direction along which the data line 11 and current supply lines 12 extend shall be referred to as the X direction, the direction along which the gate line 13 extends as the Y direction, the direction orthogonal to these as the Z direction, and a direction away from the substrate 30 (forward in the Z direction) as an upper layer.

[0084] The vertical organic light emitting transistor 20 is configured to include, from the upper layer, a drain electrode layer 20d corresponding to a cathode electrode, an organic EL layer 20c, an organic semiconductor layer 20a, and a source electrode layer 20s formed by coating a surface of a surface layer 31 with a conductive material containing carbon (carbon nanotube in this embodiment), and, in a layer underneath, a gate electrode layer 20g, via a gate insulating layer 20h made of a dielectric material. Voltage application to the gate electrode layer 20g changes the Schottky barrier between the organic semiconductor layer 20a and the source electrode layer 20s, and a current flows from the source electrode layer 20s to the organic semiconductor layer 20a and organic EL layer 20c when a predetermined threshold is exceeded, allowing the vertical organic light emitting transistor 20 to emit light.

[0085] In the display 1 of this embodiment, the substrate 30 is made of a material transmissive to visible light. The gate electrode layer 20g and the source electrode layer 20s are both transmissive to visible light, and configured such that there is a gap that allows visible light to pass through, causing the light output from the organic EL layer 20c to pass through the substrate 30 and exit to the outside, whereby images are displayed. This configuration wherein light is passed through the substrate 30 and emitted is referred to as “bottom emission type”, and is advantageous in that production is easy due to simple interconnections between electrodes.

[0086] The source electrode layer 21s and the drain electrode layer 21d of the thin-film transistor 21 are connected via an oxide semiconductor layer 21a, and the gate electrode layer 21g is formed below the oxide semiconductor layer 21a via an insulating layer or a dielectric layer. A voltage applied to the gate electrode layer 21g creates respective conductive channels in the oxide semiconductor layer 21a so that power is supplied to the source electrode layer 21s and drain electrode layer 21d.

[0087] The source electrode layer 21s and the drain electrode layer 21d of the thin-film transistor 21 are connected to the data line 11 and the gate electrode layer 20g of the vertical organic light emitting transistor 20, respectively.

[0088] As illustrated in FIG. 3, the vertical organic light emitting transistor 20 is formed to cover substantially the entire region delineated by the data line 11, current supply lines 12, and gate line 13 to achieve a high luminance for the display 1, while the thin-film transistor 21 is formed to take up as little space as possible in a corner of this delineated region so as to minimize the influence on the light emitting region of the vertical organic light emitting transistor 20.

[0089] The capacitor 23 is not shown in FIG. 3 to FIG. 5. The vertical organic light emitting transistor 20 of this embodiment includes the capacitor 23 as a parasitic device, with the source electrode layer 20s and the gate electrode layer 20g being arranged opposite each other via the gate insulating layer 20h as shown in FIG. 4 or FIG. 5. This capacitor 23 is also capable of serving the function of voltage retention. Another capacitor may be added if the capacitance provided by this capacitor 23 configured as a parasitic device is not sufficient.

[0090] Below, examples of materials that may be used for respective layers are listed.

[0091] For the gate line 13 and wiring layer auxiliary line 14a, aluminum (Al), titanium (Ti), molybdenum (Mo), tungsten (W), niobium (Nb), magnesium (Mg), silver (Ag), copper (Cu), and metal alloys of combinations thereof may be adopted.

[0092] For the substrate 30, glass materials, or plastics such as PET (Poly Ethylene Terephthalate), PEN (Poly Ethylene Naphthalate), and polyimide may be adopted.

[0093] For the drain electrode layer 20d of the vertical organic light emitting transistor 20, single- or multi-layer graphene, carbon nanotube, aluminum (Al), silver (Ag), lithium fluoride (LiF), molybdenum oxide (MoXOY), indium tin oxide (ITO), and zinc oxide (ZnO) may be adopted.

[0094] For the gate electrode layer 20g of the vertical organic light emitting transistor 20, metal- or non-doped transparent conductive oxides such as zinc oxide (ZnO), indium oxide (In2O3), tin dioxide (SnO2), and cadmium oxide (CdO) which may be doped with a metal such as aluminum (Al), tin (Sn), yttrium (Y), scandium (Sc), and gallium (Ga), and materials containing combinations thereof, or, aluminum (Al), gold (Au), silver (Ag), platinum (Pt), cadmium (Cd), nickel (Ni), and tantalum (Ta), and combinations thereof, and p- or n-doped silicon (Si) or gallium arsenide (GaAs) may be adopted.

[0095] For the gate insulating layer 20h between the surface layer 31 and the gate electrode layer 20g of the vertical organic light emitting transistor 20, silicon oxide (SiOX), aluminum oxide (Al2O3), silicon nitride (Si3N4), yttrium oxide (Y2O3), lead titanate (PbTiOX), aluminum titanate (AlTiOX), glass, and organic compounds such as parylene polymer, polystyrene, polyimide, polyvinylphenol, polymethyl methacrylate, and fluoropolymer may be adopted.

[0096] Materials that can be adopted for the organic semiconductor layer 20a of the vertical organic light emitting transistor 20 include: linear annulated polycyclic aromatic compounds (or acene compounds) such as naphthalene, anthracene, rubrene, tetracene, pentacene, hexacene, and derivatives thereof; pigments such as, for example, copper phthalocyanine (CuPc) compounds, azo compounds, perylene compounds and derivatives thereof; low-molecular compounds such as, for example, hydrazone compounds, triphenyl methane compounds, diphenylmethane compounds, stilbene compounds, arylvinyl compounds, pyrazoline compounds, triphenylamine derivatives (TPD), arylamine compounds, low-molecular weight amine derivatives (α-NPD), 2,2′,7,7′-tetrakis(diphenylamino)-9,9′-spirobifluorene (Spiro-TAD), N,N′-di(1-naphthyl)-N,N′-diphenyl-4,4′-diamonobiphenyl (Spiro-NPB), 4,4′,4″-tris[N-3-methylphenyl-N-phenylamino]-triphenylamine (mMTDATA), 2,2′,7,7′-tetrakis(2,2-diphenylvinyl)-9,9-spirobifluorene (Spiro-DPVBi), 4,4′-bis(2,2-diphenylvinyl)biphenyl (DPVBi), (8-quinolinolate)aluminum (Alq), tris(8-quinolinolato)aluminum (Alq3), tris(4-methyl-8quinolinolato)aluminum (Almq3), and derivatives thereof; polymer compounds such as, for example, poly-thiophene, poly(p-phenylenevinylene) (PPV), polymers containing biphenyl groups, polymers containing dialkoxy groups, alkoxyphenyl-PPV, phenyl-PPV, phenyl/dialkoxy-PPV copolymer, poly(2-methoxy-5-(2′-ethylhexyloxy)-1,4-phenylenevinylene) (MEH-PPV), poly(ethylenedioxythiophene) (PEDOT), poly(styrenesulfonic acid) (PSS), poly(aniline) (PAM), poly(N-vinylcarbazole), poly(vinylpyrene), poly(vinylanthracene), pyrene-folmaldehyde resin, halogenated ethylcarbazole-folmaldehyde resin, and modifications thereof; n-type transport organic low molecules, oligomers, or polymers, such as, for example, 5,5_-diperfluorohexyl carbonyl-2,2_:5_,2_:5_,2_-quaterthiophene (DFHCO-4T), DFH-4T, DFCO-4T, P(NDI2OD-T2), PDI8-CN2, PDIF-CN2, and F16CuPc, fullerene, naphthalene, and perylene, and oligothiophene derivatives; and aromatic compounds having a thiophene ring, such as thieno[3,2-b]thiophene, dinaphthyl[2,3-b:2′,3′-f]thieno[3,2-b]thiophene (DNTT), 2-decyl-7-phenyl[1]benzothieno[3,2-b][1]benzothiophene (BTBT), and so on.

[0097] Suitable selection of organic semiconductors with a matching energy level allows for favorable use of a hole injection layer, a hole transport layer, an organic EL layer, an electron transport layer, an electron injection layer, and so on for the vertical organic light emitting transistor 20, which are used in a standard OLED display. The material of the organic EL layer 20c is selected from the group above so that light emitted to the outside is adjusted to have a color such as red, green, and blue. Alternatively, the vertical organic light emitting transistor 20 may be configured to emit white light, i.e., the same vertical organic light emitting transistor 20 may be configured to selectively emit light of a desired color using a color filter.

[0098] The surface layer 31 is a layer formed over the gate insulating layer 20h for the purpose of securing the source electrode layer 20s (in particular, CNT layer). The surface layer 31 may be formed by applying a composition containing a binder resin made of a silane coupling material, an acrylic resin and the like.

[0099] For the oxide semiconductor layer 21a included in the thin-film transistor 21, In—Ga—Zn—O semiconductors, Zn—O semiconductors (ZnO), In—Zn—O semiconductors (IZO(Registered Trademark)), Zn—Ti—O semiconductors (ZTO), Cd—Ge—O semiconductors, Cd—Pb—O semiconductors, CdO (cadmium oxide), Mg—Zn—O semiconductors, In—Sn—Zn—O semiconductors (e.g., In2O3-SnO2-ZnO), In—Ga—Sn—O semiconductors, and so on, may be adopted.

[0100] While the thin-film transistor 21 in this embodiment is an oxide semiconductor, the thin-film transistor may be made of amorphous silicon. The semiconductor may be either p-type or n-type. Any of the configurations, including, specifically, a staggered type, an inverted staggered type, a coplanar type, an inverted coplanar type, and so on, may be adopted.

[0101] A bank layer 24 is formed between the organic semiconductor layer 20a and the surface layer 31 for insulation. At points where the source electrode layer 20s is connected to the data line 11, the bank layer 24 is formed such as to fill the gap provided in the surface layer 31 and gate insulating layer 20h for allowing electrical connection.

[0102] For the vertical organic light emitting transistor 20, the vertical organic light emitting transistor 20 that is described in Patent Documents 1 and 2 mentioned above may be employed. Further, the configuration described in Patent Document 3 may also be adopted.

[0103] The configuration described above wherein the current supply lines 12 are connected by the wiring layer auxiliary lines 14a allows the connection points between the current supply lines 12 and the wiring layer auxiliary lines 14a to have the same voltage value as that at the connection points of other connected current supply lines 12. Namely, in the event of an extreme local voltage drop due to variations in the resistance of the current supply lines 12, the voltage is lifted up by other current supply lines 12 connected to the wiring layer auxiliary lines 14a. The more there are connection points between the current supply lines 12 and the wiring layer auxiliary lines 14a as in this embodiment, the more entirely the voltage of the current supply lines 12 is made uniform over the display 1.

[0104] The voltage of the current supply lines 12 connected by the wiring layer auxiliary lines 14a is made uniform in this way. Thus the display 1 with better display quality, wherein a local voltage drop rarely occurs in each current supply line 12 so that display defects are unlikely to be recognized, is realized.

Second Embodiment

[0105] The configuration of a second embodiment of the display 1 of the present invention will be described, mainly centering on the points different from the first embodiment.

[0106] FIG. 6 is a top plan view of a schematic device configuration of the light emitting part 10 and its vicinity in one embodiment. FIG. 7 is a cross-sectional view along A-A′ of FIG. 6. FIG. 7, which is a cross-sectional view along A-A′ of FIG. 6, illustrates the same configuration as the first embodiment in FIG. 4. FIG. 8 is a cross-sectional view along B-B of FIG. 6. As illustrated in FIG. 6 and FIG. 8, in the second embodiment, in addition to the wiring layer auxiliary line 14a, an electrode layer auxiliary line 14b made of the same material as the gate electrode layer 20g is formed in parallel thereto in the same layer as the gate electrode layer 20g of the vertical organic light emitting transistor 20.

[0107] Since the electrode layer auxiliary line 14b is configured in the same layer as the gate electrode layer 20g of the vertical organic light emitting transistor 20 as noted above, this auxiliary line cannot be provided in the region where the vertical organic light emitting transistor 20 is formed. Namely, the electrode layer auxiliary line is formed in a different region from where there is the vertical organic light emitting transistor 20. However, since the wiring layer auxiliary line 14a and the electrode layer auxiliary line 14b are formed in different layers as illustrated in FIG. 6 and FIG. 8, they can be overlapped in the Z direction.

[0108] That is, this configuration allows the respective resistance values of both auxiliary lines 14 (14a and 14b) to be reduced while minimizing a size reduction of the light emitting region. The smaller the resistance of the auxiliary lines 14 (14a and 14b), the smaller the voltage drop caused by the current flowing through the auxiliary lines 14 (14a and 14b), which enables the voltage difference in each current supply line 12 to be reduced even more. This further ensures that local voltage drops rarely occur in each current supply line 12, and allows for realization of the display 1 with better display quality.

Third Embodiment

[0109] The configuration of a third embodiment of the display 1 of the present invention will be described, mainly centering on the points different from the first and second embodiments.

[0110] While the description given above outlines a configuration where the wiring layer auxiliary lines 14a alone are provided, and a configuration where both the wiring layer auxiliary lines 14a and the electrode layer auxiliary lines 14b are provided, it is also possible to provide only the electrode layer auxiliary lines 14b.

Fourth Embodiment

[0111] The configuration of a fourth embodiment of the display 1 of the present invention will be described, mainly centering on the points different from the first, second, and third embodiments.

[0112] FIG. 9 is a top plan view of a schematic device configuration of the light emitting part 10 and its vicinity in one embodiment. FIG. 10 is a cross-sectional view along A-A′ of FIG. 9. As illustrated in FIG. 9 and FIG. 10, in the fourth embodiment, the source electrode layer 20s of the vertical organic light emitting transistor 20 extends continuously between at least two or more pixels so that it substantially functions as the current supply line 12. Additionally, during the display 1 manufacturing process, after the formation of the source electrode layer 20s, additional treatment and/or process, such as chemical doping can be done to the source electrode layer 20s, so that the electrical conductivity of the source electrode layer 20s can be increased dramatically. After the bank layer 24 is formed, another treatment and/or process, such as chemical treatment, heat treatment and/or UV irradiation can be done to the exposed region of the source electrode layer 20s to reverse the effect of the prior treatment so that the source electrode layer 20s can recover the initial intrinsic resistivity and electronic characterization, while the bank layer 24 serves as a mask to maintain the increased electrical conductivity of the source electrode layer 20s that is under its coverage.

[0113] The more there are pixels having the source electrode layers 20s coupled together as in the fourth embodiment, the more the voltage in the source electrode layers 20s of respective vertical organic light emitting transistors 20 is made uniform over the entire display 1, so that the display 1 hardly showing visible display defects and demonstrating better display quality is realized.

[0114] Although the source electrode layer 20s is described as being continuous between respective vertical organic light emitting transistors 20 so that no current supply lines 12 are provided in the fourth embodiment, it is also possible to form current supply lines 12 along with the configuration of the fourth embodiment.

Fifth Embodiment

[0115] The configuration of a fifth embodiment of the display 1 of the present invention will be described, mainly centering on the points different from the first to fourth embodiments.

[0116] The fourth embodiment wherein current supply lines 12 are provided can be combined with any of the configurations of the first to third embodiments, and with such combined use of measures, the voltage difference in each current supply line 12 can be reduced even more as compared to that of the fourth embodiment. This ensures that local voltage drops rarely occur in each current supply line 12, and allows for realization of the display 1 with better display quality.

Other Embodiments

[0117] Below, other embodiments will be described.

[0118] <1> The display 1 may be configured to display images by emitting light output from the organic EL layer 20c to the opposite side from the substrate 30. Such a configuration is referred to as “top emission type” and advantageous in that it allows devices and wirings to be configured also between the vertical organic light emitting transistor 20 and the substrate 30.

[0119] <2> The configurations and control methods of the display 1 described above are merely examples and the present invention is not limited to the various illustrated configurations.