MULTIPHASE DC-DC CONVERTER AND METHOD FOR CONTROLLING A MULTIPHASE DC-DC CONVERTER

Abstract

A method for controlling a multiphase DC-DC converter with two or more phase circuits, each with a switch arranged to control an inductor current through an inductor, the phase circuit is arranged to generate a phase current contributing to a total current to be delivered to an output side of the multiphase DC-DC converter. The method includes switching two or more of the phase circuits in Boundary Conduction Mode to generate interleaved phase current pulses, with a period length and a nominal turn-on time period of the switch; and, in at least one of the two or more of the phase circuits being switched, and for successive phases, repeatedly adapting the turn-on time period for controlling the length of the pulses of the inductor current to minimise a difference from the period length.

Claims

1. A control method for controlling a multiphase DC-DC converter the multiphase DC-DC converter being arranged for exchanging electrical power between an input side an output side, the multiphase DC-DC converter comprising two or more phase circuits, each phase circuit comprising a switch and an inductor, the switch being arranged to control an inductor current I.sub.L through the inductor, the phase circuit being arranged to generate a phase current contributing to a total current to be delivered to an output side of the multiphase DC-DC converter, the method comprising: switching two or more of the phase circuits in Boundary Conduction Mode (BCM) to generate interleaved phase current pulses, with a period length T and a nominal turn-on time period t.sub.on of the switch; in at least one of the two or more of the phase circuits being switched, and for successive phases, repeatedly adapting the turn-on time period t.sub.on for controlling the length of the pulses of the inductor current I.sub.L to minimise a difference from the period length T.

2. The control method of claim 1, the multiphase DC-DC converter being arranged for exchanging electrical power between an input side, comprising a first input terminal and a second input terminal, and an output side, comprising a first output terminal and a second output terminal, the multiphase DC-DC converter comprising two or more phase circuits, each phase circuit comprising an inductor connected between the first input terminal and a bridge point, an upper branch switching unit connected between the bridge point and the first output terminal, and a switch with a parallel freewheeling diode connected between the bridge point and the second input terminal and second output terminal, the control method comprising the steps of, determining a number N of phase circuits to be active; determining an initial value for a turn-on time period t.sub.on; determining a period length T; for at least one of the phase circuits that are to be active; turning on the switch of the phase circuit, causing an inductor current I.sub.L and the switch to increase over time, and determining a target turn-on time when the switch shall be turned on the next time; after the turn-on time period t.sub.on, switching off the switch, causing the inductor current I.sub.L to flow through the upper branch switching unit and decrease over time; after the current through the inductor has returned to zero, at a zero crossing time, turning the switch on again and repeating the above steps; when repeating the above steps, controlling the turn-on time period t.sub.on by increasing the turn-on time period t.sub.on if the zero crossing time is before the target turn-on time and by decreasing the turn-on time period t.sub.on if the zero crossing time is after the target turn-on time.

3. The control method of 1, wherein the initial value for the turn-on time period t.sub.on of a phase circuit is computed as: $t_{\mathrm{on}}=\frac{2.Math.I_{\mathrm{mean}}.Math.L}{U_{\mathrm{IN}}}$ wherein U.sub.IN is the voltage at the input side, L is the inductance value of the inductor and I.sub.mean is the mean current to be delivered by the phase circuit.

4. The control method of claim 1, wherein in the active phase circuits, the respective period length T is computed as $T=t_{\mathrm{on}}\frac{U_{\mathrm{OUT}}}{U_{\mathrm{OUT}}-U_{\mathrm{IN}}}$ wherein U.sub.OUT is the voltage at the output side.

5. The control method of claim 2, wherein the step of determining the target turn-on time comprises computing the target turn-on time as being offset from a reference time by the period length T divided by the number N of phase circuits that are active.

6. The control method of claim 2, wherein the step of turning the switch on again comprises one of: monitoring the voltage across the switch and turning on the switch when the voltage across the switch is zero; monitoring the voltage across the switch, and turning on the switch a predetermined time delay after the voltage across the switch falls under a predetermined threshold; monitoring the inductor current I.sub.L and turning on the switch when the inductor current I.sub.L becomes zero after having been negative due to a reverse current through the upper branch switching unit; monitoring the current through the upper branch switching unit, in particular a diode current, and turning on the switch when this current becomes zero after having been negative due to a reverse current through the upper branch switching unit.

7. The control method of claim 2, wherein the step of turning the switch on again comprises: when the inductor current I.sub.L has returned to zero, letting the current reverse its direction and continue to flow through the inductor and the upper branch switching unit until the upper branch switching unit is turned off and the inductor current I.sub.L, commutates to the freewheeling diode; turning on the switch; in particular wherein the upper branch switching unit is constituted by a diode, or comprises a diode, and is turned off by a reverse charge in the diode having built up, and in wherein a reverse charge of the diode is chosen so that the reverse current through the diode is sufficient to discharge capacitances between the bridge point and the second input terminal.

8. The method of claim 1, further comprising, for increasing the number N of phase circuits that are active to N+1, given a total current set point, in a pre-transition period of length Tpi, switching the switches of the N phase circuits to turn on at turn-on times, relative to this period, of 0, dTpi, 2.Math.dTpi, 3.Math.dTpi . . . (N−1).Math.dTpi where dTpi=Tpi/N; computing, for a post-transition period of length Tsi, target turn-on times for the N+1 phase circuits, relative to this period, as 0, dTsi, 2.Math.dTsi, 3.Math.dTsi . . . N.Math.dTsi where dTsi=Tsi/(N+1); in a transition period, switching the switches of the N phase circuits to turn on at the same turn-on times, relative to this period, as in the pre-transition period; in the transition period, for each of the N phase circuits, setting the turn-on time periods t.sub.on so that the current returns to zero at the respective target turn-on time in the post-transition period; in the transition period, after the turn-on time at (N−1).Math.dTpi, turn on the switch of the newly operated (N+1)th at a time and with a turn-on time period t.sub.on such that a deviation of the total current of all phase circuits in the transition period and the post-transition period from the total current set point is minimised.

9. The method of claim 1, further comprising, for decreasing the number N of phase circuits that are active to N−1, given a total current set point, in a pre-transition period of length Tpd, switching the switches of the N phase circuits to turn on at turn-on times, relative to this period, of 0, dTpd, 2.Math.dTpd, 3.Math.dTpd . . . (N−1).Math.dTpd where dTpd=Tpd/N; computing, for a post-transition period of length Tsd, target turn-on times for the N−1 phase circuits, relative to this period, as 0, dTsd, 2.Math.dTsd, 3.Math.dTsd . . . (N−2).Math.dTsd where dTsd=Tsd/(N−1); in a transition period, switching the switches of the N phase circuits to turn on at the same turn-on times, relative to this period, as in the pre-transition period; in the transition period, for each of the N phase circuits, except for the phase circuit whose target turn on time relative to this period is dTpd, setting the turn-on time periods t.sub.on so that the current returns to zero at the respective target turn-on time in the post-transition period; in the transition period, for the phase circuit whose target turn on time relative to this period is dTpd, setting the turn-on time period t.sub.on for one last pulse of this phase circuit such that a deviation of the total current of all phase circuits in the transition period and the post-transition period from the total current set point is minimised.

10. The method of claim 1, further comprising, for a transition between operation of the multiphase DC-DC converter in discontinuous conduction mode to boundary conduction mode, for one or more sets of np phase circuits each, np being two or more, for each of said sets: operating the respective np phase circuits of the set in discontinuous conduction mode to generate a sequence of np pairwise adjacent current pulses of period length T, each phase circuit contributing one of the current pulses of the sequence; not operating the respective np phase circuits of the set in discontinuous conduction mode, and instead operating one phase circuit in boundary conduction mode to continue the sequence of current pulses of period length T.

11. The method of claim 1, further comprising, for a transition between operation of the multiphase DC-DC converter in boundary conduction mode to discontinuous conduction mode, for one or more sets of np phase circuits each, np being two or more, for each of said sets: operating one phase circuit in boundary conduction mode to generate a sequence of current pulses with period length T in boundary conduction mode; not operating this one phase circuit in boundary conduction mode, and instead operating the respective np phase circuits of the set to continue the sequence of current pulses of period length T by operating the np phase circuits in discontinuous conduction mode to generate a sequence of np pairwise adjacent current pulses of period length T, each phase circuit contributing one of the current pulses of the sequence.

12. The method of claim 1, further comprising determining the period length T by operating one of the phase circuits, called master phase, with a turn-on time period t.sub.on that is determined according to a mean current to be delivered by this phase circuit, and operating one or more of the remaining active phase circuits to adapt their timing and period length to that of the master phase.

13. A multiphase DC-DC converter, comprising a controller comprising voltage sensors arranged for determining the voltage U.sub.IN at the input side, the voltage U.sub.OUT at the output side and the voltage U.sub.L across the inductor of each phase circuit, the controller being configured to perform the method of claim 1.

14. The multiphase DC-DC converter of claim 13, wherein in at least one of the phase circuits the upper branch switching unit comprises or consists of a diode that comprises a reverse recovery time that is sufficiently large to reverse the inductor current I.sub.L after the inductor current I.sub.L has returned to zero, such that the reversed current discharges a capacitance of the switch and of a freewheeling diode and of a parallel capacitance, if present, before turning on the switch.

15. The multiphase DC-DC circuit of claim 14, wherein the reverse recovery time that is sufficiently large for the reversed current to also discharge a capacitor arranged parallel to the switch before turning on the switch.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0094] The subject matter of the invention will be explained in more detail in the following text with reference to exemplary embodiments which are illustrated in the attached drawings, which schematically show:

[0095] FIG. 1 a prior art DC-DC boost converter and typical values in CCM operation;

[0096] FIG. 2 a multiphase DC-DC converter;

[0097] FIG. 3 the interleaving of current pulses;

[0098] FIG. 4 different trajectories of an inductor current I.sub.L;

[0099] FIG. 5 pertinent points in time when controlling the multiphase DC-DC converter;

[0100] FIG. 6 voltage and current trajectories for a switch of a phase circuit;

[0101] FIG. 7 activation of an additional phase circuit and insertion of its current pulses into a sequence of interleaved pulses;

[0102] FIG. 8 deactivation of a phase circuit and removal of its current pulses from a sequence of interleaved pulses;

[0103] FIG. 9 switching between DCM and BCM and vice versa; and

[0104] FIG. 10 a method for controlling the converter in DCM.

DETAILED DESCRIPTION OF THE INVENTION

[0105] In principle, identical parts are provided with the same reference symbols in the figures.

[0106] FIG. 2 shows a multiphase DC-DC converter 10. It includes, at an input side, a first input terminal 11 and second input terminal 12, with an input capacitance 13 arranged between the two input terminals. At an output side, it includes a first output terminal 14 and a second output terminal 15, with a output capacitance 16 arranged between the two output terminals. Two or more phase circuits 20 are arranged to connect the input and output terminals. In the present embodiment, the phase circuits 20 are boost converters, each with an inductor 21 arranged between the first input terminal 11 and a bridge point 22, an upper branch switching unit 23 constituted by a diode arranged between the bridge point 22 and the first output terminal 14, and a switch 24 with a freewheeling diode 25 arranged between the bridge point 22 and the second input terminal 12 and second output terminal 15. The switch 24 typically is a semiconductor switch, for example, a MOSFET, SiC, IGBT, GaN or other known switch type.

[0107] The figures show the upper branch switching unit 23 constituted by a diode, in other words, the upper branch switching unit 23 essentially is a diode. In other embodiments, the upper branch switching unit 23 includes variants such as an active switch in parallel with a diode (shown in the rightmost phase circuit 20 of FIG. 2 in an exemplary fashion, in reality, all phase circuits 20 typically have upper branch switching units 23 of the same kind), or as an active switch alone (not shown).

[0108] The expression “arranged between” means that the respective element connects two points in the circuit, and can carry a current between the two points, depending on the state of the element.

[0109] A controller 40 is arranged to control switching of the switches 24 and to measure, e.g., voltages and currents in the multiphase DC-DC converter 10, using sensors not shown in the figure. The controller 40 can be configured to control a current delivered to the output side to follow a total current set point. Such a set point can be determined by a supervisory control loop, depending on the circumstances under which the multiphase DC-DC converter 10 is operated.

[0110] The total current delivered to the output side is the sum of phase currents delivered by the phase circuits 20. The phase circuits 20 are operated to generate interleaved current pulses, in order to minimise a ripple in the total current. Depending on the required total current, according to the total current set point, the controller 40 can determine an optimal number of phase circuits 20 to be active, so that the total current is delivered while each of the phase circuits 20 operates in an optimal or near optimal condition, for example with regard to switching losses.

[0111] FIG. 3 shows the interleaving of current pulses with two phase circuits 20 being active. The top graph shows the inductor currents I.sub.L of the two phase circuits 20 being operated in BCM. In each of the successive current pulses, the inductor current I.sub.L rises to a positive peak value +I.sub.peak while the respective switch 24 is closed, driven by the input voltage across the inductor 21 and flowing through the switch 24. While the switch 24 is open, the inductor current I.sub.L decreases again, driven by the difference between the output and input voltage across the inductor 21. While the switch 24 is open, the inductor current I.sub.L flows through the upper branch switching unit 23 and constitutes the phase current delivered to the output side. The decreasing inductor current I.sub.L is allowed to go below zero, to a negative peak value −I.sub.peak before the switch 24 is closed again. This allows for zero voltage and/or zero current switching of the switch 24, as is explained further below.

[0112] The bottom graph shows the output current I.sub.A resulting from the addition of the two phase currents. This output current I.sub.A is filtered by the output capacitance 16. Its mean current I.sub.Amean can be controlled according to the total current set point. The input current I.sub.E with mean value I.sub.Emean is also shown. It is evident that for a switching frequency corresponding to a switching time period T.sub.SW in each phase circuit 20, the output current has a period of T.sub.SW/2 and the input current has a period of T.sub.SW/2 of the variation about its respective mean, corresponding to its respective ripple frequency. The ripple frequencies increase according to the number of active phase circuits 20.

[0113] FIG. 4 shows, for a phase circuit 20, different trajectories over time of an inductor current I.sub.L, together with a state SW of the corresponding switch 24. When SW is high, the switch 24 is closed, i.e., in a conducting state. When SW is low, the switch 24 is open, i.e., in a non-conducting state. Given a period length T (corresponding to a switching frequency) between a turn-on time 31 and a next turn-on time 31′, a turn-on time period t.sub.on during which the switch 24 is closed is to be chosen such that the phase circuit 20 operates in BCM. This is illustrated by the BCM mode trajectory 38 in which the returns to zero at the next turn-on time 31′.

[0114] The turn-on time period t.sub.on and the period length T are calculated such that a mean current to be delivered is generated and the current will return to zero at the end of the period length T. This requires only knowledge of the inductance value of the inductor 21, and is further determined by the input voltage and the mean current to be delivered by the phase circuit 20.

[0115] In more detail, the turn-on time period t.sub.on of a phase circuit 20 can be computed as

[00003]$t_{\mathrm{on}}=\frac{2.Math.I_{\mathrm{mean}}.Math.L}{U_{\mathrm{IN}}}$

wherein [0116] U.sub.IN is the voltage at the input side, which can be measured; [0117] L is the inductance value of the inductor 21, which can be known, by the design of the inductor 21, or by measurements; and [0118] I.sub.mean is the mean current to be delivered by the phase circuit 20. which can be given, e.g., by the controller 40.

[0119] The period length T can be computed as

[00004]$T=t_{\mathrm{on}}\frac{U_{\mathrm{OUT}}}{U_{\mathrm{OUT}}-U_{\mathrm{IN}}}$

wherein U.sub.OUT is the voltage at the output side.

[0120] If two or more phase circuits 20 are to operate synchronously, with a phase shift of their respective phase currents according to the number of active phase circuits 20, then their period lengths T should be the same. The period length T to be used for all phase circuit 20 can be determined by different approaches:

[0121] In an embodiment, one phase circuit 20 is designated as Master, and the others as Slaves. The Master is operated to run in “self-synchronised” mode. That is, the ideal period length T, computed as shown above is not reached exactly, but is determined by the actual time at which the inductor current I.sub.L reaches zero.

[0122] The period length T determined in this manner by the Master is then used for the Slave phase circuits 20.

[0123] In another embodiment, the controller 40 determines the period length T for all the active phase circuits 20 together. This implies prescribing a mean output current for each of the phase circuits 20 according to the total current set point, and adapting the period length T and turn-on time periods t.sub.on for the phase circuits 20 accordingly.

[0124] In each of the different approaches, for any phase circuit 20 that is not operated in “self-synchronised” mode, there is the issue of operating it in BCM with a prescribed period length T: [0125] With the turn-on time period t.sub.on computed as shown above, ideally, the BCM mode trajectory 38 should result. In reality, parameters of the phase circuit 20, in particular the inductance value, will not be perfectly correct, or will drift over time.

[0126] If the real inductance value is lower than expected, or due to other deviations, a CCM mode trajectory 37 will be realised: while the switch 24 is closed, the inductor current I.sub.L will rise more than expected. At the end of the period length T, at the next turn-on time 31′, the switch 24 is turned on again before the inductor current IL has returned to zero. Over several periods, the inductor current I.sub.L will keep rising. This is not acceptable.

[0127] If the real inductance value is higher than expected, or due to other deviations, a DCM mode trajectory 39 will be realised: while the switch 24 is closed, the inductor current I.sub.L will rise less than expected. At the end of the period length T, at the next turn-on time 31′, the switch 24 is turned on again after the inductor current I.sub.L has returned to zero. Depending on the corresponding delay, electromagnetic disturbances and switching losses will arise.

[0128] In order to keep avoid the phase circuit 20 operating in either CCM or DCM, and keep it in BCM, the period t.sub.on is controlled: rather than switching the switch 24 on at the predetermined next turn-on time 31′, it is switched on as for self-synchronised operation, that is, after the inductor current I.sub.L has returned to zero. The time at which it is switched on is compared to the predetermined next turn-on time 31′, and the turn-on time period t.sub.on is adapted according to the different in time. A controller such as a PID controller can be used, and more generally, a controller that brings a steady state error to zero. Consequently, over a sequence of periods, the turn-on time period t.sub.on is adapted so that the inductor current I.sub.L returns to zero at the desired respective next turn-on time 31′, corresponding to the desired or predetermined period length T.

[0129] The period length T in turn can be adapted or varied by another, outer control loop, in order for the mean current of the phase circuit 20 and the total current of the multiphase DC-DC converter 10 to follow a variation in their corresponding set points.

[0130] If the total current actually delivered by the multiphase DC-DC converter 10 is not as it ideally should be, according to the above formulae, then the outer control loop can adapt the total current and thereby the mean current to be delivered by each phase. This will in turn cause the turn-on time period t.sub.on and the period length T to be adapted.

[0131] FIG. 5 shows pertinent points in time when controlling the multiphase DC-DC converter: inductor current pulses from one phase circuit 20, which can be a Master, are shown with drawn out lines, parts of other pulses, which can be Slaves, are shown with dashed lines. The beginning of a pulse in the Master is used as reference time 35 (T.sub.ref) for the other pulses. For the n-th Slave, a target turn-on time 34 (T.sub.target(n)) is determined as T.sub.target(n)−(T.Math.n)/N. In operation of each phase circuit 20, the respective actual turn-on time 36 can deviate from the target turn-on time 34, and the controller as described above modifies, for the next period, the turn-on time period t.sub.on.

[0132] If there is no Master phase and the period length T is prescribed for all active phase circuits 20, then all the active phase circuits 20 are operated as Slaves.

[0133] The situation illustrated in the previous figures, and the calculations for determining the period length T and turn-on time period t.sub.on are approximations that do not consider the detailed current trajectory just before and after the turn-on time 31. This is acceptable since on the one hand the charges and currents involved in the switching operation, as explained in the context of FIG. 6, are much smaller than those over an entire period. On the other hand, small errors resulting from the approximation will be corrected by the control of the turn-on time period t.sub.on.

[0134] FIG. 6 shows a trajectory of the inductor current I.sub.L and the voltage V.sub.S across the switch 24 of a phase circuit 20. The voltage V.sub.S across the switch 24 is the same as the voltage of the bridge point 22. At the turn-off time 32, the voltage rises and the current begins to decrease, flowing through the switch 24 and the upper branch switching unit 23.

[0135] According to an embodiment, the switch 24 is turned on after the inductor current I.sub.L has become zero: The inductor current I.sub.L, driven by the difference between the input and output voltages, becomes negative to an extent depending on the time at which the upper branch switching unit 23 is turned off. In the case in which the upper branch switching unit 23 is constituted by a diode, this time depends on the reverse recovery charge of the diode. When the upper branch switching unit 23 blocks the inductor current I.sub.L, it commutates to the freewheeling diode 25 of the switch 24. The freewheeling diode 25 becomes conducting and the voltage V.sub.S across the switch drops to zero. When the voltage is zero, the switch 24 is switched on at turn-on time 31. Ideally at this instant the inductor current I.sub.L has returned to zero again. As a result, the switch 24 is turned on at zero current, reducing EMC disturbances, and zero voltage, reducing switching losses. The figure shows, in addition to the inductor current I.sub.L rising again after the turn-on time 31, trajectories I′ and V′ that the current and voltage would take if the switch 24 were not turned on.

[0136] Thus, the switching on can be triggered by a threshold detection of the voltage V.sub.S across the switch 24. The switching can be triggered when the voltage V.sub.S is zero. Or the switching can be triggered a predetermined time delay T.sub.del after the voltage V.sub.S across the switch 24 falls under a predetermined threshold V.sub.S_tresh that is larger than zero. The predetermined time delay and threshold can be determined according to the parameters of the phase circuit, and stored in the controller 40. Triggering on the basis of the threshold V.sub.S_tresh that is larger than zero moves the point at which the threshold is crossed to an earlier point in time and so allows to compensate for processing time required by the controller 40. Alternatively, the switching on can be triggered by threshold detection of the voltage at the bridge point 22, which usually is identical to the voltage V.sub.S across the switch 24.

[0137] Alternatively, the switching on can be triggered by threshold detection of the inductor current I.sub.L. For this, inductor current I.sub.L itself can be monitored, or the current through the upper branch switching unit 23, since prior to commutation it is the same as the inductor current I.sub.L. The inductor current I.sub.L can be monitored by monitoring the magnetic field of the inductor 21.

[0138] In order for the current and voltage to be zero or near zero at the same time, a diode constituting the upper branch switching unit 23 can be chosen to have a corresponding reverse recovery time. The reverse recovery time determines the time during which the inductor current I.sub.L is negative. The diode is chosen such that for nominal operation conditions the current and voltage are zero at the same time.

[0139] FIG. 7 shows activation of an additional phase circuit and insertion of its current pulses into a sequence of interleaved pulses. Given a total current set point, in a pre-transition period the current pulses are higher and the period length Tpi is longer than in a post-transition period with period length Tsi. A transition period has the same period length Tpi as the pre-transition period and coincides with the pulse period of a phase that is designated as the Master. The other phases already active (Slaves) are operated to be [0140] switched on in the transition period, with turn-on times (relative to the period) as in the pre-transition period, and [0141] their turn-on time period t.sub.on is chosen so that their next turn-on time (at which the current returns to zero) is as required in the post-transition period.

[0142] The new phase circuit 20 being activated is inserted to be last in the post-transition phase, after the last of the Slave phases and before the Master phase. Its next turn-on time 31′ is as required in the post-transition period. Its only free parameter is its turn-on time period t.sub.on: The turn-on time period t.sub.on determines its period length T which in turn, going backwards in time from the next turn-on time 31′, determines the first turn-on time 31 when activating the new phase circuit 20. The turn-on time period t.sub.on is chosen such that the total current of all phase circuits 20 is minimises its deviation from the total current set point.

[0143] FIG. 8 shows deactivation of a phase circuit and removal of its current pulses from a sequence of interleaved pulses. Given a total current set point, in a pre-transition period the current pulses are lower and the period length Tpd is shorter than in a post-transition period with period length Tsd. A transition period has the same period length Tpd as the pre-transition period and coincides with the pulse period of a phase that is designated as the Master. The other phases (Slaves) except the one following the Master are operated to be [0144] switched on in the transition period, with turn-on times (relative to the period) as in the pre-transition period, and [0145] their turn-on time period t.sub.on is chosen so that their next turn-on time (at which the current returns to zero) is as required in the post-transition period.

[0146] The phase circuit 20 following the Master is also, like the other Slaves, switched on with a turn-on time 31 as in the pre-transition period. Here too, its only free parameter for shaping the last pulse is its turn-on time period t.sub.on: The turn-on time period t.sub.on determines the period length T and the point at which its current returns to zero, ending the last pulse. The turn-on time period t.sub.on is chosen such that the total current of all phase circuits 20 is minimises its deviation from the total current set point.

[0147] FIG. 9 shows switching between DCM and BCM and vice versa: the upper diagram shoes four phase circuits A, B, C, D operating in DCM and pairwise. In each pair (A-C and B-D), the two phase circuits generate alternating pulses, with one phase circuit (A or B) generating a current pulse while the other one (C or D) provides no current, and vice versa. The pulses from the two pairs are interleaved. Switching to BCM can be done individually in each pair, by deactivating one of the two phase circuits (C and D) and operating the other one (A and B) to generate both pulses in BCM. The pattern of the total current remains the same.

[0148] Switching from BCM to DCM can be done in an analogous way, i.e., by switching one phase circuit 20 from BCM to DCM and thereby omitting alternating pulses, and activating another phase circuit 20 to supply the omitted pulses.

[0149] More generally (not illustrated), in the same way an integer multiple of phases operating in DCM to generate a sequence of adjacent pulses can be replaced by a single phase operating in BCM, and vice versa.

[0150] Such a switch from BCM to DCM or vice versa can be applied in conditions where the load, or required total current requires it. For example, when a relatively small current is required, the maximum frequency or minimum turn-on time period ton may not allow for BCM, and thus DCM must be used.

[0151] FIG. 10 shows a method for controlling the multiphase DC-DC converter 10 in DCM. Its purpose is to trigger pulses from one or more phase circuits 20 operating in DCM, given a total current set point to be delivered by the converter. A sequence of phase current pulses of essentially the same shape is generated in the following way: [0152] a peak current I.sub.Peak and period length T, defining the shape of the pulses, is determined; [0153] an integrator is initialised with a value corresponding to the product of the peak current I.sub.Peak and the period length T; [0154] a current pulse with the peak current I.sub.Peak and period length T is triggered in one of the phase circuits 20; [0155] the integrator integrates the total current set point value 41, with its integrator output 42 running towards zero; [0156] when the integrator output 42 reaches zero, a next current pulse in another phase circuit 20 is triggered by a trigger pulse 43, the integrator is initialised again, and the procedure continues with the preceding step.

[0157] Limits for ranges in which the peak current I.sub.Peak and period length T can be chosen depend on the hardware and operation considerations. Relevant parameters for the choice can be a maximum switching frequency, minimal pulse length, switching losses.

[0158] The trigger pulses 43 are multiplexed over the active phase circuits 20. The sum of the current pulses will correspond to the total current set point 41. Thanks to the simple structure, the total current set point 41 can be tracked with low latency.

[0159] The example in FIG. 10 shows the integrator being initialised to a negative value and then integrating in the positive direction. It is understood that the same principle can be realised with inverted signs and with differently scaled values of the signals involved.

[0160] In typical applications, the following values can be present for the [0161] period length T: corresponding to a frequency of 10 kHz to 700 kHz, in particular of 20 kHz to 400 kHz. [0162] number of phases N: 6 to 12 phases. [0163] peak current per phase: up to 120 A or up to 200 A or more. [0164] mean current per phase: up to 60 A or up to 100 A or more. [0165] total current: up to 600 A, up to 800 A or more. [0166] output voltage: 200 V to 800 V. [0167] inductance value of the inductor 21: 5 to 20 micro-H or 8 to 15 micro-H,

[0168] While the invention has been described in present embodiments, it is distinctly understood that the invention is not limited thereto, but may be otherwise variously embodied and practised within the scope of the claims.