Encapsulation of digital communications traffic for transmission on an optical link
10135557 ยท 2018-11-20
Assignee
Inventors
Cpc classification
H04L25/49
ELECTRICITY
International classification
H04J3/16
ELECTRICITY
Abstract
A method (10) of encapsulating digital communications traffic for transmission on an optical link, the method comprising: a. receiving an input digital communications signal having an input line code (12); b. performing clock and data recovery on the input digital communications signal to obtain input line coded digital communications traffic and a recovered clock signal (14); c. decoding the input digital communications traffic to obtain information bits and non-information bits (16); d. removing the non-information bits (18); e. adding service channel bits for monitoring or maintenance (20); f. assembling the service channel bits and information bits into frames (22); and g. line coding the assembled frames using an output line code to form an encapsulated digital communications signal for transmission on an optical link (24), wherein steps c. to g. are performed using the timing of the recovered clock signal. A communications network receiver configured to implement the method is also provided.
Claims
1. A method of encapsulating digital communications traffic for transmission on an optical link, the method comprising: a. receiving an input digital communications signal having an input line code; b. performing clock and data recovery on the input digital communications signal to obtain input line coded digital communications traffic and a recovered clock signal; c. decoding the input line coded digital communications traffic to obtain information bits and non-information bits; d. removing the non-information bits; e. adding service channel bits for monitoring or maintenance; f. assembling the service channel bits and information bits into frames; and g. line coding the assembled frames using an output line code to form an encapsulated digital communications signal for transmission on an optical link, wherein steps c. to g. are performed using a timing of the recovered clock signal.
2. The method as claimed in claim 1, wherein the input line code has a first spectral efficiency and the output line code has a second spectral efficiency, higher than the first spectral efficiency.
3. The method as claimed in claim 1, and further comprising obtaining a delay asymmetry of the optical link and step f. comprises buffering the information bits for a time offset substantially equal to the delay asymmetry.
4. The method as claimed in claim 1, wherein step f. comprises applying forward error correction to the information bits and to the service channel bits using a plurality of interleaved forward error correction codecs each configured to apply a preselected forward error correction code, and wherein the method comprises obtaining a maximum acceptable latency to be added by the forward error correction and selecting said plurality of forward error correction codecs such that a latency added by the forward error correction is not greater than the maximum acceptable latency.
5. The method as claimed in claim 1, wherein step f. comprises applying forward error correction to the information bits using a plurality of interleaved forward error correction codecs each configured to apply a first forward error correction code and step f. comprises applying forward error correction to the service channel bits using a plurality of interleaved forward error correction codecs each configured to apply a second forward error correction code, different to the first forward error correction code.
6. The method as claimed in claim 1 and comprising at step a. receiving a plurality of input digital communications signals each having the input line code, performing steps b. to g. for each input digital communication signal to form a respective encapsulated digital communications signal and generating and transmitting a respective optical signal carrying each encapsulated digital communications signal, and the method further comprising: i. receiving each said optical signal; ii. performing clock and data recovery on each respective encapsulated digital communications signal to obtain the respective frames and a respective recovered clock signal; iii. obtaining a clock signal from at least one of the recovered clock signals; iv. disassembling the frames of each said signal and removing the forward error correction coding to obtain the respective service channel bits and information bits, and removing the respective service channel bits of each said signal; v. time division multiplexing the information bits from each of the said signals; vi. adding further service channel bits for monitoring or maintenance; vii. applying forward error correction to the further service channel bits and time division multiplexed information bits and assembling the further service channel bits and time division multiplexed information bits into frames; and viii. line coding the assembled frames using the output line code to form an encapsulated aggregate digital communications signal for transmission on an optical link, wherein steps v. to viii. are performed using the timing of the clock signal obtained in step iii.
7. A communications network transmitter comprising: an input arranged to receive an input digital communications signal having an input line code; clock and data recovery apparatus arranged to perform clock and data recovery on the input digital communications signal to obtain input line coded digital communications traffic and a recovered clock signal, and arranged to generate and transmit a clock signal comprising the recovered clock signal; decoder apparatus arranged to decode the input line coded digital communications traffic to obtain information bits and non-information bits and arranged to remove the non-information bits; a framer arranged to receive the information bits and service channel bits for monitoring or maintenance, and arranged to assemble the service channel bits and information bits into frames; line coding apparatus arranged to line code the assembled frames using an output line code to form an encapsulated digital communications signal for transmission on an optical link; and an optical transmitter arranged to generate and transmit an optical signal carrying the encapsulated digital communications signal, wherein each of the decoder apparatus, the framer and the line coding apparatus are arranged to receive the clock signal and are arranged to operate using a timing of the recovered clock signal.
8. The communications network transmitter as claimed in claim 7, wherein the input line code has a first spectral efficiency and the line coding apparatus is arranged to line code the assembled frames using an output line code having a second spectral efficiency, higher than the first spectral efficiency.
9. The communications network transmitter as claimed in claim 7, wherein the framer is arranged to obtain a delay asymmetry of the optical link and the framer comprises a buffer arranged to buffer the information bits for a time offset substantially equal to the delay asymmetry.
10. The communications network transmitter as claimed in claim 7, wherein the framer comprises forward error correction apparatus comprising a plurality of forward error correction codecs each configured to apply a preselected forward error correction code, and wherein the forward error correction codecs are interleaved and said plurality of interleaved forward error correction codecs is such that a latency added by the forward error correction is not greater than a maximum acceptable latency.
11. The communications network transmitter as claimed in claim 7, wherein the forward error correction apparatus comprises a plurality of interleaved forward error correction codecs each configured to apply a first forward error correction code to the information bits and the forward error correction apparatus comprises a plurality of interleaved forward error correction codecs each configured to apply a second forward error correction code, different to the first forward error correction code, to the service channel bits.
12. The communications network transmitter as claimed in claim 7, further comprising: at least one further input, clock and data recovery apparatus, decoder apparatus, framer and line coding apparatus; a plurality of optical receivers each arranged to receive a respective optical signal from a respective one of the transmitters carrying a respective encapsulated digital communications signal; a plurality of further clock and data recovery apparatus each arranged to perform clock and data recovery on the respective encapsulated digital communications signal to obtain the respective frames and a respective recovered clock signal; a clock selector arranged to obtain a clock signal from at least one of the recovered clock signals and to generate and transmit a further clock signal comprising said obtained clock signal; a plurality of deframers each arranged to disassemble the frames of the respective decoded digital communications signal and remove the forward error correction coding to obtain the respective service channel bits and information bits, and arrange to remove the respective service channel bits of each said signal; a time division multiplexer arranged to time division multiplex the information bits from each of the said signals; a further framer arranged to add further service channel bits for monitoring or maintenance, apply forward error correction and assemble the further service channel bits and time division multiplexed information bits into frames; further line coding apparatus arranged to line code the assembled frames using the output line code to form an encapsulated aggregate digital communications signal for transmission on an optical link, and a further optical transmitter arranged to generate and transmit a further optical signal carrying the encapsulated aggregate digital communications signal, wherein each of the deframers, the multiplexer, the further framer and the further line coding apparatus are arranged to receive the further clock signal and are arranged to operate using the timing of said obtained clock signal.
13. The communications network transmitter as claimed in claim 12, wherein the clock selector is arranged to obtain the clock signal by one of arbitrarily selecting one of the recovered clock signals, selecting a most accurate one of the recovered clock signals and averaging the recovered clock signals.
14. A communications network base station node comprising at least one of the communications network transmitter as claimed in claim 7 and a communications network receiver.
15. A communications network base station comprising: at least two communications network base station nodes as claimed in claim 14; and at least one optical link connecting said at least two communications network base station nodes.
16. A method of converting encapsulated digital communications traffic for transmission on a digital communications link, the method comprising: A. receiving an encapsulated digital communications signal having an input line code from an optical link; B. performing clock and data recovery on the encapsulated digital communications signal to obtain digital communications traffic frames and a recovered clock signal; C. disassembling the digital communications traffic frames to obtain information bits and service channel bits for monitoring or maintenance; D. removing the service channel bits; and E. line coding the information bits using an output line code to form an output digital communications signal for transmission on digital communications link, wherein steps C. to E. are performed using a timing of the recovered clock signal.
17. The method as claimed in claim 16, wherein the input line code has a first spectral efficiency and the output line code has a second spectral efficiency, lower than the first spectral efficiency.
18. The method as claimed in claim 16, and further comprising obtaining a delay asymmetry of the optical link and step C. comprises buffering the information bits for a time offset substantially equal to the delay asymmetry.
19. The method as claimed in claim 16, wherein step C. comprises performing forward error correction on the information bits and the service channel bits using a plurality of interleaved forward error correction codecs each configured to perform a preselected forward error correction code, and wherein the method comprises obtaining a maximum acceptable latency to be added by the forward error correction and using a plurality of forward error correction codecs such that a latency added by the forward error correction is not greater than the maximum acceptable latency.
20. The method as claimed in claim 16, wherein step C. comprises performing forward error correction on the information bits using a plurality of interleaved forward error correction codecs each configured to perform a first forward error correction code and performing forward error correction on the service channel bits using a plurality of interleaved forward error correction codecs each configured to perform a second forward error correction code, different to the first forward error correction code.
21. A communications network receiver comprising: an input arranged to receive an optical signal carrying an encapsulated digital communications signal having an input line code; clock and data recovery apparatus arranged to perform clock and data recovery on the encapsulated digital communications signal to obtain digital communications traffic frames and a recovered clock signal, and arranged to generate and transmit a clock signal comprising the recovered clock signal; a deframer arranged to disassemble the digital communications traffic frames to obtain information bits and service channel bits for monitoring or maintenance, and arranged to remove the service channel bits; line coding apparatus arranged to fine code the information bits using an output line code to form an output digital communications signal for transmission on a digital communications link; and a digital transmitter arranged to generate and transmit the output digital communications signal, wherein the deframer, the line coding apparatus and the digital transmitter are each arranged to receive the clock signal and are each arranged to operate using a timing of the recovered clock signal.
22. The communications network receiver as claimed in claim 21, wherein the input line code has a first spectral efficiency and the line coding apparatus is arranged to line code the information bits using an output line code having a second spectral efficiency, lower than the first spectral efficiency.
23. The communications network receiver as claimed in claim 21, further comprising: a time division demultiplexer arranged to receive the information bits from the deframer and arranged to time division demultiplex the information bits into a plurality of streams of information bits; at least one further said line coding apparatus, each said line coding apparatus arranged to receive a respective one of the streams of information bits and arranged to line code the information bits using an output line code to form a respective output digital communications signal for transmission on a respective digital communications link; and at least one further said digital transmitter, each digital transmitter arranged to generate and transmit the respective output digital communications signal, wherein the time division demultiplexer, each line coding apparatus and each digital transmitter is arranged to receive the clock signal and is arranged to operate using the timing of the recovered clock signal.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
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DETAILED DESCRIPTION
(28) Referring to
(29) The method 10 comprises the following steps:
(30) a. receiving an input digital communications signal having an input line code 12;
(31) b. performing clock and data recovery on the input digital communications signal to obtain input line coded digital communications traffic and a recovered clock signal 14;
(32) c. decoding the input digital communications traffic to obtain information bits and non-information bits 16;
(33) d. removing the non-information bits 18;
(34) e. adding service channel bits for monitoring or maintenance 20;
(35) f. assembling the service channel bits and information bits into frames 22; and
(36) g. line coding the assembled frames using an output line code to form an encapsulated digital communications signal for transmission on an optical link 24.
(37) Steps c. to g. are performed using the timing of the recovered clock signal.
(38)
(39) In this embodiment, the input line code has a first spectral efficiency 32 and the output line code has a second spectral efficiency 34. The second spectral efficiency is higher than the first spectral efficiency.
(40) In a third embodiment of the invention, described with reference to
(41) In a fourth embodiment of the invention, described with reference to
(42) Referring to
(43) In this embodiment, the method further comprises obtaining an upstream/downstream, US/DS, delay asymmetry of the optical link 42. Step f. comprises buffering the information bits for a time offset substantially equal to the delay asymmetry 44.
(44) The delay asymmetry may be obtained by estimation depending on at least one parameter of the optical link or it may be obtained by measurement. The method of measuring delay asymmetry disclosed in WO2013/139367 may be used to obtain the delay asymmetry.
(45) It is not necessary to buffer the service channel bits but it can be done if desired.
(46)
(47) In this embodiment, step f. comprises applying forward error correction, FEC, to the information bits and to the service channel bits using a plurality of interleaved FEC codecs. Each FEC codec is configured to apply a preselected FEC code. The method 50 comprises obtaining a maximum acceptable latency to be added by the forward error correction 52. The number of FEC codecs used is then selected so that a latency added by the forward error correction process is not greater than the maximum acceptable latency 54.
(48) By way of example, each FEC code may be a Reed-Solomon code, such as a Reed-Solomon (255, 239) code.
(49)
(50) In this embodiment, forward error correction is applied in step f. to the information bits using a plurality of interleaved FEC codecs each configured to apply a first FEC code. Forward error correction is also applied to the service channel bits in step f. but it is done using a plurality of interleaved FEC codecs each configured to apply a second FEC code, different to the first FEC code 112.
(51) By way of example, the FEC code may be a Reed-Solomon code, such as a Reed-Solomon (255, 239) code. Optionally, the number of interleaved FEC codecs used may be selected, as in the previous embodiment, to control the latency added by the FEC processing. For example, four interleaved FEC codecs may be used for each of the information bits and the service channel bits, to achieve a lower latency that is possible using the 16-byte interleaved codecs using a Reed-Solomon (255, 239) code specified for the OTN in Annex A of ITU-T Recommendation G.709.
(52) Referring to
(53) The method 60 comprises:
(54) a. receiving a plurality of input digital communications signal having an input line code 62;
(55) b. for each input digital communications signal, performing clock and data recovery to obtain respective input line coded digital communications traffic and a respective recovered clock signal 64;
(56) c. for each input digital communications signal, decoding the input digital communications traffic to obtain information bits and non-information bits 66;
(57) d. for each input digital communications signal, removing the non-information bits 68;
(58) e. for each input digital communications signal, adding service channel bits for monitoring or maintenance 70;
(59) f. for each input digital communications signal, assembling the service channel bits and information bits into frames 72;
(60) g. for each input digital communications signal, line coding the assembled frames using an output line code to form a respective encapsulated digital communications signal for transmission on an optical link 74; and
(61) h. generate and transmit a respective optical signal carrying each encapsulated digital communications signal 76.
(62) For each input digital communications signal, steps c. to g. are performed using the timing of the respective recovered clock signal.
(63) The method 60 further comprises:
(64) i. receiving each optical signal carrying a respective encapsulated digital communications signal 78;
(65) ii. performing clock and data recovery on each respective encapsulated digital communications signal to obtain the respective frames and a respective recovered clock signal 80;
(66) iii. obtaining a clock signal from at least one of the recovered clock signals 82;
(67) iv. disassembling the frames of each said signal and removing the forward error correction coding to obtain the respective service channel bits and information bits 84, and removing the respective service channel bits of each said signal 86;
(68) v. time division multiplexing, TDM, the information bits from each of the said signals 88;
(69) vi. adding further service channel bits for monitoring or maintenance 90;
(70) vii. applying forward error correction to the further service channel bits and time division multiplexed, TDM, information bits and assembling the further service channel bits and time division multiplexed information bits into frames 92; and
(71) viii. line coding the assembled frames using the output line code to form an encapsulated aggregate digital communications signal for transmission on an optical link 94.
(72) Steps v. to viii. are performed using the timing of the clock signal obtained in step iii.
(73) Referring to
(74) In this embodiment, in step iii. the clock signal is obtained by arbitrarily selecting one of the recovered clock signals 102. This assumes that all of the input digital communications signals are frequency synchronous, and all the recovered clock signals are therefore equivalent. If they are not, the clock signal may be obtained in step iii. by selecting a most accurate one of the recovered clock signals or by averaging the recovered clock signals.
(75) A tenth embodiment of the invention provides a communications network transmitter 200 as shown in
(76) The input 202 is arranged to receive an input digital communications signal having an input line code.
(77) The clock and data recovery apparatus 204 is arranged to perform clock and data recovery on the input digital communications signal to obtain input line coded digital communications traffic and a recovered clock signal. The clock and data recovery apparatus 204 is also arranged to generate and transmit a clock signal 214, comprising the recovered clock signal, to the decoder, the framer, the line coding apparatus and the optical transmitter. Each of the decoder apparatus, the framer and the line coding apparatus are arranged to receive the clock signal and are arranged to operate using the timing of the recovered clock signal.
(78) The decoder apparatus 206 is arranged to decode the input digital communications traffic to obtain information bits and non-information bits. The decoder apparatus 206 is also arranged to remove the non-information bits.
(79) The framer 208 is arranged to receive the information bits and is arranged to receive service channel bits for monitoring or maintenance. The framer is arranged to assemble the service channel bits and information bits into frames.
(80) The line coding apparatus 210 is arranged to line code the assembled frames using an output line code to form an encapsulated digital communications signal for transmission on an optical link.
(81) The optical transmitter 212 is arranged to generate and transmit an optical signal carrying the encapsulated digital communications signal.
(82) An eleventh embodiment of the invention provides a communications network transmitter 220 as shown in
(83) In this embodiment, the input digital communications signal 222 is a CPRI signal having 8B10B line coding.
(84) The transmitter 220 additionally comprises a receiver 224, a serial to parallel converter 228, clock signal generation and distribution apparatus 238, and a parallel to serial converter 236.
(85) The receiver 224 is arranged to receive the CPRI signal 222 and deliver it to the clock and data recovery apparatus 204. The recovered clock signal 226 is sent to the clock signal generation and distribution apparatus, which is arranged to generate and transmit the clock signal 214 to the serial to parallel converter 228, decoder apparatus 230, framer 208, line coding apparatus 234, parallel to serial converter 236 and the transmitter 212.
(86) The serial to parallel converter 228 converts the CPRI signal 222 into a plurality of parallel signals for parallel processing by the decoder apparatus 230, the framer 208 and the line coding apparatus 234. The parallel to serial converter 236 receives a plurality of encapsulated digital communications signals and converts them into a single encapsulated digital communications signal for transmission by the transmitter 212. It will be appreciated that the serial to parallel converter 228 and the parallel to serial converter 236 are not essential but their use may increase the overall processing speed achievable by the decoder apparatus, framer and line coding apparatus.
(87) The decoder apparatus 230 is arranged to decode the parallel 8B10B coded CPRI signals to obtain information bits and non-information bits. The decoder apparatus 230 is also arranged to remove the non-information bits, with the exception of control characters.
(88) The framer 208 is arranged to receive the information bits and an operation and maintenance, O&M, channel carrying service channel bits. The framer comprises FEC apparatus comprising a plurality of interleaved FEC codecs each configured to apply a preselected FEC code, in this example a Reed-Solomon (255, 239) code. The FEC apparatus is configured to apply FEC to the information bits and the newly added service channel bits. The number of interleaved FEC codecs, used to correct bursts of consecutive errors, may be adjusted according to latency requirements. Four interleaved FEC codecs are used here, which reduces the resulting FEC code-word length and latency as compared to FEC apparatus configured according to Annex A of ITU-T Recommendation G.709, which uses 16 interleaved FEC codecs.
(89) The framer is arranged to assemble the parallel streams of information bits and the service channel bits into frames.
(90) The line coding apparatus 234 is arranged to line code the assembled frames using a 64B66B line code, which is more spectrally efficient than the 8B10B line code, to form parallel encapsulated digital communications signals, which are then combined in the parallel to serial converter 236.
(91)
(92) The framer 240 of this embodiment comprises a buffer 242 which is arranged to receive a delay asymmetry 244 of the optical link. The buffer is arranged to buffer the information bits 248 for a time offset substantially equal to the delay asymmetry.
(93) The framer 240 also comprises frame delimiting apparatus 246 which is arranged to receive the information bits from the buffer 242 and service channel bits 241, and assemble the information bits and service channel bits into frames.
(94)
(95) The framer 250 comprises interleavers 254a, 254b, FEC apparatus 256a, 256b, a buffer 258 and frame delimiting apparatus 262.
(96) A first one of the interleavers 254a has two inputs, one arranged to receive information bits (data) 252 and the other arranged to receive control bits, and is arranged to interleave the information bits and control bits. The first FEC apparatus 256a is arranged to apply FEC to the interleaved information and control bits.
(97) The second interleaver 256b is arranged to receive the OAM channel 232 and is arranged to time interleave the service channel bits. The second FEC apparatus 256b is arranged to apply FEC to the interleaved service channel bits.
(98) The buffer 258 which is arranged to receive a time offset 260 substantially equal to the delay asymmetry of the optical link. The buffer is arranged to buffer the FEC wrapped information and control bits for the time offset. The buffer may also be used to buffer the FEC wrapped service channel bits.
(99) The frame delimiting apparatus 262 which is arranged to receive the buffered FEC wrapped information bits and control bits and the FEC wrapped service channel bits 241, and is arranged assemble the FEC wrapped information bits, control bits and service channel bits into frames.
(100) A fourteenth embodiment of the invention provides a communications network transmitter 270 comprising a plurality of inputs 202, 222 clock and data recovery apparatus 204, decoder apparatus 206, 230, framers 208, 240, 250, line coding apparatus 210, 234, and transmitter 212 arranged as a plurality of communications network transmitters 200, 220 as shown in any of
(101) As shown in
(102) Each optical receiver 272 is arranged to receive a respective optical signal from a respective one of the transmitters 212, carrying a respective encapsulated digital communications signal.
(103) Each further clock and data recovery apparatus 274 is arranged to perform clock and data recovery on the respective encapsulated digital communications signal to obtain the respective frames and a respective recovered clock signal.
(104) The clock selector 276 is arranged to obtain a clock signal from at least one of the recovered clock signals. In this example the clock selector is arranged to obtain the clock signal by one of arbitrarily selecting one of the recovered clock signals. This is based on the assumption that all of the input digital communications signals are frequency synchronous. Alternatively, the clock selector may be arranged to select a most accurate one of the recovered clock signals or to average the recovered clock signals.
(105) The clock selector 276 is also arranged to generate and transmit a further clock signal 278 comprising the clock signal so obtained. The serial to parallel converters 272, the deframers 280, the multiplexer 282, the further framer 284, the further line coding apparatus 286 and the parallel to serial converter 288 are each arranged to receive the further clock signal and are arranged to operate using the timing of the clock signal obtained by the clock selector.
(106) The deframers 280 are each arranged to disassemble the frames of the respective decoded digital communications signal and to remove the FEC coding to obtain the respective service channel bits and information bits. The deframers are also arranged to remove the respective service channel bits of each said signal.
(107) The time division multiplexer 282 is arranged to time division multiplex the information bits from each of the said signals. The multiplexing is time division based on the assumption that all of the input digital communications signals are frequency synchronous, and no phase synchronisation is required.
(108) The further framer 284 is arranged to add further service channel bits 292 for monitoring or maintenance. The further framer is also arranged to apply forward error correction and to assemble the further service channel bits and time division multiplexed information bits into frames.
(109) The further line coding apparatus 286 is arranged to line code the assembled frames using the output line code to form an encapsulated aggregate digital communications signal for transmission on an optical link.
(110) The further optical transmitter 290 is arranged to generate and transmit a further optical signal carrying the encapsulated aggregate digital communications signal.
(111) The communications network transmitter 270 enables multiplexing of FEC protected tributary signals into one higher bit rate aggregate signal.
(112) Referring to
(113) The method 300 comprises
(114) A. receiving an encapsulated digital communications signal having an input line code from an optical link 302;
(115) B. performing clock and data recovery on the encapsulated digital communications signal to obtain digital communications traffic frames and a recovered clock signal 304;
(116) C. disassembling the digital communications traffic frames to obtain information bits and service channel bits for monitoring or maintenance 306;
(117) D. removing the service channel bits 308; and
(118) E. line coding the information bits using an output line code to form an output digital communications signal for transmission on digital communications link 310.
(119) Steps C. to E. are performed using the timing of the recovered clock signal.
(120) A sixteenth embodiment of the invention provides a method 320 of converting encapsulated digital communications traffic for transmission on a digital communications link. The method 320 of this embodiment is similar to the method 310 shown in
(121) In this embodiment, the input line code has a first spectral efficiency 322 and the output line code has a second spectral efficiency, lower than the first spectral efficiency (324).
(122) A seventeenth embodiment of the invention provides a method 330 of converting encapsulated digital communications traffic for transmission on a digital communications link, having the steps shown in
(123) In this embodiment, the method 330 further comprises an initial step of obtaining a delay asymmetry of the optical link 332. Step C. comprises buffering the information bits for a time offset substantially equal to the delay asymmetry 334.
(124)
(125) In this embodiment, the method comprises obtaining a maximum acceptable latency to be added by forward error correction 342.
(126) Step C. comprises performing forward error correction on the information bits and the service channel bits using a plurality of interleaved FEC codecs each configured to perform a preselected FEC code 344. The forward error correction is performed using a plurality of FEC codecs such that a latency added by performing the forward error correction is not greater than the maximum acceptable latency.
(127)
(128) In this embodiment, the method comprises performing forward error correction on the information bits using a plurality of interleaved FEC codecs each configured to perform a first FEC code 352. The method further comprises performing forward error correction on the service channel bits using a plurality of interleaved FEC codecs each configured to perform a second FEC code, different to the first FEC code.
(129) A twentieth embodiment of the invention provides a communications network receiver 400 as shown in
(130) The input 402 is arranged to receive an optical signal carrying an encapsulated digital communications signal having an input line code.
(131) The clock and data recovery apparatus 404 is arranged to perform clock and data recovery on the encapsulated digital communications signal to obtain digital communications traffic frames and a recovered clock signal. The clock and data recovery apparatus 404 is also arranged to generate and transmit a clock signal 406 comprising the recovered clock signal. The deframer, the line coding apparatus and the digital transmitter are each arranged to receive the clock signal and are each arranged to operate using the timing of the recovered clock signal.
(132) The deframer 408 is arranged to disassemble the digital communications traffic frames to obtain information bits and service channel bits for monitoring or maintenance. The deframer 408 is also arranged to remove the service channel bits.
(133) The line coding apparatus 410 is arranged to line code the information bits using an output line code to form an output digital communications signal for transmission on a digital communications link.
(134) The digital transmitter 412 is arranged to generate and transmit the output digital communications signal.
(135) A twenty-first embodiment of the invention provides a communications network receiver 420 as shown in
(136) In this embodiment, the input line code has a first spectral efficiency. The line coding apparatus 422 is arranged to line code the information bits using an output line code having a second spectral efficiency, which is lower than the first spectral efficiency.
(137)
(138) In this embodiment, the communications network receiver 430 additionally comprises an optical receiver, WDM RX, 434, clock signal generation and distribution apparatus 436, a serial to parallel converter 438 and a parallel to serial converter 444.
(139) The receiver 224 is arranged to receive an optical signal carrying an encapsulated digital communications signal having an input line code and output the encapsulated digital communications signal it to the clock and data recovery apparatus 404. In this example, the input line code is a 64B66B line code.
(140) The recovered clock signal 435 is sent to the clock signal generation and distribution apparatus 436, which is arranged to generate and transmit the clock signal 406 to the serial to parallel converter 438, deframer 408, line coding apparatus 442, parallel to serial converter 444 and the digital transmitter 412.
(141) The serial to parallel converter 438 converts the encapsulated digital communications signal into a plurality of parallel signals for parallel processing by the deframer 408 and the line coding apparatus 442. The parallel to serial converter 444 receives a plurality of line coded digital communication signals and converts them into a single digital communications signal for transmission by the transmitter 412. It will be appreciated that the serial to parallel converter 438 and the parallel to serial converter 444 are not essential but their use may increase the overall processing speed achievable by the deframer and the line coding apparatus.
(142) The line coding apparatus 442 is arranged to line code the information bits using an 8B10B line code, which is less spectrally efficient than the received 64B66B line code, to form parallel line coded digital communications signals, which are then combined in the parallel to serial converter 444.
(143)
(144) The deframer 440 comprises frame alignment and disassembling apparatus 442, deinterleavers 444a, 444b, and forward error correction apparatus comprising first and second forward error correction decoders 446a, 446b.
(145) The frame alignment and disassembling apparatus 442 is arranged to receive the encapsulated digital communications signal and is arranged to recover frame alignment and disassemble the frames to obtain interleaved FEC wrapped information bits, control bits and service channel bits. The first of the deinterleavers 444a is arranged to receive the interleaved FEC wrapped information bits and control bits and is arranged to deinterleave the FEC wrapped information bits and control bits. The second deinterleaver 444b receives the interleaved FEC wrapped service channel bits and is arranged to deinterleave the FEC wrapped service channel bits.
(146) The first of the forward error correction decoders 446a is arranged to receive the FEC wrapped information bits and control bits and is arranged to perform forward error correction on them using a preselected FEC code. The second forward error correction decoder 446b is arranged to receive the FEC wrapped service channel bits and is arranged to perform forward error correction on them using a preselected FEC code. In this example each FEC codes is a Reed-Solomon (255, 239) code.
(147) Referring to
(148) The communications network receiver 450 additionally comprises a time division demultiplexer, TDM DEMUX, 452, four framers 454, three further line coding apparatus 442, three further parallel to serial converters 444 and three further digital transmitters 412.
(149) The time division demultiplexer 452 is arranged to receive the information bits from the deframer 408 and is arranged to time division demultiplex the information bits into a plurality of streams of information bits.
(150) The framers 454 are each arranged to perform forward error correction on the respective streams of information bits.
(151) Each of the line coding apparatus 442 is arranged to receive a respective one of the streams of information bits. Each of the line coding apparatus is arranged to line code the respective information bits using an output line code.
(152) Each digital transmitter 412 is arranged to receive the respective line coded information bits and is arranged to generate and transmit a respective output digital communications signal.
(153) The time division demultiplexer, each framer, each line coding apparatus and each digital transmitter is arranged to receive the clock signal and is arranged to operate using the timing of the recovered clock signal.
(154) Referring to
(155) Referring to
(156) Referring to
(157) Referring to
(158) A twenty-ninth embodiment of the invention provides a data carrier having computer readable instructions embodied therein. The computer readable instructions are for providing access to resources available on a processor. The computer readable instructions comprise instructions to cause the processor to perform any of the steps of the method 10, 30, 40, 50, 60, 100, 110 of encapsulating digital communications traffic for transmission on an optical link as described above with reference to
(159) The data carrier may be a non-transitory data carrier.
(160) A thirtieth embodiment of the invention provides a data carrier having computer readable instructions embodied therein. The said computer readable instructions are for providing access to resources available on a processor. The computer readable instructions comprise instructions to cause the processor to perform any of the above steps of the method 300, 320, 33, 340, 350 of converting encapsulated digital communications traffic for transmission on a digital communications link as described above with reference to
(161) The data carrier may be a non-transitory data carrier.