Method for processing a measured-value signal representing a value determined in analog form for the output current of a converter and device for carrying out the method

Abstract

A method for processing a measured-value signal representing a value, determined in analog form, for the output current of a converter, and device for carrying out the method, the measured-value signals acquired by a sensor, especially including a shunt resistor, being supplied to a respective processing channel that has at least one delta-sigma modulator.

Claims

1. A device for processing a measured-value signal representing a value, determined in analog form, for an output current of a converter, comprising: a sensor; at least one delta-sigma modulator; and first and second digital filters; wherein: the sensor (a) acquires the measured-value signal and (b) supplies the measured-value signal to the at least one delta-sigma modulator; the at least one delta-sigma modulator supplies a bit stream to the first digital filter; the first digital filter (a) converts the bit stream into a stream of digital intermediate words and (b) supplies an output signal to the second digital filter, wherein the first digital filter includes a number of serially disposed accumulators, the bit stream and the stream of digital intermediate words being clocked with a clock frequency f.sub.S and a clock period T.sub.S1/f.sub.S; the second digital filter determines a difference between a first and a second result data-word stream such that the difference is output as output data-word stream; the first and second result data-word streams are determined from the intermediate data-word stream over a first and a second time interval, the first and second time intervals having time duration T1; the first result data-word stream is determined from the intermediate data-word stream as a time-discrete differential of the order (n 1), with time duration T.sub.D; the second result data-word stream is determined from the intermediate data-word stream as a time-discrete differential of the order (n1), with time duration T.sub.D; and T1 is equal to or greater than the double of T.sub.D.

2. The device according to claim 1, wherein the bit stream includes a one-bit data stream.

3. The device according to claim 1, wherein the stream of digital intermediate words is a multi-bit data stream.

4. The device according to claim 1, wherein the accumulators include integrators.

5. The device according to claim 1, wherein the first digital filter includes 3 serially disposed accumulators.

6. The device according to claim 1, wherein the output data stream is transmitted to the first and/or second digital filter according to a Manchester code process, the first and/or second digital filter being spatially separate from the delta-sigma modulator.

7. The device according to claim 1, wherein at least one of (a) a respective measured-value signal is supplied to a delta-sigma modulator, which makes a bit stream available on the output side, and (b) at least one of (i) digital data and (ii) a one-bit output data stream from the delta-sigma modulator, is transmitted as a simple one-bit binary signal, without additional transmission of a clock signal and/or in the Manchester code.

8. The device according to claim 1, wherein the output data stream from the delta-sigma modulator is supplied to at least one of (a) the first and/or second digital filter and (b) the first and/or second digital filter spatially separate from the delta-sigma modulator.

9. The device according to claim 1, wherein the clock period duration T.sub.D is an integral multiple of T.sub.S.

10. The device according to claim 1, wherein the first digital filter includes three integrators or accumulators disposed directly one after another.

11. The device according to claim 1, wherein a moving average of the bit stream corresponds to the measured-value signal.

12. The device according to claim 1, wherein the clock signal used in the delta-sigma modulator is separated on the filter side and is applied to the clock input of the first digital filter.

13. The device according to claim 1, the first digital filter having n number of serially disposed accumulators, where n is an integer and is equal to or greater than 2.

14. The device according to claim 1, wherein the sensor and the delta-sigma modulator are disposed in at least one of (a) power electronics and (b) a shared housing with power electronics, and the at least one digital filter is disposed in at least one of (a) signal electronics and (b) a shared housing with signal electronics.

15. The device according to claim 14, wherein the at least one digital filter is spatially separate from the delta-sigma modulator.

16. The device according to claim 14, wherein the delta-sigma modulator and the filter are disposed so as to be galvanically isolated, the signals being transmitted at least one of (a) inductively and (b) with the aid of optical fibers.

17. The device according to claim 1, wherein the sensor and the delta-sigma modulator are disposed in at least one of (a) power electronics and (b) a shared housing with power electronics, and the first and/or second digital filter is disposed in at least one of (a) signal electronics and (b) a shared housing together with signal electronics.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 illustrates the method according to an example embodiment of the present invention.

(2) FIG. 2 shows a producible configuration according to an example embodiment of the present invention.

(3) FIG. 3 illustrates the method according to an example embodiment of the present invention.

DETAILED DESCRIPTION

(4) A three-phase motor M is energized from a converter, the converter making a three-phase voltage available with the aid of its power electronics 1, so that the speed of the motor is controllable.

(5) Power electronics 1 are implemented with an output stage that includes three half-bridges of semiconductor switches, the switches receiving pulse-width-modulated control signals from signal electronics 3, or corresponding information being furnished by signal electronics 3 to a driver stage, included in power electronics 1, which then generates corresponding pulse-width-modulated signals and supplies them to the switches.

(6) The signal electronics are situated in an area that is set off spatially from the area of the power electronics. For example, the power electronics are disposed in a first housing and the signal electronics are disposed in a second housing, the first and second housings being situated in different spatial areas.

(7) Devices for sensing the motor current are also situated in the area of the power electronics, preferably in the housing of the power electronics, or directly joined to the housing of the power electronics. Given the three-phase realization of the three-phase current, the sensing of two phase currents of the three-phase motor is sufficient. Preferably, the devices include at least one shunt resistor. It is situated either in one of the half-bridges of the output stage of the converter, or in the lead from which the three half-bridges are supplied. In the last-named case, the current assigned to a respective half-bridge is able to be sensed as a function of the point in time, since in the case of converter-energized three-phase motors, in each instance, only one of the switches of a respective half-bridge is enabled as a function of time.

(8) Device 2 for sensing the motor current also includes at least one delta-sigma modulator. Thus, each measured value acquired in respect to a motor phase is able to be supplied to a respective processing channel, including a delta-sigma modulator. Since the delta-sigma modulator supplies a bit stream, thus, a one-bit data stream, on the output side, the acquired value, converted from an analog to a digital representation, is able to be forwarded easily and without great expenditure to spatially remote signal electronics 3. Signal electronics 3 use the detected currents to determine the voltage values to be adjusted on the output side of the converter and the associated pulse-width-modulation ratio, respectively.

(9) The transmission of the digital one-bit data stream to the signal electronics is made possible especially easily in galvanically isolated manner, thus, for example, via optical fiber or transformer. In so doing, the transmission is carried out using a Manchester-code data-transmission process. In this connection, the actual output signal of the delta-sigma modulator is combined with a higher-frequency clock signal, e.g., XOR, thus, exclusive-OR combined, and this combined signal is transmitted. For example, the higher-frequency clock signal has half the period duration as the sampling clock signal of the delta-sigma modulator. The decoding on the receive side may be accomplished easily and without special expenditure. In this manner, the signal is transmittable without difficulty, especially in noise-free fashion, over large spatial distances. In so doing, a line-conducted, differential, serial data channel may be used, which includes an electrical isolation. Alternatively, a radio transmission or an optical-fiber transmission may be used, as well. A non-differential data transmission is also sufficient for shorter distances.

(10) Thus, one especially important advantage is that the respective one-bit data stream is also transmittable without interference over long distances, since it is carried out digitally.

(11) In signal electronics 3, the transmitted signal, received and decoded again into the one-bit data stream, is supplied to a digital filter, the filter being included in the signal electronics. The filter has three integrators connected in series, the output signal of this series connection being subjected to a special data-processing method.

(12) Preferably, the filter is likewise implemented digitally and needs multibit data streams, that preferably are realized with the aid of parallel multibit data buses, between the individual components of the filter. Transmitting such multibit data streams over large distances would require too much effort and is not necessary in the case of the present invention. In addition, the components of the filter are realizable with the aid of a computer, such as a microcontroller or the like. For example, this computer is also usable for the computation steps of the control process active in the converter, thus, for instance, for the computation steps of a field-oriented, closed-loop control of the electric motor. Thus, it is possible to dispense with an additional computer otherwise necessary

(13) In this manner, the filter, sophisticated from the standpoint of technical computations, is disposed in the signal electronics, in particular, components of the signal electronics thus also being effective as components of the filter.

(14) The one-bit data stream of each processing channel has the information about the measured value of the supplied signal as time average.

(15) FIG. 1 shows a portion of a filter according to an example embodiment of the present invention, downstream of the delta-sigma modulator, for one respective processing channel.

(16) As also in the case of DE 10 2005 005 024, three integrators, which are also denotable as accumulators or integrating elements and are not shown in FIG. 1, and which are also included by the filter and are operated with a clock frequency f.sub.S, thus clock period T.sub.S=1/f.sub.S, are disposed serially one after the other, so that an intermediate data-word stream is output at this serial configuration. In contrast to DE 10 2005 005 024, in which the intermediate data-word stream is supplied to the three following, again serially disposed differentiators, which, however, are operated with the much slower clock frequency f.sub.D, thus, clock period T.sub.D=1/f.sub.D, a special data-processing method is carried out.

(17) This special data processing is illustrated in FIG. 1.

(18) In this context, it is important that the intermediate data-word stream be updated in the clock pulse of clock period T.sub.S, thus, in the sampling clock of the delta-sigma modulator.

(19) From this intermediate data stream, a time-discrete differential of the second order is determined by adding a first intermediate data word at a first instant to an intermediate data word at a distance 2T.sub.D away in time, and from the sum thus formed, subtracting the double value of the intermediate data word lying centrally in time between these two intermediate data words. Thus, a first result value is formed.

(20) In order to form a second result value, the same operation is performed at a time interval lying at the distance in time T.sub.1 from the first intermediate data word indicated. Thus, added to an intermediate data word at that place is again an intermediate data word at a distance 2T.sub.D away in time, and from the sum thus formed, the double value of the intermediate data word lying centrally between these two intermediate data words is subtracted, the centrally lying intermediate data word having the distance in time T.sub.1 to the centrally lying intermediate data word utilized for calculating the first result value. Thus, a second result value is formed.

(21) Difference D between the two result values is made available on the output side and represents the filtered measured value in digital form, a high accuracy being achievable in the process.

(22) In contrast to DE 10 2005 005 024, neither any differentiators nor an output-side decimation filter OSR2 are necessary, since according to the method described herein, the result on the output side is determined directly by the difference between the first and second result.

(23) A special advantage hereof is also that T1 is an arbitrary integral multiple of T.sub.S, no further specification having to be made. Naturally, in this context, T1 is advantageously greater than the double of T.sub.D, thus, T1>T.sub.D. Since, for example, 1/T.sub.S amounts to several MHz, thus, for instance, more than 10 MHz, T1 is alterable in fine steps.

(24) Consequently, T1 is alterable with high time resolution during the operating time, and synchronizations to different clocked signal streams are therefore practicable without special expenditure. If, for example, the measured value of the signals of a resolver processed according to example embodiments of the present invention is supplied to control electronics of a converter, it is therefore possible in easy manner to carry out a synchronization to a clock pulse predefined by a field bus connected to the converter. To that end, only the value of T1 must thus be changed, which is practicable with the high time resolution of T.sub.S.

(25) In further exemplary embodiments of the present invention, instead of the second time-discrete differential, a time-discrete differential of the first, second, third or higher order is used, if the number of integrators, thus, accumulators, is changed correspondingly. Thus, if n integrators are provided, in order to form the first and second result value, in each case an n-tuple of intermediate data words f.sub.k set apart form each other at regular intervals with distance in time T.sub.D is used, where k runs from 0 to n1. In this context, the differential is formed by forming the sum

(26) $\underset{k=0}{\overset{n-1}{.Math.}}{\left(-1\right)}^k\left(\begin{array}{c}n-1\\ k\end{array}\right)f_k$

(27) where summation index k runs from 0 to n1.

(28) FIG. 3 shows, by way of example, an example embodiment in which the method is used to sense the output current i of a converter, which is operated with pulse-width modulation. In this case, for example, measuring duration T1 is intended to extend over one half PWM period duration. Consequently, T1 is able to be set very exactly with the high time resolution of T.sub.S according to the measuring duration desired.

(29) In FIG. 3, the instants which are used for determining the differentials of second order are in each case represented by a set of three small bars. Each set of three has a time length of 2T.sub.D. However, since T.sub.D is very much greater than T.sub.S, a representation of distance in time T.sub.S is no longer possible in FIG. 3.

(30) In addition, one measurement is to be performed in each PWM period. Consequently, T.sub.U is specified according to PWM period duration T.sub.PWM, independently of T1. This may likewise be done with the high time resolution of T.sub.S. Even if, for instance, T.sub.PWM is not an integral multiple of T.sub.S, the time deviation therefrom in specifying T.sub.U remains very slight owing to the use of the method described herein.