Clock recovery method, device and system and computer storage medium

Abstract

A clock recovery method is provided. The method has the following operations: performing clock balance pre-filtering on an input time/frequency domain signal according to a self-adaptive balance coefficient input currently, to obtain a balance pre-filtering signal; according to the balance pre-filtering signal, acquiring a phase error of the input time/frequency domain signal; and performing phase adjustment on the input time/frequency domain signal according to the phase error, and outputting a new self-adaptive balance coefficient after self-adaptive balance processing is performed on the phase-adjusted time/frequency domain signal. A clock recovery device and system and a non-transitory computer-readable storage medium are also provided.

Claims

1. A clock recovery method, comprising: performing a clock equalization pre-filtering on an input time and/or frequency domain signal according to a self-adaptive equalization coefficient inputted currently, to obtain an equalization pre-filtering signal; acquiring a phase error of the input time and/or frequency domain signal according to the equalization pre-filtering signal; and performing a phase adjustment on the input time and/or frequency domain signal according to the phase error and performing a self-adaptive equalization processing on the phase-adjusted time and/or frequency domain signal to output a new self-adaptive equalization coefficient.

2. The method according to claim 1, wherein the time and/or frequency domain signal comprises a first time and/or frequency domain sub-signal according to first optical polarization and a second time and/or frequency domain sub-signal according to second optical polarization, wherein the frequency domain signal is generated by converting a time domain signal into a frequency domain signal through a time-frequency conversion.

3. The method according to claim 1, wherein the performing the clock equalization pre-filtering on the input frequency domain signal according to the self-adaptive equalization coefficient inputted currently employs the following manner: $\{\begin{array}{c}{X}_{\mathrm{pd}}\left(k\right)=X\left(k\right)H_{\mathrm{xx}}\left(k\right)+Y\left(k\right)H_{\mathrm{xy}}\left(k\right)\\ Y_{\mathrm{pd}}\left(k\right)=X\left(k\right)H_{\mathrm{yx}}\left(k\right)+Y\left(k\right)H_{\mathrm{yy}}\left(k\right)\end{array},kK.Math.\left(K+\frac{N}{2}\right),K=\left(\frac{N}{8},\mathrm{.Math.}\frac{3N}{8}-1\right)$ wherein, H.sub.xx(k), H.sub.xy(k), H.sub.yx(k) and H.sub.yy(k) are frequency domain self-adaptive equalization coefficients, K is a frequency point index for phase discrimination, X(k) is a first frequency domain polarization sub-signal, Y(k) is a second frequency domain polarization sub-signal, and X.sub.pd(k) and Y.sub.pd(k) are the equalization pre-filtering signals obtained after the clock equalization pre-filtering.

4. The method according to claim 3, wherein the acquiring the phase error of the input frequency domain signal according to the equalization pre-filtering signal employs the following manner: $C=\underset{k=0}{\overset{\frac{N}{2}-1}{.Math.}}\left\{X_{\mathrm{pd}}\left(k\right)X_{\mathrm{pd}}^{*}\left(k+\frac{N}{2}\right)+Y_{\mathrm{pd}}\left(k\right)Y_{\mathrm{pd}}^{*}\left(k+\frac{N}{2}\right)\right\}$ wherein, X.sub.pd(k) and Y.sub.pd(k) are the equalization pre-filtering signals obtained after the clock equalization pre-filtering; X*.sub.pd(k) and Y.sub.pd*(k) are complex conjugate signals of the equalization pre-filtering signals; and a phase value of C is calculated according to the following formula to obtain the phase error, between the input and output frequency domain signals: $=-\frac{1}{2}\arg \left(C\right)$ wherein, a value range of the phase error, is [0,1).

5. The method according to claim 4, wherein the performing the phase adjustment on the input frequency domain signal according to the phase error comprises: acquiring a phase adjustment angle (k) according to the following formula: $\left(k\right)=\{\begin{array}{c}\frac{2k}{N},0k\frac{N}{2}-1\\ \frac{2\left(k-N\right)}{N},\frac{N}{2}kN-1\end{array},k=0,\mathrm{.Math.},N-1,$ wherein, is the phase error, and the phase adjustment is performed on X(k) and Y(k) according to the phase adjustment angle (k) by using the following formula: $\{\begin{array}{c}{X}_{\mathrm{cr}}\left(k\right)=X\left(k\right)e^{i2\left(k\right)}\\ Y_{\mathrm{cr}}\left(k\right)=Y\left(k\right)e^{i2\left(k\right)}\end{array},k=0,\mathrm{.Math.},N-1$ wherein, X(k) is the first frequency domain polarization sub-signal, Y(k) is the second frequency domain polarization sub-signal, and X.sub.cr(k) and Y.sub.cr(k) are frequency domain signals obtained after the phase adjustment.

6. The method according to claim 4, wherein the performing the phase adjustment on the input time domain signal according to the phase error comprises: employing the following manner to perform the phase adjustment on the input time domain signal by using a cubic Lagrange interpolation algorithm: $z\left[k\right]=\underset{i=-2}{\overset{I}{.Math.}}{a}_{i}f\left[k-i\right]$ wherein, the coefficients are: $\{\begin{array}{c}{a}_{-2}=\frac{\left(u+1\right)u\left(u-1\right)}{6}\\ a_{-1}=\frac{\left(u+1\right)u\left(u-2\right)}{-2}\\ a_0=\frac{\left(u+1\right)\left(u-1\right)\left(u-2\right)}{2}\\ a_1=\frac{\left(u-1\right)u\left(u-2\right)}{-6}\end{array}$ wherein, z[k] is a sample point value obtained by interpolating a sample point f[k] to a k+ position through a decimal pointer, ; if every 128 sample points use the same interpolation decimal pointer, , then the decimal pointer, =mod(2, 1), and is the phase error.

7. The method according to claim 1, wherein the method, after the acquiring the phase error of the input time and/or frequency domain signal according to the equalization pre-filtering signal, further comprises filtering the phase error to obtain a filtered phase error; and wherein the performing the phase adjustment on the input time and/or frequency domain signal according to the phase error and performing the self-adaptive equalization processing on the phase-adjusted time and/or frequency domain signal to output the new self-adaptive equalization coefficient comprises: performing the phase adjustment on the input time and/or frequency domain signal according to the filtered phase error and performing the self-adaptive equalization processing on the phase-adjusted time and/or frequency domain signal to output the new self-adaptive equalization coefficient.

8. A clock recovery device, comprising: an equalization pre-filtering unit, a timing error extraction unit and a phase adjustment unit connected in sequence, wherein: the equalization pre-filtering unit is configured to perform a clock equalization pre-filtering on an input time and/or frequency domain signal according to a self-adaptive equalization coefficient inputted currently, and input the obtained equalization pre-filtering signal to the timing error extraction unit; the timing error extraction unit is configured to acquire a phase error of the input time and/or frequency domain signal according to the equalization pre-filtering signal, and input the obtained phase error to the phase adjustment unit; and the phase adjustment unit is configured to perform a phase adjustment on the input time and/or frequency domain signal according to the phase error, perform a self-adaptive equalization processing on the phase-adjusted time and/or frequency domain signal to output a new self-adaptive equalization coefficient, and feed the new self-adaptive equalization coefficient back to the equalization pre-filtering unit.

9. The device according to claim 8, wherein the time and/or frequency domain signal comprises a first time and/or frequency domain sub-signal according to first optical polarization and a second time and/or frequency domain sub-signal according to second optical polarization, wherein the frequency domain signal is generated by converting a time domain signal into a frequency domain signal through a time-frequency conversion.

10. The device according to claim 8, further comprising: a timing error filtering unit disposed between the timing error extraction unit and the phase adjustment unit, and configured to filter the phase error, and input the filtered phase error to the phase adjustment unit; wherein the phase adjustment unit is further configured to perform the phase adjustment on the input time and/or frequency domain signal according to the filtered phase error, perform a self-adaptive equalization processing on the phase-adjusted time and/or frequency domain signal, and output a new self-adaptive equalization coefficient.

11. The device according to claim 10, wherein the timing error filtering unit comprises a loop filter, a digital oscillator and a subtractor.

12. The device according to claim 8, wherein the equalization pre-filtering unit comprises a finite impulse response filter of a single polarization system, or a finite impulse response filter of a polarization multiplexing system.

13. A clock recovery system, comprising: the clock recovery device according to claim 8, and a self-adaptive equalizer, wherein: the clock recovery device inputs the phase-adjusted time and/or frequency domain signal to the self-adaptive equalizer; and the self-adaptive equalizer outputs the new self-adaptive equalization coefficient according to the phase-adjusted time and/or frequency domain signal, and feeds the new self-adaptive equalization coefficient back to an input end of the clock recovery device.

14. A non-transitory computer-readable storage medium storing instructions which, when executed by a processor, cause the processor to perform a clock recovery method comprising: performing a clock equalization pre-filtering on an input time and/or frequency domain signal according to a self-adaptive equalization coefficient inputted currently, to obtain an equalization pre-filtering signal; acquiring a phase error of the input time and/or frequency domain signal according to the equalization pre-filtering signal; and performing a phase adjustment on the input time and/or frequency domain signal according to the phase error and performing a self-adaptive equalization processing on the phase-adjusted time and/or frequency domain signal to output a new self-adaptive equalization coefficient.

15. The method according to claim 2, wherein the method, after acquiring the phase error of the input time and/or frequency domain signal according to the equalization pre-filtering signal, further comprises: filtering the phase error to obtain a filtered phase error; and wherein the performing the phase adjustment on the input time and/or frequency domain signal according to the phase error and performing the self-adaptive equalization processing on the phase-adjusted time and/or frequency domain signal to output the new self-adaptive equalization coefficient comprises: performing the phase adjustment on the input time and/or frequency domain signal according to the filtered phase error and performing the self-adaptive equalization processing on the phase-adjusted time and/or frequency domain signal to output the new self-adaptive equalization coefficient.

16. The method according to claim 3, wherein the method, after acquiring the phase error of the input time and/or frequency domain signal according to the equalization pre-filtering signal, further comprises: filtering the phase error to obtain a filtered phase error; and wherein the performing the phase adjustment on the input time and/or frequency domain signal according to the phase error and performing the self-adaptive equalization processing on the phase-adjusted time and/or frequency domain signal to output the new self-adaptive equalization coefficient comprises: performing the phase adjustment on the input time and/or frequency domain signal according to the filtered phase error and performing the self-adaptive equalization processing on the phase-adjusted time and/or frequency domain signal to output the new self-adaptive equalization coefficient.

17. The method according to claim 4, wherein the method, after acquiring the phase error of the input time and/or frequency domain signal according to the equalization pre-filtering signal, further comprises: filtering the phase error to obtain a filtered phase error; and wherein the performing the phase adjustment on the input time and/or frequency domain signal according to the phase error and performing the self-adaptive equalization processing on the phase-adjusted time and/or frequency domain signal to output the new self-adaptive equalization coefficient comprises: performing the phase adjustment on the input time and/or frequency domain signal according to the filtered phase error and performing the self-adaptive equalization processing on the phase-adjusted time and/or frequency domain signal to output the new self-adaptive equalization coefficient.

18. The method according to claim 5, wherein the method, after acquiring the phase error of the input time and/or frequency domain signal according to the equalization pre-filtering signal, further comprises: filtering the phase error to obtain a filtered phase error; and wherein the performing the phase adjustment on the input time and/or frequency domain signal according to the phase error and performing the self-adaptive equalization processing on the phase-adjusted time and/or frequency domain signal to output the new self-adaptive equalization coefficient comprises: performing the phase adjustment on the input time and/or frequency domain signal according to the filtered phase error and performing the self-adaptive equalization processing on the phase-adjusted time and/or frequency domain signal to output the new self-adaptive equalization coefficient.

19. The method according to claim 6, wherein the method, after acquiring the phase error of the input time and/or frequency domain signal according to the equalization pre-filtering signal, further comprises: filtering the phase error to obtain a filtered phase error; and wherein the performing the phase adjustment on the input time and/or frequency domain signal according to the phase error and performing the self-adaptive equalization processing on the phase-adjusted time and/or frequency domain signal to output the new self-adaptive equalization coefficient comprises: performing the phase adjustment on the input time and/or frequency domain signal according to the filtered phase error and performing the self-adaptive equalization processing on the phase-adjusted time and/or frequency domain signal to output the new self-adaptive equalization coefficient.

20. The device according to claim 9, further comprising: a timing error filtering unit disposed between the timing error extraction unit and the phase adjustment unit, and configured to filter the phase error, and input the filtered phase error to the phase adjustment unit; wherein the phase adjustment unit is further configured to perform the phase adjustment on the input time and/or frequency domain signal according to the filtered phase error, perform a self-adaptive equalization processing on the phase-adjusted time and/or frequency domain signal, and output a new self-adaptive equalization coefficient.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a block diagram of an existing digital coherent receiver;

(2) FIG. 2 is a block diagram showing a structure of a first clock recovery system according to the embodiments of the present disclosure;

(3) FIG. 3 is a block diagram showing a structure of a second clock recovery system according to the embodiments of the present disclosure;

(4) FIG. 4 is a block diagram showing an implementation flow of a first clock recovery method according to the embodiments of the present disclosure;

(5) FIG. 5 is a block diagram showing an implementation flow of a second clock recovery method according to the embodiments of the present disclosure;

(6) FIG. 6 is a block diagram showing an implementation structure in which a timing error filtering unit filters a phase error according to the embodiments of the present disclosure;

(7) FIG. 7 is a block diagram showing a structure of a clock recovery system according to a first embodiment of the present disclosure;

(8) FIG. 8 is a block diagram showing a structure of a clock recovery system according to a second embodiment of the present disclosure; and

(9) FIG. 9 is a block diagram showing a structure of a clock recovery device according to the embodiments of the present disclosure.

DETAILED DESCRIPTION

(10) In the embodiments of the present disclosure, clock equalization pre-filtering is performed on an input time/frequency domain signal according to a self-adaptive equalization coefficient input currently, to obtain an equalization pre-filtering signal; a phase error of the input time/frequency domain signal is acquired according to the equalization pre-filtering signal; and phase adjustment is performed on the input time/frequency domain signal according to the phase error, and a new self-adaptive equalization coefficient is output after self-adaptive equalization processing is performed on the phase-adjusted time/frequency domain signal. In this manner, the self-adaptive equalization coefficient can be adjusted continuously, the dynamic change of a channel can be tracked more preferably, and channel distortion can be compensated exactly, so that the effect of the clock equalization pre-filtering is better, so as to be capable of quickly and exactly extracting the phase error of the input time/frequency signal, and restoring the phase of the input time/frequency signal more preferably.

(11) Here, the currently input self-adaptive equalization coefficient is a self-adaptive equalization coefficient output and fed back after the self-adaptive equalization processing is performed on the input phase-adjusted time/frequency domain signal by a self-adaptive equalizer. The originally inputted self-adaptive equalization coefficient is preset by a system, and the time/frequency domain signal includes a first time/frequency domain sub-signal according to first optical polarization and a second time/frequency domain sub-signal according to second optical polarization; and the time domain signal becomes the frequency domain signal through a time-frequency conversion.

(12) The embodiments of the present disclosure would be further described in details hereinafter with reference to the drawings.

(13) FIG. 2 is a block diagram showing a structure of a clock recovery system provided by the embodiments of the present disclosure. As shown in FIG. 2, the system includes: a clock recovery device 20 and a self-adaptive equalizer 21, wherein the clock recovery device 20 includes an equalization pre-filtering unit 200, a timing error extraction unit 201 and a phase adjustment unit 202 connected in sequence, and the foregoing functional modules may either be software functional modules or hardware devices.

(14) The clock recovery device 20 inputs the phase-adjusted time/frequency domain signal to the self-adaptive equalizer 21; and the self-adaptive equalizer 21 outputs a new self-adaptive equalization coefficient according to the phase-adjusted time/frequency domain signal, and feeds back the new coefficient to the input end of the clock recovery device 20.

(15) In the clock recovery device 20, the equalization pre-filtering unit 200 is configured to perform clock equalization pre-filtering on an input time/frequency domain signal according to a self-adaptive equalization coefficient input currently, the equalization pre-filtering signal obtained being input to the timing error extraction unit 201.

(16) The self-adaptive equalization coefficient input currently is the self-adaptive equalization coefficient output and fed back after self-adaptive equalization processing is performed on the input phase-adjusted time/frequency domain signal by the self-adaptive equalizer, and the initially inputted self-adaptive equalization coefficient is preset by a system; and the time/frequency domain signal includes a first time/frequency domain sub-signal according to first optical polarization and a second time/frequency domain sub-signal according to second optical polarization, the time domain signal becoming the frequency domain signal through time-frequency conversion.

(17) The timing error extraction unit 201 is configured to acquire a phase error of the input time/frequency domain signal according to the input equalization pre-filtering signal, the phase error obtained being input to the phase adjustment unit 202.

(18) The phase adjustment unit 202 is configured to perform phase adjustment on the input time/frequency domain signal according to the input phase error, and input the phase-adjusted time/frequency domain signal to the self-adaptive equalizer 21, so that the self-adaptive equalizer 21 outputs a new self-adaptive equalization coefficient and feeds back the new coefficient to the equalization pre-filtering unit 200.

(19) Based on the foregoing system structure, the clock recovery process provided by the embodiments of the present disclosure is particularly implemented as follows.

(20) Firstly, the equalization pre-filtering unit 200 performs clock equalization pre-filtering on the input time/frequency domain signal according to the self-adaptive equalization coefficient input currently, and inputs the obtained equalization pre-filtering signal to the timing error extraction unit 201.

(21) Then, the timing error extraction unit 201 acquires the phase error of the input time/frequency domain signal according to the equalization pre-filtering signal, and inputs the obtained phase error to the phase adjustment unit 202.

(22) Finally, the phase adjustment unit 200 performs phase adjustment on the input time/frequency domain signal according to the phase error, and inputs the phase-adjusted time/frequency domain signal to the self-adaptive equalizer 21, so that the self-adaptive equalizer 21 feeds back the updated self-adaptive equalization coefficient to the input end of the equalization pre-filtering unit 200.

(23) The initially inputted self-adaptive equalization coefficient is set by the system according to such parameters as the frequency and the phase of the input signal.

(24) Preferably, the clock recovery device further includes a timing error filtering unit 203 as shown in FIG. 3.

(25) The timing error filtering unit 203 is connected between the timing error extraction unit 201 and the phase adjustment unit 202, and is configured to filter the phase error, and input the phase error after the filtering to the phase adjustment unit 202.

(26) The phase adjustment unit 200 is further configured to perform phase adjustment on the input time/frequency domain signal according to the input phase error after the filtering, and input the phase-adjusted time/frequency domain signal to the self-adaptive equalizer 21, so that the self-adaptive equalizer 21 outputs a new self-adaptive equalization coefficient.

(27) To facilitate description, parts of the above clock recovery system are divided into various modules or units by functions and are respectively described. Certainly, the functions of the modules or units may be implemented in one or more software or hardware while implementing the present disclosure.

(28) Based on the above system structure, the embodiments of the present disclosure provide a clock recovery method, as shown in FIG. 4, including the following steps.

(29) At step S400, clock equalization pre-filtering is performed on an input time/frequency domain signal according to a self-adaptive equalization coefficient input currently, to obtain an equalization pre-filtering signal.

(30) The step may be implemented by the equalization pre-filtering unit 200 in the clock recovery device 20.

(31) In this step, the self-adaptive equalization coefficient input currently is the self-adaptive equalization coefficient output and fed back after performing self-adaptive equalization processing on the input phase-adjusted time/frequency domain signal by the self-adaptive equalizer, and the initially inputted self-adaptive equalization coefficient is preset by a system. The time/frequency domain signal includes a first time/frequency domain sub-signal according to first optical polarization such as x polarization and a second time/frequency domain sub-signal according to second optical polarization such as y polarization.

(32) In this step, the filtering of the equalization pre-filtering unit 200 may either be implemented in a time domain or in a frequency domain. The input signal may either be a time domain signal or a frequency domain signal, and the corresponding output may either be a time domain signal or a frequency domain signal.

(33) If it is needed to input a frequency domain signal, then before inputting a time domain signal to the equalization pre-filtering unit 200, it is necessary to convert the time domain signal into a frequency domain signal through a module or device having a time-frequency conversion function such as a Fourier transformation module, and then input the obtained frequency domain signal to the equalization pre-filtering unit 200. If the self-adaptive equalization coefficient fed back by the self-adaptive equalizer is a time domain coefficient, and a frequency domain coefficient is needed, then it is necessary to add a time-frequency conversion unit between the self-adaptive equalizer and the equalization pre-filtering unit 200; or, a module having the time-frequency conversion function is added in the equalization pre-filtering unit 200 to convert the time domain coefficient fed back by the self-adaptive equalizer into a frequency domain coefficient.

(34) The equalization pre-filtering unit 200 may be implemented by using an FIR filter of a single polarization system or an FIR filter of a polarization multiplexing system.

(35) In this step, when inputting a frequency domain signal and a frequency domain self-adaptive equalization coefficient, the equalization pre-filtering unit 200 performs clock equalization pre-filtering on the input frequency domain signal, specifically employing the following manner

(36) $\{\begin{array}{c}{X}_{\mathrm{pd}}\left(k\right)=X\left(k\right)H_{\mathrm{xx}}\left(k\right)+Y\left(k\right)H_{\mathrm{xy}}\left(k\right)\\ Y_{\mathrm{pd}}\left(k\right)=X\left(k\right)H_{\mathrm{yx}}\left(k\right)+Y\left(k\right)H_{\mathrm{yy}}\left(k\right)\end{array},kK.Math.\left(K+\frac{N}{2}\right),K=\left(\frac{N}{8},\mathrm{.Math.}\frac{3N}{8}-1\right)$

(37) wherein, H.sub.xx(k), H.sub.xy(k), H.sub.yx(k) and H.sub.yy(k) are frequency domain self-adaptive equalization coefficients, K is a frequency point index for phase discrimination, X(k) is a first frequency domain polarization sub-signal, Y(k) is a second frequency domain polarization sub-signal, and X.sub.pd(k) and Y.sub.pd(k) are equalization pre-filtering signals obtained after the clock equalization pre-filtering, and the obtained equalization pre-filtering signal is input to the timing error extraction unit 201.

(38) In this step, the equalization pre-filtering unit 200 employs the self-adaptive equalization coefficient fed back by the self-adaptive equalizer to perform clock equalization pre-filtering on the time/frequency domain signal, so that the dynamic change of a channel can be tracked more preferably, and channel distortion can be compensated exactly, so that the effect of the clock equalization pre-filtering is better, so as to be capable of quickly and exactly extracting the phase error of the input time/frequency signal, and restoring the phase of the input time/frequency signal more preferably.

(39) At step S401, a phase error of the input time/frequency domain signal is acquired according to the equalization pre-filtering signal.

(40) This step may be implemented by the timing error extraction unit 201 in the clock recovery device.

(41) In this step, the error extracting of the timing error extraction unit 201 may be implemented in a time domain or in a frequency domain. The input time/frequency signal may either be a time domain signal or a frequency domain signal, and the corresponding output may either be a time domain signal or a frequency domain signal.

(42) Usually, the timing error extraction unit 201 may employ a square timing error extraction algorithm or the like to extract the phase error of the input time domain signal; and may employ a Godard algorithm or the like to extract the phase error of the input frequency domain signal. The extraction algorithm of the phase error is not specifically defined herein.

(43) In this step, the equalization pre-filtering signal is the frequency domain equalization pre-filtering signal obtained in the foregoing step S400; therefore, the timing error extraction unit 201 may employ a Godard algorithm to acquire the phase error of the input frequency domain signal according to the equalization pre-filtering signal, wherein the particular implementation manner is as follows:

(44) $C=\underset{k=0}{\overset{\frac{N}{2}-1}{.Math.}}\left\{X_{\mathrm{pd}}\left(k\right)X_{\mathrm{pd}}^{*}\left(k+\frac{N}{2}\right)+Y_{\mathrm{pd}}\left(k\right)Y_{\mathrm{pd}}^{*}\left(k+\frac{N}{2}\right)\right\}$

(45) wherein, X.sub.pd(k) and Y.sub.pd(k) are equalization pre-filtering signals obtained after the clock equalization pre-filtering; X*.sub.pd(k) and Y.sub.pd*(k) are complex conjugate signals of the equalization pre-filtering signals; and the phase value of C is calculated according to the following formula to obtain the phase error of the input frequency domain signals:

(46) 0$=-\frac{1}{2}\arg \left(C\right)$

(47) wherein the value range of the phase error is [0,1), and obtained the phase error is input to the phase adjustment unit 202.

(48) In this step, the timing error extraction unit 201 acquires the phase error of the input time/frequency domain signal according to the equalization pre-filtering signal, wherein the equalization pre-filtering signal is a signal obtained by performing clock equalization pre-filtering on the input time/frequency domain signal by the equalization pre-filtering unit 200 using the self-adaptive equalization coefficient fed back by the self-adaptive equalizer 21; in this way, the timing error extraction unit 201 can extract the phase error of the input time/frequency domain signal more exactly.

(49) At step S403, phase adjustment is performed on the input time/frequency domain signal according to the phase error, and a new self-adaptive equalization coefficient is output after self-adaptive equalization processing is performed on the phase-adjusted time/frequency domain signal.

(50) This step may be implemented by the phase adjustment unit 202 in the clock recovery device 20.

(51) In this step, if a frequency domain signal is input to the phase adjustment unit 202, then performing the phase adjustment on the input frequency domain signal according to the phase error obtained in the foregoing step S401 specifically employs the following manner:

(52) acquiring a phase adjustment angle (k) according to the following formula:

(53) $\left(k\right)=\{\begin{array}{c}\frac{2k}{N},0k\frac{N}{2}-1\\ \frac{2\left(k-N\right)}{N},\frac{N}{2}kN-1\end{array},k=0,\mathrm{.Math.},N-1$

(54) wherein, is the phase error, and phase adjustment is performed on X(k) and Y(k) according to the phase adjustment angle (k) using the following formula:

(55) $\{\begin{array}{c}{X}_{\mathrm{cr}}\left(k\right)=X\left(k\right)e^{i2\left(k\right)}\\ Y_{\mathrm{cr}}\left(k\right)=Y\left(k\right)e^{i2\left(k\right)}\end{array},k=0,\mathrm{.Math.},N-1$

(56) wherein, X(k) is a first frequency domain sub-signal, Y(k) is a second frequency domain sub-signal, and X.sub.cr(k) and Y.sub.cr(k) are frequency domain signals obtained after the phase adjustment.

(57) If a time domain signal is input to the phase adjustment unit 202, then an interpolation operation is performed on the input frequency domain signal according to the phase error obtained in the foregoing step S401 so as to adjust the phase of the input time domain signal, wherein a fraction interpolation algorithm such as a cubic Lagrange interpolation algorithm may be employed as the interpolation algorithm, and the interpolation algorithm would not be specifically defined herein.

(58) If the cubic Lagrange interpolation algorithm is employed to perform phase adjustment on the input time domain signal, the following manner is employed specially:

(59) $z\left[k\right]=\underset{i=-2}{\overset{I}{.Math.}}{a}_{i}f\left[k-i\right]$

(60) wherein, the coefficients are:

(61) $\{\begin{array}{c}{a}_{-2}=\frac{\left(u+1\right)u\left(u-1\right)}{6}\\ a_{-1}=\frac{\left(u+1\right)u\left(u-2\right)}{-2}\\ a_0=\frac{\left(u+1\right)\left(u-1\right)\left(u-2\right)}{2}\\ a_1=\frac{\left(u-1\right)u\left(u-2\right)}{-6}\end{array}$

(62) wherein, z[k] is a sample point value obtained by interpolating a sample point f[k] to a k+ position through a decimal pointer ; and if every 128 sample points use the same interpolation decimal pointer , then the decimal pointer =mod(2, 1), and is the phase error.

(63) In another embodiment of the present disclosure, the foregoing embodiment is optimized. As shown in FIG. 5, the method, after the step S401 and before the step S403, further includes a step S402.

(64) At step S402, the phase error is filtered to obtain a phase error after filtering.

(65) Accordingly, the phase error used for performing phase adjustment on the time/frequency domain signal in step S403 is the phase error after the filtering in step S402.

(66) One preferred implementation manner of step S402 is given below. The step S402 may be implemented by the timing error filtering unit 203 in the clock recovery device.

(67) In this step, the timing error filtering unit 203 can be implemented using a loop filter, a digital control oscillator and a subtractor. As shown in FIG. 6, the particular implementation manner is as follows.

(68) Firstly, the subtractor calculates a difference .sub.e between the phase error and the filtered phase error .sub.1 fed back by the digital control oscillator:

(69) ${}_e=\{\begin{array}{cc}\mathrm{mod}\left(-{}_1,1\right),& \mathrm{mod}\left(-{}_1,1\right)<0.5\\ \mathrm{mod}\left(-{}_1,1\right)-1,& \mathrm{mod}\left(-{}_1,1\right)0.5\end{array}$

(70) Then, the obtained difference .sub.e is input to the loop filter.

(71) And then, the loop filter filters the difference .sub.e using a proportional gain channel and an integral gain channel usually, wherein the proportional gain channel is composed of a proportional gain module k1, while the integral gain channel is composed of an integral gain module k2 and an integrator (accumulator) connected with the integral gain module k2 in series; the results of the proportional gain channel and the integral gain channel are added as the output of the loop filter, and the output of the loop filter is input to the digital control oscillator.

(72) Finally, the digital control oscillator which is an integrator (accumulator) feeds back the filtered phase error .sub.1 to the subtractor, and outputs the phase error .sub.1 to the phase adjustment unit 202.

(73) In the foregoing preferred implementation manner of step S402, the filtering the phase error to obtain the filtered phase error .sub.1 not only can evaluate the phase error more exactly, but also can track timing frequency deviation. The phase error used for performing the interpolation operation on the input time/frequency domain signal in step S403 is the filtered phase error .sub.1 in step S402; in this way, the phase of the input time/frequency domain signal can be adjusted and restored more preferably, i.e., the sampling positions can be adjusted more preferably.

(74) In the foregoing embodiments of the present disclosure, clock equalization pre-filtering is performed on the input time/frequency domain signal according to the self-adaptive equalization coefficient input currently, to obtain the equalization pre-filtering signal; the phase error of the input time/frequency domain signal is acquired according to the equalization pre-filtering signal; and phase adjustment is performed on the input time/frequency domain signal according to the phase error, and the new self-adaptive equalization coefficient is output after self-adaptive equalization processing is performed on the phase-adjusted time/frequency domain signal. In this manner, performing clock equalization pre-filtering on the time/frequency domain signal through the continuously updated self-adaptive equalization coefficient can implement a better clock equalization pre-filtering effect, so that the effect of the clock equalization pre-filtering is better, so as to be capable of quickly and exactly extracting the phase error of the input time/frequency signal, and restoring the phase of the input time/frequency signal more preferably, i.e., adjusting the sampling positions more preferably.

(75) The embodiments of the present disclosure also provide a computer storage medium, wherein the computer storage medium is stored with a computer-executable instruction, and the computer-executable instruction is configured to perform the aforementioned clock recovery method.

(76) The implementations of the present disclosure would be illustrated in details hereinafter with reference to the specific embodiments.

(77) First Embodiment

(78) In order to explain the embodiments of the present disclosure more clearly, the clock phase recovery process corresponding to a flow as shown in FIG. 4 is described hereinafter by taking a system structure as shown in FIG. 7 for example.

(79) As shown in FIG. 7, the system includes: a clock recovery device 20 and a self-adaptive equalizer 21; the clock recovery device 20 may include: a time-frequency conversion unit 204, an equalization pre-filtering unit 200, a timing error extraction unit 201, a timing error filtering unit 203 and a phase adjustment unit 202.

(80) In step S400, after receiving time a domain input signal including a first polarization sub-signal and a second polarization sub-signal, the time-frequency conversion unit 204 performs a FFT transformation on the two time domain signals to obtain frequency domain signals. Herein, considering that the output of the time-frequency conversion unit 204 is namely the input of the phase adjustment unit 202, the input data of the time-frequency conversion unit 204 needs to be stacked by a certain points; if the sample points of the time domain signal inputted each time are 128, it may select to stack 32 points to perform FFT transformation with N=160 points:

(81) $\{\begin{array}{c}X\left(k\right)=\underset{n=0}{\overset{N-1}{.Math.}}x\left(n\right)e^{-i\frac{2\mathrm{nk}}{N}}\\ Y\left(k\right)=\underset{n=0}{\overset{N-1}{.Math.}}y\left(n\right)e^{-i\frac{2\mathrm{nk}}{N}}\end{array},k=0,\mathrm{.Math.},N-1$

(82) wherein, x(n) is a first time domain polarization sub-signal, and y(n) is a second time domain polarization sub-signal; the time-frequency conversion unit 204 performs FFT transformation to obtain two frequency domain signals X(k) and Y(k) in a state of polarization, and input them to the equalization pre-filtering unit 200 and the phase adjustment unit 202.

(83) After inputting the two frequency domain signals in a state of polarization and the frequency domain self-adaptive equalization coefficient input currently, the equalization pre-filtering unit 200 performs clock equalization pre-filtering on the input frequency domain signal according to the self-adaptive equalization coefficient input currently, specifically employing the following manner:

(84) $\{\begin{array}{c}{X}_{\mathrm{pd}}\left(k\right)=X\left(k\right)H_{\mathrm{xx}}\left(k\right)+Y\left(k\right)H_{\mathrm{xy}}\left(k\right)\\ Y_{\mathrm{pd}}\left(k\right)=X\left(k\right)H_{\mathrm{yx}}\left(k\right)+Y\left(k\right)H_{\mathrm{yy}}\left(k\right)\end{array},kK.Math.\left(K+\frac{N}{2}\right),K=\left(\frac{N}{8},\mathrm{.Math.}\frac{3N}{8}-1\right)$

(85) wherein, H.sub.xx(k), H.sub.xy(k), H.sub.yx(k) and H.sub.yy(k) are frequency domain self-adaptive equalization coefficients, K is a frequency point index for phase discrimination, X(k) is a first frequency domain polarization sub-signal, Y(k) is a second frequency domain polarization sub-signal, X.sub.pd(k) and Y.sub.pd(k) are equalization pre-filtering signals obtained after the clock equalization pre-filtering, and the obtained equalization pre-filtering signal is input to the timing error extraction unit 201.

(86) In step S401, the timing error extraction unit 201 may employ a Godard algorithm to acquire the phase error of the input frequency domain signal according to the equalization pre-filtering signal, wherein the specific implementation manner is as follows:

(87) $C=\underset{k=0}{\overset{\frac{N}{2}-1}{.Math.}}\left\{X_{\mathrm{pd}}\left(k\right)X_{\mathrm{pd}}^{*}\left(k+\frac{N}{2}\right)+Y_{\mathrm{pd}}\left(k\right)Y_{\mathrm{pd}}^{*}\left(k+\frac{N}{2}\right)\right\}$

(88) wherein, X.sub.pd(k) and Y.sub.pd(k) are equalization pre-filtering signals obtained after the clock equalization pre-filtering, and X*.sub.pd(k) and Y.sub.pd*(k) are complex conjugate signals of the equalization pre-filtering signals; and the phase of C is calculated according to the following formula, i.e., the phase error of the input frequency domain signal:

(89) $=-\frac{1}{2}\arg \left(C\right)$

(90) wherein, the value range of the phase error is [0,1). The phase error is input to the phase adjustment unit 202.

(91) At step S402, the phase error is filtered to obtain a filtered phase error .sub.1.

(92) In step S403, phase adjustment is performed on the frequency domain signal according to the filtered phase error .sub.1, specifically employing the following manner:

(93) acquiring a phase adjustment angle (k) according to the following formula:

(94) 0$\left(k\right)=\{\begin{array}{c}{}_1\frac{2k}{N},0k\frac{N}{2}-1\\ {}_1\frac{2\left(k-N\right)}{N},\frac{N}{2}kN-1\end{array},k=0,\mathrm{.Math.},N-1$

(95) wherein, .sub.1 is the filtered phase error, and phase adjustment is performed on X(k) and Y(k) according to the phase adjustment angle (k) using the following formula:

(96) $\{\begin{array}{c}{X}_{\mathrm{cr}}\left(k\right)=X\left(k\right)e^{i2\left(k\right)}\\ Y_{\mathrm{cr}}\left(k\right)=Y\left(k\right)e^{i2\left(k\right)}\end{array},k=0,\mathrm{.Math.},N-1$

(97) wherein, X(k) is a first frequency domain polarization sub-signal, Y(k) is a second frequency domain polarization sub-signal, and X.sub.cr(k) and Y.sub.cr(k) are frequency domain signals obtained after the phase adjustment. The phase-adjusted frequency domain signal is input to the self-adaptive equalizer 21; and then the self-adaptive equalizer performs self-adaptive butterfly filtering, outputs an updated self-adaptive equalization coefficient, and feeds back the updated coefficient to the input end of the equalization pre-filtering unit 200.

(98) It should be illustrated that during the process of performing phase adjustment on the frequency domain signal, sample points may be added or deleted, and control signals for adding or deleting the sample points need to be output to the self-adaptive equalizer. A calculation method for adding or deleting the sample points is as follows: a current phase discrimination value .sub.1 is recorded as mu1, and a prior phase discrimination value .sub.1 is recorded as mu0, and then a difference between mu1 and mu0 is calculated.
dmu=mu1mu0

(99) A control signal num_add is calculated. When mu1<0.5 and dmu<0.5, the value of num_add is 1; and when mu10.5 and dmu0.5, the value of num_add is 1; for other cases, the value of num_add is 0.

(100) When num_add is 0, the data outputs 128 sample points through the self-adaptive equalizer; when num_add is 1, the data outputs 126 sample points through the self-adaptive equalizer; and when num_add is 1, the data outputs 130 sample points through the self-adaptive equalizer.

(101) Second Embodiment

(102) The clock recovery process corresponding to the flow as shown in FIG. 4 is described by taking the system structure as shown in FIG. 8 for example.

(103) As shown in FIG. 8, the system includes: a clock recovery device 20 and a self-adaptive equalizer 21; the clock recovery device may include: a time-frequency conversion unit 204, an equalization pre-filtering unit 200, a timing error extraction unit 201, a timing error filtering unit 203 and a phase adjustment unit 202.

(104) The step S400, the step S401 and the step S402 are as described in the foregoing embodiments.

(105) In step S403, an interpolation operation is performed on the input time domain signal according to the filtered phase error .sub.1, specifically employing the following manner:

(106) if a cubic Lagrange interpolation algorithm is employed, the specific implementation manner is as follows:

(107) adjusting the phase of the input time domain signal according to the following manner:

(108) $z\left[k\right]=\underset{i=-2}{\overset{I}{.Math.}}{a}_{i}f\left[k-i\right]$

(109) wherein, the coefficients are:

(110) $\{\begin{array}{c}{a}_{-2}=\frac{\left(u+1\right)u\left(u-1\right)}{6}\\ a_{-1}=\frac{\left(u+1\right)u\left(u-2\right)}{-2}\\ a_0=\frac{\left(u+1\right)\left(u-1\right)\left(u-2\right)}{2}\\ a_1=\frac{\left(u-1\right)u\left(u-2\right)}{-6}\end{array}$

(111) wherein, z[k] is a sample point value obtained by interpolating a sample point f[k] to a k+ position through a decimal pointer ; and if every 128 sample points use the same interpolation decimal pointer , then the decimal pointer =mod(2.sub.1, 1), and 1 is the filtered phase error.

(112) It should be illustrated that during the process of the digital interpolation operation, sample points would be added or deleted, and control signals for adding or deleting the sample points need to be output to the self-adaptive equalizer. A calculation method for adding or deleting the sample points is as follows: marking a current phase discrimination value .sub.1 as mu1, marking a prior phase discrimination value .sub.1 as mu0, and calculating a difference between mu1 and mu0.
dmu=mu1mu0

(113) A control signal num_add is calculated. When mu1<0.5 and dmu<0.5, the value of num_add is 1; when mu10.5 and dmu0.5, the value of num_add is 1; for other cases, the value of num_add is 0.

(114) When num_add is 0, 128 sample points are output through the self-adaptive equalizer from the data; when num_add is 1, 126 sample points are output through the self-adaptive equalizer from the data; and when num_add is 1, 130 sample points are output through the self-adaptive equalizer from the data.

(115) Preferably, after the time domain signal after the interpolation operation is obtained, sample points can be added or deleted for the time domain signal after the interpolation operation, and the time domain signal after adding or deleting the sample points is input to the self-adaptive equalizer, and the self-adaptive equalizer outputs an updated self-adaptive equalization coefficient.

(116) Based on the same technical concept, the embodiments of the present disclosure also provide a clock recovery device and system. Because the principles of the clock recovery device and system for solving problems are similar to the method, the implementation of the device can refer to the implementation of the method, and the repeated portions would not be elaborated.

(117) As shown in FIG. 9, the clock recovery device provided by the embodiment of the present disclosure may include: an equalization pre-filtering unit 200, a timing error extraction unit 201 and a phase adjustment unit 202 connected in sequence.

(118) The equalization pre-filtering unit 200 is configured to perform clock equalization pre-filtering on an input time/frequency domain signal according to a self-adaptive equalization coefficient input currently, the obtained equalization pre-filtering signal being input to the timing error extraction unit.

(119) The timing error extraction unit 201 is configured to acquire a phase error of the input time/frequency domain signal according to the equalization pre-filtering signal, the obtained phase error being input to the phase adjustment unit.

(120) The phase adjustment unit 202 is configured to perform phase adjustment on the input time/frequency domain signal according to the phase error, output a new self-adaptive equalization processing after self-adaptive equalization processing is performed on the phase-adjusted time/frequency domain signal, and feed back the new coefficient to the equalization pre-filtering unit.

(121) The time/frequency domain signal includes a first time/frequency domain sub-signal according to first optical polarization and a second time/frequency domain sub-signal according to second optical polarization, the time domain signal becoming the frequency domain signal through time-frequency conversion; and the equalization pre-filtering unit is implemented by using a finite impulse response FIR filter of a single polarization system or an FIR filter of a polarization multiplexing system.

(122) The division manner of the above functional modules is merely a preferred implementation manner given by the embodiments of the present disclosure, and the division manner of the above functional modules is not intend to limit the present disclosure.

(123) During specific implementation, the device further includes:

(124) a timing error filtering unit 203 connected between the timing error extraction unit and the phase adjustment unit, and configured to filter the phase error, the phase error after filtering being input to the phase adjustment unit; and

(125) the phase adjustment unit 202 being further configured to perform phase adjustment on the input time/frequency domain signal according to the phase error after the filtering, and output a new self-adaptive equalization coefficient after self-adaptive equalization processing is performed on the phase-adjusted time/frequency domain signal.

(126) The timing error filtering unit 203 may be implemented by using a loop filter, a digital oscillator and a subtractor.

(127) During practical application, all the equalization pre-filtering unit 200, the timing error extraction unit 201, the phase adjustment unit 202 and the timing error filtering unit 203 may be implemented through a central processing unit (CPU, Central Processing Unit), a micro processor unit (MPU, Micro Processor Unit), a digital signal processors (DSP, Digital Signal Processor) or a field programmable gate array (FPGA, Field programmable Gate Array) located in the clock recovery device; and all the CPU, the DSP and the FPGA may be built in the clock recovery system.

(128) The present disclosure is illustrated with reference to the flow chart and/or the block diagram of the method, device (system) and computer program product according to the embodiments of the present disclosure. It should be appreciated that each flow in the flow chart and/or each block in the block diagram and/or the combination of the flows in the flow chart and the blocks in the block diagram may be realized by computer program instructions. These computer program instructions may be provided to a general-purpose computer, a special purpose computer, an embedded processor or processors of other programmable data processing devices to generate a machine which makes the instructions executed by the processors of the computers or the processors of other programmable data processing devices generate a device for realizing the functions specified in one or more flows of the flow chart and/or one or more blocks in the block diagram.

(129) These computer program instructions may also be stored in a computer-readable memory which is capable of guiding a computer or another programmable data processing device to work in a given manner, thereby enabling the instructions stored in the computer-readable memory to generate a product including an instruction device for realizing the functions specified in one or more flows of the flow chart and/or one or more blocks in the block diagram.

(130) These computer program instructions may also be loaded to a computer or other programmable data processing devices to execute a series of operations thereon to generate the processing realized by the computer, so that the instructions executed by the computer or other programmable data processing devices offer the steps for realizing the functions specified in one or more flows of the flow chart and/or one or more blocks in the block diagram.

(131) Although preferred embodiments of the present disclosure have been described herein, additional variations and modifications may be made on these embodiments once those skilled in the art know the basic creative concept of the present disclosure. Thus, the accompanying claims are intended to cover the preferred embodiments and all the variations and modifications that fall within the scope of the present disclosure.

(132) Apparently, various modifications and variations can be devised by those skilled in the art without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure belong to the scope of the claims of the present disclosure and the equivalents thereof, then the present disclosure is also intended to cover such modifications and variations.