SELECTIVE NON-VOLATILE MEMORY DEVICE AND ASSOCIATED READING METHOD

Abstract

A selective non-volatile memory device includes a first electrode, a second electrode and at least one layer made of an active material. The device has at least two programmable memory states associated with two voltage thresholds and also provides a selective role when it is in a highly resistive state.

Claims

1 A selective non-volatile memory device comprising: a first electrode; a second electrode; at least one layer made of an active material, forming an active memory layer, disposed between the first and the second electrode; said selective non-volatile memory device having at least two programmable memory states: a first programmable non-volatile memory state associated with a first threshold voltage V.sub.th1 for the active memory layer, said selective non-volatile memory device having in said first memory state a characteristic voltage current such that said selective non-volatile memory device switches from a highly resistive state to a state that is less resistive than the highly resistive state as soon as a voltage greater than or equal to V.sub.th1 is applied between the first and second electrodes and returns to its highly resistive state when the voltage applied is strictly less than V.sub.th1, an intensity of the current passing through said selective non-volatile memory device in its highly resistive state being strictly less than 10.sup.−7 A; a second non-volatile memory state associated with a second threshold voltage V.sub.th2 strictly greater than the first threshold voltage V.sub.th1, said selective non-volatile memory device having in said second memory state a characteristic voltage current such that said selective non-volatile memory device switches from a highly resistive state to a state that is less resistive than the highly resistive state as soon as a voltage greater than or equal to V.sub.th2 is applied between the first and second electrodes and returns to its highly resistive state when the voltage applied is strictly less than V.sub.th2, the intensity of the current passing through said selective non-volatile memory device in its highly resistive state being strictly less than 10.sup.−7 A; the material of the active memory layer being made of a mixture of an As.sub.2Te.sub.3 alloy and of a Ge.sub.3Se.sub.7 alloy.

2. The selective non-volatile memory device according to claim 1, wherein the mixture comprises a percentage greater than 15% and strictly less than 60% by weight of the As.sub.2Te.sub.3 alloy.

3. The selective non-volatile memory device according to claim 2, wherein the mixture comprises a percentage substantially equal to 20% by weight of the As.sub.2Te.sub.3 alloy.

4. The selective non-volatile memory device according to claim 1, wherein a thickness of the active memory layer is chosen according to the difference desired between the first threshold voltage V.sub.th1 and the second threshold voltage V.sub.th2.

5. The selective non-volatile memory device according to claim 1, wherein the active memory layer is constituted by a single active layer made of a mixture of an As.sub.2Te.sub.3 alloy and of a Ge.sub.3Se.sub.7 alloy.

6. The selective non-volatile memory device according to claim 1, wherein the active memory layer is constituted by a stack of layers wherein each layer has a thickness less than or equal to 5 nm.

7. A method for writing the second memory state in a selective non-volatile memory device according to claim 1, comprising programming said second non-volatile memory state by applying a given programming current and a current pulse comprised between V.sub.th1 and V.sub.th2 with a descending flank of a predetermined duration.

8. A method for writing the first memory state in a selective non-volatile memory device according to claim 1, comprising programming 6 the first non-volatile memory state by applying a voltage pulse greater than V.sub.th2 with a predetermined descending flank of a predetermined non-zero duration and greater than a duration of the descending flank of the programming voltage pulse of the second memory state.

9. The method according to claim 8, wherein the descending flank of a predetermined non-zero duration of the voltage pulse greater than V.sub.th2 has a slope preferably comprised between 10.sup.6 V/s and 10.sup.8 V/s

10. A method for reading the memory state of the selective non-volatile memory device according to claim 1, comprising applying a pulse with a voltage strictly greater than V.sub.th1 and strictly less than V.sub.th2 with a predetermined descending flank of a predetermined non-zero duration and greater than a duration of a descending flank of a programming voltage pulse of the second memory state.

Description

BRIEF DESCRIPTION OF THE FIGURES

[0053] The figures are shown for the purposes of information and in no way limit the invention.

[0054] FIG. 1 shows a first addressing architecture of a plurality of memory cells according to the prior art;

[0055] FIG. 2 shows a second addressing architecture of a plurality of memory cells according to the prior art;

[0056] FIG. 3 shows a graph that explains the operating principle of a selective device;

[0057] FIG. 4 shows a diagrammatical representation of a device according to a first aspect of the invention;

[0058] FIG. 5 shows the change in the current on a logarithmic scale passing through the device of FIG. 4 according to the voltage applied between its bottom and top electrodes;

[0059] FIG. 6 diagrammatically shows examples of programming and reading pulses making it possible to use the device of FIG. 4 as memory;

[0060] FIG. 7 shows the behaviour of the threshold voltage according to the slope of the descending flank of the programming pulse for three materials of the active layer of the device of FIG. 4;

[0061] FIG. 8 shows the behaviour of the sub-threshold current according to the slope of the descending flank of the programming pulse for three materials of the active layer of the device of FIG. 4;

[0062] FIG. 9 shows the slope of the descending flank “Ramp rate” of a programming pulse of the device of FIG. 4;

[0063] FIG. 10 shows the change in the voltage threshold for an example of material of the active layer of the device of FIG. 4 according to the voltage threshold for four different thicknesses of the active layer.

[0064] FIG. 11 shows another example of a programming pulse.

DETAILED DESCRIPTION OF AN EMBODIMENT OF THE INVENTION

[0065] Unless mentioned otherwise, the same element that appears on different figures has a unique reference.

[0066] [FIG. 1] has already been described in reference to the prior art.

[0067] [FIG. 2] has already been described in reference to the prior art.

[0068] [FIG. 3] has already been described in reference to the prior art.

[0069] [FIG. 4] shows a diagrammatical representation of a device 1 according to a first aspect of the invention.

[0070] [FIG. 5] shows the change in the current on a logarithmic scale passing through the device of FIG. 4 according to the voltage applied between its bottom and top electrodes.

[0071] [FIG. 6] diagrammatically shows examples of programming and reading pulses making it possible to use the device of FIG. 4 as memory.

[0072] [FIG. 7] shows the behaviour of the voltage threshold according to the slope of the descending flank of the programming pulse for three materials of the active layer of the device of FIG. 4.

[0073] [FIG. 8] shows the behaviour of the sub-threshold current according to the slope of the descending flank of the programming pulse for three materials of the active layer of the device of FIG. 4.

[0074] [FIG. 9] shows the slope of the descending flank “Ramp rate” of a programming pulse of the device of FIG. 4.

[0075] [FIG. 10] shows the change in the voltage threshold for an example of material of the active layer of the device of FIG. 4 according to the voltage threshold for four different thicknesses of the active layer

[0076] [FIG. 11] shows another example of a programming pulse.

[0077] As shall be seen in what follows, the device 1 is a device that serves as a non-volatile memory and selector, with the two functions being integrated into the same device 1 which comprises: [0078] a first electrode or bottom electrode 3; [0079] a second electrode or top electrode 4; [0080] a layer 2 made of an active material, referred to as active memory layer, disposed between the first and the second electrode.

[0081] A top electrode of a device is defined as the electrode located above this device and the bottom electrode of a device as the electrode located under this device, the electrodes being located on either side of the device. Of course, the adjectives “top” and “bottom” are here relative to the orientation of the assembly including the top electrode, the device and the bottom electrode to the extent that when turning over this assembly, the electrode previously qualified as top becomes the bottom electrode and the electrode previously qualified as bottom becomes the top electrode. Likewise, a vertical disposition of the electrodes can also be provided with the active layer 2 disposed between the two electrodes 3 and 4.

[0082] The bottom 3 and top 4 electrodes are each carried out a conductive material that can be different or the same for the two electrodes 3 and 4. Such a conductive material is for example TiN, TaN, W, TiWN, TiSiN or WN.

[0083] The active layer 2 is for example a layer of active material of the chalcogenide type carried out by mixing (by co-sputtering for example) from As.sub.2Te.sub.3 and Ge.sub.3Se.sub.7 alloys. Advantageously, the mixture forming the active material comprises a percentage greater than 15% and strictly less than 60% by weight of As.sub.2Te.sub.3. As a preferred example, the mixture forming the active material here comprises 20% by weight of As.sub.2Te.sub.3. The principle of co-sputtering is to use the energy of a plasma on the surface of one or more sputtering targets (here As.sub.2Te.sub.3 and Ge.sub.3Se.sub.7 targets), to pull off one-by-one the atoms of the material of the target or targets and deposit them, for example on the bottom electrode 3.

[0084] The material of the active layer 2 is chosen to allow the device 1 to have a very strong resistivity in its amorphous stationary state (so-called “OFF” state) and a strong conductivity once subjected to a voltage greater than a threshold voltage. The particularity of the material chosen is to allow for a modulation of this threshold voltage that can have several values (at least two threshold voltages V.sub.th1 and V.sub.th2) thanks to the control of the descending flank of the electrical programming pulse which shall be further covered in what follows. The presence of these two threshold voltages V.sub.th1 and V.sub.th2 (with the understanding that it is entirely possible to consider more than two threshold voltages with an ad hoc programming) is shown in FIG. 5 which shows the change in current (on a logarithmic scale) passing through the device 1 according to the voltage applied between the bottom 3 and top 4 electrodes, for the two threshold voltages V.sub.th1 and V.sub.th2 obtained by programming the device 1. Note that, in the embodiment described here, the second threshold voltage V.sub.th2 is strictly greater than the first threshold voltage V.sub.th1.

[0085] Thus, when the device 1 has a threshold voltage Vth1, the intensity of the current passing through it (designated by I.sub.Leak or sub-threshold current) is very low (the device is therefore very resistive) as long as the voltage at the terminals of the device 1 is strictly less than V.sub.th1. As soon as the threshold voltage Vth1 is reached, the current rapidly increases and the device 1 becomes very conductive. As soon as the voltage is reduced again under V.sub.th1, the device 1 becomes a low conductor again. Note that the material of the active layer is here chosen so that the sub-threshold current has a particularly low intensity; in other terms, the intensity of the sub-threshold current is strictly less than 10.sup.−7 A.

[0086] The behaviour of the device 1 is similar when it has a second threshold voltage V.sub.th2 strictly greater than the first threshold voltage V.sub.th1. In this case, the intensity of the current passing through it (I.sub.Leak or sub-threshold current) is very low as long as the voltage at the terminals of the device 1 is strictly less than V.sub.th2. As soon as the threshold voltage V.sub.th2 is reached, the current rapidly increases and the device 1 becomes very conductive. As soon as the voltage is reduced again below V.sub.th2, the device 1 becomes a low conductor again. Here again, the intensity of the sub-threshold current is strictly less than 10.sup.−7 A.

[0087] The particularity of the materials chosen for the active layer 2 is to be able to provide a modulation of the threshold voltage V.sub.th according to the type of electrical programming pulse of the device 1. In other terms, the device 1 has at least two different voltage thresholds (a first threshold voltage V.sub.th1 and a second threshold voltage V.sub.th2) due to the material of the active layer that will react differently according to the shape of the electrical programming pulse, and in particular according to the descending flank of the electrical programming pulse. This operation will be explained in more details hereinafter.

[0088] It is understood that as soon as, contrary to resistive memories of the PCRAM or CBRAM type, the memory state does not depend on the resistivity of the device 1 but on the value of the threshold voltage, V.sub.th1 or V.sub.th2, which can be programmed and written in a non-volatile manner in the device 1. The device 1 according to the invention can thus be designated by the terminology “NVTS” or “non-volatile threshold switching” (device with a non-volatile switching threshold). The memory information is here given by the value of the threshold voltage.

[0089] Furthermore, having an intensity of sub-threshold current strictly less than 10.sup.−7 A and a volatile behaviour of the resistivity of the device 1 (i.e. according to whether the voltage is above or below the threshold voltage, the device respectively switches to the conductive or resistive state) makes it possible to have a device 1 that also acts as a selector; in a configuration of the crossbar type, in the absence of a polarisation voltage greater than the threshold voltage at the terminals of the device, the current passing through the device is very low and makes it possible to prevent a parasitic leakage current of the “sneak pass” type.

[0090] The device 1 is therefore both a non-volatile memory device (with the threshold voltage as memory information) and a selector (with a very low leakage current).

[0091] The programming and the reading of the device 1 according to the invention in reference to FIG. 6 shall be explained in what follows. FIG. 6 shows examples of programming voltage pulses (three pulses 100, 101 and 102) and of reading according to time that makes it possible to use the device 1 according to the invention as memory. Note that the programming and reading voltages can be inverted in polarity because the device according to the invention responds identically to a pulse with an inverted sign. Thus, when reference is made to a first voltage Vth1 with an intensity less than the intensity of the second threshold voltage Vth2, it must be understood that the absolute values of the two voltages are compared when the latter are negative.

[0092] The pulse 100 (referred to as RESET) is a programming pulse to bring the device 1 to the programming state represented by the second threshold voltage V.sub.th2. This pulse has an intensity in voltage that is comprised between the first threshold voltage V.sub.th1 and the second threshold voltage V.sub.th2.

[0093] According to a first configuration, the device 1 is already in a programming state represented by the second threshold voltage V.sub.th2. In this case, the device 1 will remain in this state. Indeed, in order for a change in the threshold voltage to occur, a sufficient programming current has to flow in the device 1. Here, in accordance with FIG. 5, with the value of the voltage remaining under the second threshold voltage V.sub.th2, no switching can occur. This property makes it possible moreover to preserve the endurance of the device 1. However, according to a second configuration, if the device is in the programming state represented by the threshold voltage V.sub.th1, as the programming voltage exceeds the threshold voltage V.sub.th1, the device 1 switches to a conductive state and allows for the passing of a significant level of programming current. The duration of the descending flank of the pulse 100 is very short (close to 0). It is the combination of the presence of a significant programming current (i.e. conductive state of the device 1) and of the suitable choice of the substantially zero descending flank duration of the descent of the pulse for the specific material of the active layer 2 that makes it possible to modify the threshold voltage of the device 1 and have the latter change from V.sub.th1 to V.sub.th2 (thus the memory state V.sub.th2 is written although the memory state V.sub.th1 was written in the memory device 1).

[0094] The link between the descending duration of the programming pulse and the threshold voltage is shown in FIG. 7 which shows the behaviour of the threshold voltage V.sub.th (in Volts) according to the slope of the descending flank (in V/s) for three materials of the active layer Mat1, Mat2 and Mat3.

[0095] The active material Mat1 is a mixture of As.sub.2Te.sub.3 and Ge.sub.3Se.sub.7 alloys with 20% by weight of As.sub.2Te.sub.3.

[0096] The active material Mat2 is a mixture of As.sub.2Te.sub.3 and Ge.sub.3Se.sub.7 alloys with 40% by weight of As.sub.2Te.sub.3.

[0097] The active material Mat3 is a mixture of As.sub.2Te.sub.3 and Ge.sub.3Se.sub.7 alloys with 60% by weight of As.sub.2Te.sub.3.

[0098] The slope of the descending flank (“Ramp rate”) is defined in FIG. 9. This is the ratio between the maximum amplitude of the programming voltage pulse and the duration of the descending flank. In other terms, for a given amplitude, the lower the duration of the descending flank is, the larger the slope is.

[0099] It is observed in FIG. 7 that for the material Mat1, the threshold voltage substantially increases with the slope of the descending flank. Thus, for the composition Mat1, there is a window of threshold voltages V.sub.th that is very substantial that ranges from a voltage threshold of about 2.25V (for a slope of about 0.5.10.sup.7 V/s, i.e. a substantial descending flank duration) to a threshold voltage of about 3.5V (for a slope of about 0.8.10.sup.9 V/s, i.e. a very short descending flank duration).

[0100] Thus, if the device is in the programming state represented by the threshold voltage V.sub.th1 and a very short duration of the descending flank of the pulse 100 is used with a device 1 in a conductive state, the value of the threshold voltage will be modified thanks to the duration of the flank and will change the threshold voltage to the value V.sub.th2 by choosing the suitable duration of the descending flank.

[0101] The pulse 101 (referred to as SET) is a programming pulse to bring the device 1 to the programming state represented by the first threshold voltage V.sub.th1. This pulse has an intensity in voltage greater than the second threshold voltage V.sub.th2 and a descending flank that has a duration greater than the duration of the descending flank of the pulse 100.

[0102] Here, contrary to the RESET programming, the effect of the pulse 101 is independent of the starting memory state. As the programming pulse 101 has a voltage intensity that exceeds the second threshold voltage V.sub.th2 (and therefore a fortiori the threshold voltage V.sub.th1), the device 1 will become conductive as soon as its threshold voltage is exceeded (whether it is V.sub.th1 or V.sub.th2). The current will therefore reach a level of current that is substantial enough. Then, the invention resides in the choice of the material of the active layer 2 so that the duration of the descending flank makes it possible to pass to the first threshold voltage V.sub.th1. Here, the slope of the descending flank (“ramp rate”) is advantageously comprised between 10.sup.7 V/s and 10.sup.6 V/s, which can result for example in a pulse of 3.5V for a descending flank duration comprised between 350 ns and 3.5 μs. By applying such a descending duration, the first threshold voltage V.sub.th1 is “written” in the device 1.

[0103] It is observed in FIG. 7 that the material Mat1 has a maximum memory window with respect to the materials Mat2 and Mat3 (and therefore a maximum difference between the first threshold voltage V.sub.th1 and the second threshold voltage V.sub.th2). A percentage by weight of As.sub.2Te.sub.3 alloy of about 20% will therefore preferably be chosen. The material Mat2 with a percentage by weight of As.sub.2Te.sub.3 alloy of about 40% also offers this possibility with however a more reduced window. The material Mat3 with a percentage by weight of As.sub.2Te.sub.3 alloy of about 60% has on the other hand a window that is too reduced to allow for writing two different voltage thresholds in the same device according to the invention. Note that it is possible to choose the threshold voltages V.sub.th1 and V.sub.th2 at the two ends of the curve (Vthmin and Vthmax) but nothing prevents placing at another location of the curve: in this case, the duration of the slope of the descending flank will consequently be adapted (and reduced for the pulse 101 if a second threshold voltage V.sub.th2 is considered that is lower than the maximum value of V.sub.th2).

[0104] Advantageously, the alloys used for the active layer 2 do not have any crystallisation during the operation of the device 1 as NVTS.

[0105] This type of behaviour is linked to a reorganisation of the structure of the material that takes place during the application of a pulse with a sufficiently long descending flank, giving rise to a reduction in the threshold voltage of the device. It is to be underlined that even if a crystalline phase exists for As.sub.2Te.sub.3 and a crystalline phase for Ge.sub.3Se.sub.7, in the case of a mixture of the As.sub.2Te.sub.3 and Ge.sub.3Se.sub.7 alloys considered there is no corresponding crystalline phase. Only a phase segregation could give rise to the formation of a crystalline phase or phases (i.e. reached for example after an excessive rise in temperature, after excessive Resistive state/Conductive state cycling of the device, etc.). However, the behaviour of the NVTS type could be obtained through the preservation of an amorphous phase in the device in parallel with a partially or completely crystalline phase. This configuration is also compatible with the memory and selective functionalities of the device 1 object of the present invention.

[0106] Generally, the method for programming the device according to the invention comprises: [0107] a RESET step consisting of applying a voltage pulse comprised between V.sub.th1 and V.sub.th2 with a descending flank of a predetermined duration according to the material of the active layer of the device 1, to bring the device 1 to the programming state represented by the first threshold voltage V.sub.th2; [0108] a SET step consisting of applying a voltage pulse greater than V.sub.th2 with a predetermined descending flank of a predetermined non-zero duration according to the material of the active layer of the device 1 and greater than the duration of the descending flank of the RESET programming voltage pulse, to bring the device 1 to the programming state represented by the second threshold voltage V.sub.th1.

[0109] FIG. 8 shows the behaviour of the sub-threshold current (“Leakage Current”) according to the slope of the descending flank of the programming pulse for the three materials Mat1, Mat2 and Mat3 of the active layer 2 of the device 1. It is observed that this sub-threshold current remains at very low values much less than 10.sup.−7 A for the three materials Mat1, Mat2 and Mat3, regardless of the value of the slope of the descending flank of the programming pulse. This behaviour makes it possible to provide the selective function of the device 1.

[0110] The pulse 102 shown in FIG. 6 is a pulse that makes it possible to READ the memory state of the device 1. The READ pulse 102 is formed of a pulse with an intermediate voltage between the first threshold voltage V.sub.th1 and the second threshold voltage V.sub.th2. In the case of reading a programming state represented by the first threshold voltage V.sub.th1, the device 1 will become conductive due to the exceeding of the threshold voltage V.sub.th1, but the descending flank with a substantial duration of the pulse, substantially identical to that of a SET writing, will make it possible to reconstitute the programming state represented by the first initial threshold voltage V.sub.th1 without the risk of writing the second programming state V.sub.th2. Detecting a current passing through the device 1 indicates that the device 1 is in the memory state V.sub.th1. Inversely, in the case of a reading of a programming state represented by the second threshold voltage V.sub.th2, the device 1 will remain resistive (no switching) since the second threshold voltage V.sub.th2 is not exceeded. Not detecting current in the device 1 indicates that the device is in the memory state V.sub.th2. If the switching does not take place, the state V.sub.th2 is read and maintained at the same time without any risk of disturbance (untimely writing for example).

[0111] Generally, the method for reading the memory state of the device according to the invention comprises a step of applying a voltage pulse strictly greater than V.sub.th1 and strictly less than V.sub.th2 with a predetermined descending flank of a predetermined non-zero duration and greater than the duration of the descending flank of the programming voltage pulse of the second memory state V.sub.th2 (advantageously substantially identical to the duration of the descending flank of the programming voltage pulse of the first memory state V.sub.th1, i.e. with a slope of the descending flank advantageously comprised between 10.sup.7 V/s and 10.sup.6 V/s).

[0112] In light of the effect of the slope of the programming pulse on the material of the active layer 2, intermediate programming state between V.sub.th1 and V.sub.th2 can be considered in order to obtain a multi-level programming of the MLC (“multi-level cell”) type.

[0113] It should also be noted that the thickness of the active layer is advantageously chosen according to the difference desired between the first threshold voltage V.sub.th1 and the second threshold voltage V.sub.th2. This choice is in particular shown in FIG. 10 which shows the change in the threshold voltage for the material Mat2 according to the voltage threshold for four different thicknesses of the active layer 2: 10 nm, 15 nm, 25 nm and 50 nm. Thus, an increase in the thickness of the active layer advantageously increases the memory window, i.e. the possible difference between the two minimum and maximum threshold voltage. Such an increase goes against the current trend in PCRAMs which rather aims to reduce the thicknesses of the latter.

[0114] Although the invention was more specifically described in the case of a mixture of d′As.sub.2Te.sub.3 and of Ge.sub.3Se.sub.7 other alloys could be used, for example with a base of Si, Ge, As, Sb, Bi, S, Se, Te combined together but also with the introduction of elements (i.e. dopants) such as C, N or O. In particular the AsSe, AsTe, GeSe, GeS alloys with different stoichiometries are among those that could be combined in order to obtain the mechanism sought. Advantageously, the combination between an alloy of the IV-VI type (for example with a Ge and Se base) and an alloy of the VI-V type (for example with a As and Te base) can be used, the gap energy of the alloy of the IV-VI type being more substantial than that of the VI-V alloy. Note moreover that although the active layer 2 was described as a layer of material (mixture of As.sub.2Te.sub.3 and of Ge.sub.3Se.sub.7 alloys), a configuration of the active layer in the form of multi-layers of materials providing the memory behaviour and NVTS selector is also applicable to device according to the invention.

[0115] The deposition techniques of the different layers (electrodes, active layer) are well known to those skilled in the art. These can be techniques of the physical vapour deposition (PVD), chemical vapour deposition (CVD) or atomic layer deposition (ALD) type for example.

[0116] Of course, the programming proposed hereinabove is given solely for the purposes of illustration; an intelligent programming can be considered where the pulses can depend on the initial programming state of the device. This is the case for example when the device according to the invention has just been read and the state to be programmed corresponds to the state that has just been read: in this case, it is possible to overcome a programming pulse.

[0117] Likewise, any form of pulses that makes it possible to obtain the structural reorganisation of the material in the memory state V.sub.th1, of course constitutes a possible alternative. In particular, the descending flank of the pulse can be further reduced by considering the portion of the same flank that has an effective impact on the change in the threshold voltage V.sub.th. This type of pulse 200 is shown in FIG. 11. Contrary to the pulse 101 referred to as SET of FIG. 6, the pulse 200 is also a SET programming pulse to bring the device 1 to the programming state represented by the first threshold voltage V.sub.th1. This pulse 200 has an intensity in voltage greater than the second threshold voltage V.sub.th2 and a reduced descending flank 201 but the duration of which remains greater than the duration of the descending flank of the pulse 100 of FIG. 6. This remark is also valid for the reading pulse.

[0118] The global duration of each pulse of FIGS. 6 and 11 is chosen to guarantee the switching of the device if needed and the passing of a programming current for a sufficient duration in particular to reach the state V.sub.th2. This global duration can for example be comprised between 10 ns and 300 ns for the mixture of As.sub.2Te.sub.3 and Ge.sub.3Se.sub.7 alloys. The programming current, which depends on the size (i.e. the surface) of the device according to the invention, is in the case of our illustration comprised between 1 mA and 2 mA. [0119] In an alternative, the device according to the invention can be cointegrated in series with a resistive memory, to give rise to a device that would make it possible to use the selective property of the device according to the invention to access (read and program) the resistive memory and have at the same time intrinsic memorisation properties.