MEMORY DEVICE, AND DATA PROCESSING METHOD BASED ON MULTI-LAYER RRAM CROSSBAR ARRAY

Abstract

Embodiments of the present disclosure provide a memory device. The memory device includes an RRAM crossbar array that is configured to perform a logic operation, and resistance values of resistors in the RRAM crossbar array are all set to R.sub.on or R.sub.off to indicate a value 1 or 0. Based on the foregoing setting, an operation is implemented using the RRAM crossbar array, so that reliability of a logic operation of the RRAM crossbar array can be improved.

Claims

1. A memory device comprising: a control bus; and multiple memory units connected by the control bus, each of the multiple memory units comprising a control circuit and a computation circuit, wherein the computation circuit comprises a first resistive random access memory (RRAM) crossbar array and a format conversion circuit, the first RRAM crossbar array having multiple rows and multiple columns of memory cells and multiple word lines connected to respective rows of memory cells, and a plurality of comparator circuits each connected to a corresponding column of the first RRAM crossbar array, wherein the comparator circuits are set to have incremental thresholds, and outputs of the comparator circuits are connected to the format conversion circuit; wherein the control circuit is connected to the control bus and configured to: receive a computation instruction; parse the computation instruction into an instruction to perform a vector multiplication of vector A and vector B; setting the memory cells in the first RRAM crossbar array in the computation circuit such that states of memory cells of each column of the first RRAM crossbar array correspond to elements of vector B; setting the word lines of the first RRAM crossbar array according to elements of vector A; wherein the outputs of the comparator circuits are voltage signals corresponding to a first binary number in which a number of bits with a value 1 indicates a numerical result of multiplication of vector A and vector B; the format conversion circuit being set up to convert the outputs of the comparator circuits into an output corresponding to a second binary number having a numerical value equal to the numerical result of multiplication of vector A and vector B.

2. The memory device according to claim 1, wherein the format conversion circuit comprises: a second RRAM crossbar array connected to receive the outputs of the comparator circuits and configured to generate an output that corresponds to an intermediate binary number in which a location of a bit with a value 1 indicates the numerical result of multiplication of vector A and vector B; and a third RRAM crossbar array connected to receive the output of the second RRAM crossbar array and configured to generate the output corresponding to the second binary number.

3. The memory device according to claim 2, wherein the multiple rows and multiple columns of memory cells in the first RRAM crossbar array comprise N rows?N columns resistors, an input end of a resistor in each row at the first RRAM crossbar array is connected to a word line, an output end of a resistor in each column at the first RRAM crossbar array is connected to a bit line, N word lines of the first RRAM crossbar array are connected to the control circuit, and each of N bit lines of the first RRAM crossbar array are respectively connected to a comparator circuit of the plurality of comparator circuits; the first RRAM crossbar array generates N current signals on the N bit lines according to voltage signals input by the N word lines and a resistance value of a resistor at the first RRAM crossbar array, a voltage value of a voltage signal input by the j.sup.th word line in the N word lines is a voltage value corresponding to B.sub.j, a resistance value of a resistor in the j.sup.th row at the first RRAM crossbar array is a resistance value corresponding to A.sub.j, B.sub.j is the j.sup.th element of vector B, A.sub.j is the j.sup.th element of vector A, and a value of j ranges from 0 to N?1, wherein each of vector A and vector B indicates an N-dimensional vector, each elements of vector A and vector B indicates a value 1 or 0, and N is a positive integer not less than 2; the N comparator circuits respectively convert the N current signals into N voltage signals, and compare the N voltage signals with voltage thresholds respectively corresponding to the N comparator circuits, to output, from output ends of the comparator circuits, the voltage signals corresponding to the first binary number, wherein the first binary number is an N-dimensional vector, first K elements of the first binary number are 1, remaining elements are 0, and K is the result of multiplication of vector A and vector B; and the format conversion circuit receives the voltage signals corresponding to the first binary number from the output ends of the comparator circuits, and generates, according to the voltage signals corresponding to the first binary number and resistance values of resistors in the format conversion circuit, voltage signals corresponding to the second binary number, wherein the second binary number is a binary representation of K.

4. The memory device according to claim 3, wherein the j.sup.th comparator circuit in the N comparator circuits comprises a resistor R.sub.s of a constant resistance value and a comparator, one end of the resistor R.sub.s is connected to the j.sup.th bit line in the N bit lines and the comparator, the other end of the resistor R.sub.s is grounded, a voltage threshold of the j.sup.th comparator circuit is V.sub.r*g.sub.on*R.sub.s*(2j+1)/2, V.sub.r indicates a voltage value corresponding to a value 1, and g.sub.on indicates a reciprocal of R.sub.on.

5. The memory device according to claim 4, wherein the second RRAM crossbar array comprises a (2N?1) rows?N columns resistor array, an input end of a resistor in each row at the second RRAM crossbar array is connected to a word line, an output end of a resistor in each column at the second RRAM crossbar array is connected to a bit line, and each of word lines of the second RRAM crossbar array is connected to a output end of a comparator circuit in the first RRAM crossbar array; the second RRAM crossbar array receives the voltage signals corresponding to the first binary number from the output ends of the comparator circuits of the first RRAM crossbar array through the 2N?1 word lines, and performs a logic operation according to the voltage signal corresponding to the first computing result and a resistance value of a resistor at the second layer of RRAM crossbar array: ${\stackrel{\_}{O}}_{2,j}=\{\begin{array}{c}{\stackrel{\_}{O}}_{1,j}+O_{1,j+1},j<N-1\\ {\stackrel{\_}{O}}_{1,j},j=N-1\end{array}$ to obtain voltage signals corresponding to the intermediate binary number, wherein ?.sub.1,j is a negation of a value corresponding to a voltage signal output by a comparator circuit connected to the j.sup.th bit line of the first RRAM crossbar array, O.sub.1,j+1 is a value corresponding to a voltage signal output by a comparator circuit connected to the (j+1).sup.th bit line of the first RRAM crossbar array, and ?.sub.2,j is a negation of a value corresponding to a voltage signal output by the j.sup.th bit line of the second RRAM crossbar array; the third RRAM crossbar array comprises an N rows?n columns resistor array, an input end of a resistor in each row at the third RRAM crossbar array is connected to a word line, an output end of a resistor in each column at the third RRAM crossbar array is connected to a bit line, and n is greater than or equal to a minimum quantity of bits required for expressing the integer N in binary; and the third RRAM crossbar array receives voltage signals corresponding to the intermediate binary number from N bit lines of the second RRAM crossbar array through N word lines of the third RRAM crossbar array, and encodes the intermediate binary number according to the voltage signals corresponding to the intermediate binary number and resistance values of resistors at the third RRAM crossbar array to obtain voltage signals corresponding to the second binary number.

6. The memory device according to claim 5, wherein the j.sup.th word line of the third RRAM crossbar array is connected to the j.sup.th bit line of the second RRAM crossbar array, and a resistance value of a resistor in the j.sup.th row of the third RRAM crossbar array corresponds to a binary representation of the integer j+1.

7. The memory device according to claim 1, wherein vector A is a row vector of a matrix ?, vector B is a column vector of a matrix X, each of the multiple computation circuits in the memory device is set for performing point multiplication operations of a plurality of row vectors of the matrix ? and a plurality of column vectors of the matrix X, and the multiple computation circuits jointly implement a matrix multiplication operation of the matrix ? and the matrix X.

8. The memory device according to claim 1, wherein the instruction of the processor further comprises a data access instruction, and each memory unit further comprises: a storage circuit, wherein the storage circuit is connected to the control circuit, and the control circuit read data from the computation circuit or write data into the computation circuit according to the data access instruction.

9. A memory device comprising: a control bus; and a memory unit connected to the control bus, the memory unit comprising a control circuit and a computation circuit, wherein the computation circuit comprises a first resistive random access memory (RRAM) crossbar having multiple rows and multiple columns of memory cells and multiple word lines connected to respective rows of memory cells, and a plurality of comparator circuits each connected to a corresponding column of the first RRAM crossbar array, wherein the comparator circuits are set to have incremental thresholds; wherein the control circuit is connected to the control bus and configured to: receive a computation instruction; parse the computation instruction into an instruction to perform a vector multiplication of vector A and vector B; setting the memory cells in the first RRAM crossbar array in the computation circuit such that states of memory cells of each column of the first RRAM crossbar array correspond to elements of vector B; and setting the word lines of the first RRAM crossbar array according to elements of vector A, wherein the outputs of the comparator circuits are voltage signals corresponding to a first binary number in which a number of bits with a value 1 indicates a numerical result of multiplication of vector A and vector B.

10. The memory device according to claim 9, wherein the computation circuit further comprises a second RRAM crossbar array and a third RRAM crossbar array each having multiple rows and multiple columns of memory cells and multiple word lines connected to respective rows of memory cells, wherein outputs of the comparator circuits are connected to corresponding word lines of the second RRAM crossbar array, outputs of the second RRAM crossbar array are connected to corresponding words lines of the third RRAM crossbar array, wherein the second RRAM crossbar array being set up to convert the outputs of the comparator circuits into an output representing an intermediate binary number in which a location of a bit with a value 1 indicates the numerical result of multiplication of vector A and vector B; and the third RRAM crossbar array being set up to convert the output of the second RRAM crossbar into an output representing a second binary number having a numerical value equal to the numerical result of multiplication of vector A and vector B.

11. The memory device according to claim 10, wherein the multiple rows and multiple columns of memory cells in the first RRAM crossbar array comprise N rows?N columns resistors, an input end of a resistor in each row at the first RRAM crossbar array is connected to a word line, an output end of a resistor in each column at the first RRAM crossbar array is connected to a bit line, N word lines of the first RRAM crossbar array are connected to the control circuit, and each of N bit lines of the first RRAM crossbar array are respectively connected to a comparator circuit of the plurality of comparator circuits; the first RRAM crossbar array generates N current signals on the N bit lines according to voltage signals input by the N word lines and a resistance value of a resistor at the first RRAM crossbar array, a voltage value of a voltage signal input by the j.sup.th word line in the N word lines is a voltage value corresponding to B.sub.j, a resistance value of a resistor in the j.sup.th row at the first RRAM crossbar array is a resistance value corresponding to A.sub.j, B.sub.j is the j.sup.th element of vector B, A.sub.j is the j.sup.th element of vector A, and a value of j ranges from 0 to N?1, wherein each of vector A and vector B indicates an N-dimensional vector, each elements of vector A and vector B indicates a value 1 or 0, and N is a positive integer not less than 2; the N comparator circuits respectively convert the N current signals into N voltage signals, and compare the N voltage signals with voltage thresholds respectively corresponding to the N comparator circuits, to output, from output ends of the N comparator circuits, the voltage signals corresponding to the first binary number, wherein the first binary number is an N-dimensional vector, first K elements of the first binary number are 1, remaining elements are 0, and K is the result of multiplication of vector A and vector B; the second RRAM crossbar array receives the voltage signals corresponding to the first binary number from the output ends of the comparator circuits, and obtain, according to the voltage signals corresponding to the first binary number and resistance values of resistors in the second RRAM crossbar array, voltage signals corresponding to the intermediate binary number in which a location of a bit with a value 1 indicates the numerical result of multiplication of vector A and vector B; and the third RRAM crossbar array receives the voltage signals corresponding to the intermediate binary number from the bit lines of second RRAM crossbar array, and convert the intermediate binary number into the second binary number, wherein the second binary number is a binary representation of K.

12. The memory device according to claim 11, wherein the j.sup.th comparator circuit in the N comparator circuits comprises a resistor R.sub.s of a constant resistance value and a comparator, one end of the resistor R.sub.s is connected to the j.sup.th bit line in the N bit lines and the comparator, the other end of the resistor R.sub.s is grounded, a voltage threshold of the j.sup.th comparator circuit is V.sub.r*g.sub.on*R.sub.s*(2j+1)/2, V.sub.r indicates a voltage value corresponding to a value 1, and go, indicates a reciprocal of R.sub.on.

13. The memory device according to claim 11, wherein the second RRAM crossbar array comprises a (2N?1) rows?N columns resistor array, an input end of a resistor in each row at the second RRAM crossbar array is connected to a word line, an output end of a resistor in each column at the second RRAM crossbar array is connected to a bit line, and each of word lines of the second RRAM crossbar array is connected to a output end of a comparator circuit in the first RRAM crossbar array; the second RRAM crossbar array receives the voltage signals corresponding to the first binary number from the output ends of the comparator circuits of the first RRAM crossbar array through the 2N?1 word lines, and performs a logic operation according to the voltage signals corresponding to the first binary number and a resistance value of a resistor at the second RRAM crossbar array: ${\stackrel{\_}{O}}_{2,j}=\{\begin{array}{c}{\stackrel{\_}{O}}_{1,j}+O_{1,j+1},j<N-1\\ {\stackrel{\_}{O}}_{1,j},j=N-1\end{array}$ to obtain voltage signals corresponding to an intermediate binary number, wherein ?.sub.1,j is a negation of a value corresponding to a voltage signal output by a comparator circuit connected to the j.sup.th bit line of the first RRAM crossbar array, O.sub.1,j+1 is a value corresponding to a voltage signal output by a comparator circuit connected to the (j+1).sup.th bit line of the first RRAM crossbar array, and ?.sub.2,j is a negation of a value corresponding to a voltage signal output by the j.sup.th bit line of the second RRAM crossbar array; the third RRAM crossbar array comprises an N rows?n columns resistor array, an input end of a resistor in each row at the third RRAM crossbar array is connected to a word line, an output end of a resistor in each column at the third RRAM crossbar array is connected to a bit line, and n is greater than or equal to a minimum quantity of bits required for expressing the integer N in binary; and the third RRAM crossbar array receives voltage signals corresponding to the intermediate binary number from N bit lines of the second RRAM crossbar array through N word lines of the third RRAM crossbar array, and encodes the intermediate binary number according to the voltage signals corresponding to the intermediate binary number and resistance values of resistors at the third RRAM crossbar array to obtain voltage signals corresponding to the second binary number.

14. The memory device according to claim 13, wherein the j.sup.th word line of the third RRAM crossbar array is connected to the j.sup.th bit line of the second RRAM crossbar array, and a resistance value of a resistor in the j.sup.th row of the third RRAM crossbar array corresponds to a binary representation of the integer j+1.

15. The memory device according to claim 9, wherein the memory device comprises multiple memory units, each of the multiple memory units comprises a control circuit and a computation circuit, vector A is a row vector of a matrix ? and vector B is a column vector of a matrix X, each of the multiple computation circuits in the memory device is set for performing point multiplication operations of a plurality of row vectors of the matrix ? and a plurality of column vectors of the matrix X, and the multiple computation circuits jointly implement a matrix multiplication operation of the matrix ? and the matrix X.

16. The memory device according to claim 9, wherein the instruction of the processor further comprises a data access instruction, and the memory unit further comprises: a storage circuit, wherein the storage circuit is connected to the control circuit, and the control circuit read data from the computation circuit or write data into the computation circuit according to the data access instruction.

17. A computing device, comprising: a processor configured to send a computation instruction; a memory device connected to the processor, wherein the memory device comprising a control bus and a memory unit connected to the control bus, the memory unit comprising a control circuit and a computation circuit; wherein the computation circuit comprises a first resistive random access memory (RRAM) crossbar having multiple rows and multiple columns of memory cells and multiple word lines connected to respective rows of memory cells, and a plurality of comparator circuits each connected to a corresponding column of the first RRAM crossbar array, wherein the comparator circuits are set to have incremental thresholds; wherein the control circuit is connected to the control bus and configured to: receive the computation instruction; parse the computation instruction into an instruction to perform a vector multiplication of vector A and vector B; setting the memory cells in the first RRAM crossbar array in the computation circuit such that states of memory cells of each column of the first RRAM crossbar array correspond to elements of vector B; setting the word lines of the first RRAM crossbar array according to elements of vector A; wherein the outputs of the comparator circuits are voltage signals corresponding to a first binary number in which a number of bits with a value 1 indicates a numerical result of multiplication of vector A and vector B.

18. The computing device according to claim 17, wherein the computation circuit further comprises a second RRAM crossbar array and a third RRAM crossbar array each having multiple rows and multiple columns of memory cells and multiple word lines connected to respective rows of memory cells, wherein outputs of the comparator circuits are connected to corresponding word lines of the second RRAM crossbar array, outputs of the second RRAM crossbar array are connected to corresponding words lines of the third RRAM crossbar array, wherein the second RRAM crossbar array being set up to convert the outputs of the comparator circuits into an output representing an intermediate binary number in which a location of a bit with a value 1 indicates the numerical result of multiplication of vector A and vector B; and the third RRAM crossbar array being set up to convert the output of the second RRAM crossbar array into an output representing a second binary number having a numerical value equal to the numerical result of multiplication of vector A and vector B.

19. The computing device according to claim 18, wherein the multiple rows and multiple columns of memory cells in the first RRAM crossbar array comprise N rows?N columns resistors, an input end of a resistor in each row at the first RRAM crossbar array is connected to a word line, an output end of a resistor in each column at the first RRAM crossbar array is connected to a bit line, N word lines of the first RRAM crossbar array are connected to the control circuit, and each of N bit lines of the first RRAM crossbar array are respectively connected to a comparator circuit of the plurality of comparator circuits; the first RRAM crossbar array generates N current signals on the N bit lines according to voltage signals input by the N word lines and a resistance value of a resistor at the first RRAM crossbar array, a voltage value of a voltage signal input by the j.sup.th word line in the N word lines is a voltage value corresponding to B.sub.j, a resistance value of a resistor in the j.sup.th row at the first RRAM crossbar array is a resistance value corresponding to A.sub.j, B.sub.j is the j.sup.th element of vector B, A.sub.j is the j.sup.th element of vector A, and a value of j ranges from 0 to N?1, wherein each of vector A and vector B indicates an N-dimensional vector, each elements of vector A and vector B indicates a value 1 or 0, and N is a positive integer not less than 2; the N comparator circuits respectively convert the N current signals into N voltage signals, and compare the N voltage signals with voltage thresholds respectively corresponding to the N comparator circuits, to output, from output ends of the N comparator circuits, the voltage signals corresponding to the first binary number, wherein the first binary number is an N-dimensional vector, first K elements of the first binary number are 1, remaining elements are 0, and K is the result of multiplication of vector A and vector B; the second RRAM crossbar array comprises a (2N?1) rows?N columns resistor array, an input end of a resistor in each row at the second RRAM crossbar array is connected to a word line, an output end of a resistor in each column at the second RRAM crossbar array is connected to a bit line, and each of word lines of the second RRAM crossbar array is connected to a output end of a comparator circuit in the first RRAM crossbar array; the second RRAM crossbar array receives the voltage signals corresponding to the first binary number from the output ends of the comparator circuits of the first RRAM crossbar array through the 2N?1 word lines, and performs a logic operation according to the voltage signals corresponding to the first binary number and a resistance value of a resistor at the second RRAM crossbar array: ${\stackrel{\_}{O}}_{2,j}=\{\begin{array}{c}{\stackrel{\_}{O}}_{1,j}+O_{1,j+1},j<N-1\\ {\stackrel{\_}{O}}_{1,j},j=N-1\end{array}$ to obtain voltage signals corresponding to an intermediate binary number, wherein ?.sub.1,j is a negation of a value corresponding to a voltage signal output by a comparator circuit connected to the j.sup.th bit line of the first RRAM crossbar array, O.sub.1,j+1 is a value corresponding to a voltage signal output by a comparator circuit connected to the (j+1).sup.th bit line of the first RRAM crossbar array, and ?.sub.2,j is a negation of a value corresponding to a voltage signal output by the j.sup.th bit line of the second RRAM crossbar array; the third RRAM crossbar array comprises an N rows?n columns resistor array, an input end of a resistor in each row at the third RRAM crossbar array is connected to a word line, an output end of a resistor in each column at the third RRAM crossbar array is connected to a bit line, and n is greater than or equal to a minimum quantity of bits required for expressing the integer N in binary; and the third RRAM crossbar array receives voltage signals corresponding to the intermediate binary number from N bit lines of the second RRAM crossbar array through N word lines of the third RRAM crossbar array, and encodes the intermediate binary number according to the voltage signals corresponding to the intermediate binary number and resistance values of resistors at the third RRAM crossbar array to obtain voltage signals corresponding to the second binary number.

20. The computing device according to claim 19, wherein the j.sup.th comparator circuit in the N comparator circuits comprises a resistor R.sub.s of a constant resistance value and a comparator, one end of the resistor R.sub.s is connected to the j.sup.th bit line in the N bit lines and the comparator, the other end of the resistor R.sub.s is grounded, a voltage threshold of the j.sup.th comparator circuit is V.sub.r*g.sub.on*R.sub.s*(2j+1)/2, V.sub.r indicates a voltage value corresponding to a value 1, and g.sub.on indicates a reciprocal of R.sub.on.

Description

BRIEF DESCRIPTION OF DRAWINGS

[0036] To describe the technical solutions in the embodiments of the present disclosure more clearly, the following briefly describes the accompanying drawings required for describing the embodiments. Apparently, the accompanying drawings in the following description show merely some embodiments of the present disclosure.

[0037] FIG. 1 is a schematic diagram of a physical structure of an RRAM crossbar;

[0038] FIG. 2 is a structural diagram of a conventional logic circuit based on an RRAM crossbar;

[0039] FIG. 3 is a curve of a resistance characteristic of a resistor in an RRAM crossbar;

[0040] FIG. 4 is a schematic structural diagram of a memory device according to an embodiment of the present disclosure;

[0041] FIG. 5 shows an example of a bus design manner of a control module 45;

[0042] FIG. 6 is a schematic structural diagram of a layer of an RRAM crossbar;

[0043] FIG. 7 is a circuit diagram of the first layer of RRAM crossbar in a three-layer RRAM crossbar used to implement Boolean matrix multiplication;

[0044] FIG. 8 is a circuit diagram of the second layer of RRAM crossbar in a three-layer RRAM crossbar used to implement Boolean matrix multiplication; and

[0045] FIG. 9 is a circuit diagram of the third layer of RRAM crossbar in a three-layer RRAM crossbar used to implement Boolean matrix multiplication.

DESCRIPTION OF EMBODIMENTS

[0046] FIG. 4 is a schematic structural diagram of a memory device according to an embodiment of the present disclosure. From FIG. 4, that the memory device 40 is in an H-tree structure on the whole. In this structure, a storage module 43 (or referred to as a data module, a data array, or the like) is paired with a logic module 44 (or referred to as a logic circuit, a logic operation circuit, an in-memory logic, or the like).

[0047] In an embodiment, both the storage module 43 and the logic module 44 may be RRAM crossbars. Further, the storage module 43 may be a single-layer RRAM crossbar, and the logic module 44 may be a multilayer RRAM crossbar. In this disclosure, a type of the storage module 43 is not specifically limited in this embodiment of the present disclosure, and another type of storage medium may be used. In addition, even if both the storage module 43 and the logic module 44 are RRAM crossbars, a quantity of layers of the RRAM crossbar is not specifically limited in this embodiment of the present disclosure. For example, the storage module 43 may be designed as a multilayer RRAM crossbar, and the logic module 44 may be designed as a single-layer logic module 44 (a single-layer RRAM crossbar can also implement a simple logic operation).

[0048] Still referring to FIG. 4, the memory device 40 mainly includes four parts: a block decoder 41, a storage module 43, a logic module 44, and a control module 45. The control module 45 may be a CMOS-based control module. The storage module 43, the logic module 44, and the control module 45 may be included in a memory unit 42 (or referred to as a data/logic pair).

[0049] In FIG. 4, the control module 45 is separately connected to the storage module 43, the logic module 44, and the block decoder 41, and is connected to the processor 47 (such as a CPU) through the block decoder 41. The control module 45 receives and parses an instruction of the processor 47, and may further be responsible for data exchange or transmission between the storage module 43 and the logic module 44. The block decoder 41 may transfer the instruction delivered by the processor 47 to a control module 45 of a memory unit 42 corresponding to the instruction. In addition, in an embodiment, an address search function of the memory unit 42 may be integrated in the block decoder 41, and remaining control functions are all integrated in the control module 45.

[0050] From the foregoing description, that the control module 45 may be connected to the block decoder 41, but the block decoder 41 may be responsible only for transferring the instruction delivered by the processor 47 to the control module 45 of the corresponding memory unit 42. Therefore, from another perspective, the control module 45 may be considered as a main body for receiving and parsing the instruction of the processor. Using FIG. 5 as an example, the following describes, in detail, an internal structure of the control module and how the control module processes an instruction.

[0051] FIG. 5 shows an example of a bus design manner of a control module. The control module 45 may include an instruction queue 451, an instruction decoder 452, an address decoder 453, and an SRAM array 454, and a connection manner therebetween may be shown in FIG. 5. Considering that an operating frequency of the memory device may be lower than an operating frequency of the processor, the instruction queue 451 may be disposed in the control module 45 to buffer the instruction delivered by the processor 47, so as to reduce a wait time of the processor 47. The instruction decoder 452 parses a to-be-executed instruction (which may be, for example, an instruction of data reading, data storage, or memory computing, and is described in detail in the following), and then performs a corresponding operation. The address decoder 453 may decompose address information in the instruction into row/column information of the storage module 43 or row/column information of the logic module 44. The SRAM array 454 may be configured to temporarily store data that is read from the storage module 43 or the logic module 44, and according to the instruction, write the data into the storage module 43 or the logic module 44, or transfer the data back to the external processor 47.

[0052] A format and a type of the instruction delivered by the processor 47 to the memory device 40 are not specifically limited in this embodiment of the present disclosure. For example, the type of the instruction delivered by the processor 47 to the memory device 40 or a type of an instruction that needs to be parsed by the control module 45 may include 4 types of instructions listed in Table 1.

TABLE-US-00001 TABLE 1 Types and parameters of instructions needing to be parsed by a control module 45 Application requiring this Instruction Operand 1 Operand 2 Operation operation SW Data Address Store data in an address Write (ordinary write) in a (Store Word) Address 1 Address 2 Read data from the storage module, write (logic address 1 and store the configuration) in a logic module, data into the address 2 data input configuration in a logic module, write-back after memory computing LW Address Read data from an Ordinary read (Load Word) address to a processor ST Memory Turn on all row/column Performing memory computing (Start) unit serial switches of a logic number module in a memory unit corresponding to this serial number WT Wait for a completion Preventing an instruction in an (Wait) signal of memory instruction queue from being computing of a logic operated during memory module computing

[0053] Using a memory computing process as an example, first, logic configuration is performed on the logic module 44, that is, a resistance value of a resistor in the logic module 44 is configured so that the logic module 44 can implement particular operation logic. Then an input signal is provided to the logic module 44. That is, data requiring a logic operation is input into the logic module 44. Then, memory computing may be performed in the logic module 44 according to the input signal and configured operation logic. The following describes in detail a memory computing process with reference to the instructions in Table 1.

[0054] When memory computing is needed, the processor 47 may deliver the following instructions to the memory device 40.

[0055] Instruction 1: an SW instruction, which is used to write data in the processor 47 or the storage module 43 into the logic module 44 to configure a resistance value of the RRAM in the logic module 44, so that the logic module can implement particular logic such as summation, exclusive OR, and multiplication.

[0056] Instruction 2: an SW instruction, which is used to write data in the processor 47 or the storage module 43 into an input column (a voltage V.sub.w1.sup.i input by a word line (word line) in FIG. 6) of the logic module 44. A particular logic operation on input data can be implemented in the logic module based on previously configured operation logic. For example, the logic module 44 implements a+b summation logic. b may be stored into the logic module using the instruction 1, then a is input using the instruction 2, and then a and b are summed.

[0057] Instruction 3: an ST instruction, which is used to turn on all row/column switches of the logic module 44, so that a current flows through all rows/columns of the logic module 44.

[0058] Instruction 4: a WT instruction. When a complex logic operation is implemented using an RRAM crossbar, multiple layers of RRAM crossbars are needed in the logic module 44. In this case, it takes a time to complete computing of the RRAM crossbars. Therefore, the ST instruction may be used to instruct the control module 45 to wait for completion of memory computing of the logic module 44, and then execute a subsequent instruction.

[0059] Instruction 5: an SW instruction, which may be used to: after memory computing is completed, write data obtained by means of operation by the logic module 44 back into the storage module 43.

[0060] It should be noted that for particular logic, logic configuration needs to be performed on the logic module 44 only once, and the instruction 1 may not be necessarily executed each time before memory computing is performed. That is, a same logic operation can be implemented for different data by changing data in an input column of the logic module 44.

[0061] A process in which the control module 45 performs memory computing according to the instruction is described above in detail. It should be noted that the control module 45 may also perform ordinary data read/write according to an instruction. This process is similar to that in the prior art, and is not described herein in detail. Using FIG. 6 as an example, the following briefly describes a logic operation process of the logic module 44 based on an RRAM crossbar.

[0062] In FIG. 6, a comparator circuit is disposed at the bottom of each bit line (bit line). In practice, the comparator circuit may be a sense amplifier (SA). The SA includes a constant resistor R.sub.s (for example, R.sub.s<R.sub.on<R.sub.off) with a relatively small resistance value, and an operational amplifier, so as to convert a current signal in a column (that is, a bit line) into a voltage, and compare the voltage with a voltage threshold at the first layer of RRAM crossbar to obtain a computing result of this column. Computing formulas for each column are as follows:

[00003]$\begin{array}{cc}{V}_{\mathrm{bl}}^j=R_s.Math.\underset{i=1}{\overset{m}{.Math.}}.Math.g_{\mathrm{ij}}.Math.V_{\mathrm{wl}}^i& \left(1\right)\\ V_{\mathrm{out}}^j=\{\begin{array}{cc}1,& V_{\mathrm{bl}}^j>V_{\mathrm{th}}^j\\ 0,& V_{\mathrm{bl}}^j?V_{\mathrm{th}}^j\end{array}& \left(2\right)\end{array}$

[0063] In a formula (1), V.sub.wl.sup.r indicates a voltage of a word line of the i.sup.th row, V.sub.bl.sup.j indicates a voltage of a bit line (bit line) of the j.sup.th column, g.sub.ij indicates an admittance (a reciprocal of R.sub.ij) corresponding to a resistor R.sub.lj , V.sub.bl.sup.j indicates a voltage threshold corresponding to the j.sup.th column, and V.sub.out .sup.j indicates an output voltage of the j.sup.th column. In addition, FIG. 6 merely shows a circuit structure of a single-layer RRAM crossbar. If the logic module 44 includes a multilayer RRAM crossbar, a column output V.sub.out.sup.j of a layer may be used as a row input of a next layer. All layers may have a same structure or different structures. A column output V.sub.out.sup.j of a last layer may be used as a final output of the logic module 44.

[0064] In order to use the RRAM crossbar to implement a particular logic operation (or function), the following steps may be performed to configure the resistance value of the resistor in the RRAM crossbar and a voltage threshold of each column (that is, the resistance value in the RRAM crossbar and the voltage threshold of each column determine logic actually implemented by the RRAM crossbar):

[0065] Step 1: In software (such as MatLab and Octave), determine a quantity of layers of the RRAM crossbar required for implementing the particular logic, and a size of rows and columns of each layer.

[0066] Step 2: Compute a resistance value of a resistor at each layer of RRAM crossbar, and a voltage threshold of the comparator circuit.

[0067] Step 3: Use an instruction to store the computed resistance value of the resistor in the RRAM crossbar into a corresponding resistor, and set the voltage threshold of the comparator circuit.

[0068] Step 4: Implement the particular logic computing using hardware (a circuit of the logic module 44).

[0069] Disadvantages of the RRAM crossbar based on an analog signal are described above in detail with reference to FIG. 2 and FIG. 3, for example, excessive AD and DA conversion operations, and errors existing in a resistance value configuration process. To overcome the disadvantages, the following describes, with reference to specific embodiments, specific implementations of an RRAM crossbar based on a digital signal.

[0070] First, it may be learned, from (b) in FIG. 3, that in comparison with an intermediate state, reliability is higher if the resistor in the RRAM crossbar is set to R.sub.on or R.sub.off (a process of configuring the resistor in the RRAM crossbar may be referred to as RRAM programming). That is, if only the resistor in the RRAM crossbar is set to R.sub.on or R.sub.off, resistor configuration errors can be reduced, and logic operation reliability can be improved. Therefore, the resistor in the RRAM crossbar in this embodiment of the present disclosure is either set to an R.sub.on state or set to an R.sub.off state. R.sub.off may indicate a Boolean value 0 (or digit 0), and R.sub.on may indicate a Boolean value 1 (or digit 1). Then a row input interface of the RRAM crossbar may be designed as a pure digital interface, without a need for AD conversion (it may be learned, from FIG. 6, that a row input of the RRAM crossbar is a voltage signal, provided that the input voltage signal includes a high level and a low level, where the high level corresponds to the Boolean value 1, and the low level corresponds to the Boolean value 0; however, voltage values of the high level and the low level are not specifically limited in this embodiment of the present disclosure). By means of the foregoing settings, the logic module based on an analog signal shown in FIG. 2 may be converted into a logic module based on a digital signal.

[0071] Referring to FIG. 6, a resistor R.sub.s in an SA of each column may be a small resistor with a constant resistance value, and R.sub.off.sup.>>R.sub.on.sup.>>R.sub.s may be satisfied for R.sub.off, R.sub.on, and R.sub.S. A comparator circuit (using an SA as an example in the figure) is connected to an end of each column. Referring to a formula (2), the SA compares a voltage of this column with a voltage threshold of the column to obtain an output voltage of this column. The output voltage is either a voltage (low level) corresponding to the Boolean value 0 or a voltage (high level) corresponding to the Boolean value 1.

[0072] It should be understood that particular logic can be implemented by configuring the resistor in the RRAM crossbar and the voltage threshold in each column of the word line. However, a type of the logic is not specifically limited in this embodiment of the present disclosure. Using Boolean matrix (elements in the matrix are all 0 and 1) multiplication as an example, the following describes in detail how to configure the resistance value of the resistor in the RRAM crossbar and configure the voltage threshold of the word line in the RRAM crossbar to implement the Boolean matrix multiplication.

[0073] For ease of understanding, a computing process of matrix multiplication Y=?X is described first.

[0074] General forms and vector forms of matrices X and (I) are as follows:

[00004]$\begin{array}{cc}\begin{array}{c}?=\left[\begin{array}{cccc}{?}_{11}& {?}_{12}& {?}_{13}& K\\ {?}_{21}& {?}_{22}& {?}_{23}& K\\ {?}_{31}& {?}_{32}& {?}_{33}& K\\ M& M& M& O\end{array}\right]=\left[\begin{array}{c}{?}_1\\ {?}_2\\ {?}_3\\ M\end{array}\right]\\ X=\left[\begin{array}{cccc}{x}_{11}& x_{12}& x_{13}& K\\ x_{21}& x_{22}& x_{23}& K\\ x_{31}& x_{32}& x_{33}& K\\ M& M& M& O\end{array}\right]=\left[X_1.Math..Math.X_2.Math..Math.X_3.Math..Math.K\right]\end{array}& \left(3\right)\end{array}$

[0075] A product of the matrix ? and the matrix X may alternatively be considered as a product of a column vector

[00005]$\left[\begin{array}{c}{?}_1\\ {?}_2\\ {?}_3\\ M\end{array}\right]$

and a row vector [X.sub.1 X.sub.2 X.sub.3 K]. For details, refer to a formula (4):

[00006]$\begin{array}{cc}Y=\mathrm{?X}=\left[\begin{array}{c}{?}_1\\ {?}_2\\ {?}_3\\ M\end{array}\right]?\left[X_1.Math..Math.X_2.Math..Math.X_3.Math..Math.K\right]=\left[\begin{array}{cccc}\left({?}_1.Math.X_1\right)& \left({?}_1.Math.X_2\right)& \left({?}_1.Math.X_3\right)& L\\ \left({?}_2.Math.X_1\right)& \left({?}_2.Math.X_2\right)& \left({?}_2.Math.X_3\right)& K\\ \left({?}_3.Math.X_1\right)& \left({?}_3.Math.X_2\right)& \left({?}_3.Math.X_3\right)& K\\ M& M& M& O\end{array}\right]& \left(4\right)\end{array}$

[0076] It may be learned, from formulas (3) and (4), that each element of the matrix Y is a result of point multiplication of a row of the matrix ? and a column of the matrix X (that is, computing an inner product).

[0077] In this embodiment of the present disclosure, first, a logic module is provided. The logic module may implement, based on a multilayer RRAM crossbar, point multiplication operation logic of a Boolean vector (the Boolean vector is a vector whose elements are 0 or 1). Based on this, a memory device that can implement a Boolean matrix (the Boolean matrix is a matrix whose elements are 0 or 1) multiplication operation is further provided in this embodiment of the present disclosure. The memory device may include one or more logic modules that can implement Boolean vector multiplication. Because a Boolean matrix multiplication operation may be decomposed into multiple point multiplication operations of Boolean vectors, the memory device may decompose the Boolean matrix multiplication operation into multiple point multiplication operations of Boolean vectors, and then distribute the multiple point multiplication operations of Boolean vectors to the one or more logic modules. The one or more logic modules jointly implement the Boolean matrix multiplication operation.

[0078] The following describes, in detail, a structure and functions of a multilayer RRAM crossbar for implementing a Boolean vector point multiplication operation using a Boolean vector [?.sub.0,j,?.sub.1,j . . . ?.sub.N?1,j] (which may be considered as a vector formed by elements of any row in the Boolean matrix ?, and corresponds to the Boolean vector A mentioned above) and a Boolean vector [x.sub.i,0,x.sub.i,1 . . . x.sub.i,N+1] (which may be considered as a Boolean vector formed by elements of any column in the matrix X, and corresponds to the Boolean vector B mentioned above) as an example.

[0079] The multilayer RRAM crossbar may include three layers of RRAM crossbars. A circuit shown in FIG. 7 may be used at the first layer of RRAM crossbar in the three-layer RRAM crossbar. In FIG. 7, the first layer of RRAM crossbar includes an N?N resistor array. N resistors in each column of the N?N resistor array respectively indicate the Boolean vector [?.sub.0,j,?.sub.1,j . . . ?.sub.N?1,j]. For example, it is assumed that N is 8, and 8 elements of [?.sub.0,j,?.sub.1,j . . . ?.sub.N?1,j] are 10101010 sequentially. Therefore, resistance values of the first column in the N?N resistor array of the first layer of RRAM crossbar are R.sub.on (corresponding to 1), R.sub.off (corresponding to 0), R.sub.on, R.sub.off, R.sub.on, R.sub.off, R.sub.on, and R.sub.off sequentially, and a resistance configuration of each column in the N?N resistor array is the same as a resistance configuration of the first column.

[0080] A comparator circuit is disposed at the bottom of each column (bit line) of the N?N resistor array (an SA is used as an example of the comparator circuit in the following). The comparator circuit may include a constant resistor R.sub.s with a relatively small resistance value and a comparator. A function of the comparator circuit is converting a current signal in each column into a voltage signal, and comparing the voltage signal with a voltage threshold V.sup.th1 of the column, so as to determine whether a computing result of this column is 0 or 1. The voltage threshold of each column in the N?N resistor array may be set to V.sub.r*g.sub.on*R.sub.s*(2j+1)/2 sequentially, where j is a positive integer ranging from 0 to N?1. V.sub.r indicates an actual voltage (that is, a high level) when an input of X is 1, go, indicates an admittance corresponding to a resistor R.sub.on, and R.sub.s indicates a resistance value of a sampling resistor. It may be learned, from this formula, that thresholds of columns in the N?N resistor array increase sequentially and are step-shaped on the whole (as shown in FIG. 7).

[0081] The following describes logic functions that can be implemented by the first layer of RRAM crossbar.

[0082] A voltage signal corresponding to the Boolean vector [x.sub.i,0,x.sub.i,1 . . . x.sub.i,N+1] is input into the first layer of RRAM crossbar (that is, a high level is input into a word line corresponding to an element 1 in the Boolean vector [x.sub.i,0,x.sub.i,1 . . . x.sub.i,N+1], and a low level is input into a word line corresponding to an element 0 in the Boolean vector [x.sub.i,0,x.sub.i,1 . . . x.sub.i,N+1]. As described above, a resistance value of a resistor in each column at the first layer of RRAM crossbar is a resistance value corresponding to the Boolean vector [?.sub.0,j,?.sub.1,j . . . ?.sub.N?1,j]. When all row/column switches of the first layer of RRAM crossbar are turned on, point multiplication logic of the Boolean vector [?.sub.0,j,?.sub.1,j . . . ?.sub.N?1,j] and the Boolean vector [x.sub.i,0,x.sub.i,1 . . . x.sub.i,N+1] is implemented on each bit line of the first layer of RRAM crossbar based on a relationship between a voltage and a current. A result of the point multiplication logic may be represented by a current on each word line. Then, at an output end of the bit line, an SA connected to the word line of the first layer of RRAM crossbar outputs a voltage signal corresponding to a first computing result by setting the step-shaped voltage thresholds described above. The first computing result is an N-dimensional Boolean vector, first K elements of the first computing result is 1, remaining elements are 0, and K is a result of a point multiplication operation on the Boolean vector [?.sub.0,j,?.sub.1,j . . . ?.sub.N?1,j] and the Boolean vector [x.sub.i,0,x.sub.i,1 . . . x.sub.i,N+1]. For example, it is assumed that N=8 and K=3. By means of a logic operation of the first layer of RRAM crossbar, an output O.sub.1,j (0?j?N?1) result of the first layer of RRAM crossbar is 11100000. It may be understood as follows: all comparison results of SAs in columns 0 to 3 are that column voltages are greater than voltage thresholds, and all comparison results of SAs in columns 4 to 7 are that column voltages are less than voltage thresholds.

[0083] Next, a logic task of the second layer of RRAM crossbar and the third layer of RRAM crossbar in the three-layer RRAM crossbar is converting an output result of the first layer of RRAM crossbar into a binary representation of K. Still using K=3 as an example, the output result of the first layer of RRAM crossbar is 11100000, and the logic task of the second layer of RRAM crossbar and the third layer of RRAM crossbar is converting 11100000 into 11, that is, 3 in binary. The following further describes structures and logic functions of the second layer of RRAM crossbar and the third layer of RRAM crossbar (herein, the second layer of RRAM crossbar and the third layer of RRAM crossbar jointly complete the foregoing logic task, but this is not limited in this embodiment of the present disclosure; and the foregoing logic task may alternatively be implemented by one layer of RRAM crossbar or more than three layers of RRAM crossbars).

[0084] To implement the foregoing logic task, a structure shown in FIG. 8 may be used for the second layer of RRAM crossbar. In FIG. 8, the second layer of RRAM crossbar includes a (2N?1)?N resistor array. Resistance values of the (2j).sup.th and (2j+1).sup.th resistors in the j.sup.th column of resistors of the second layer of RRAM crossbar are R.sub.on, and resistance values of remaining resistors are R.sub.off, where 0?j?N?2. A resistance value of the (2N?1).sup.th resistor in the (N?1).sup.th column of resistors of the second layer of RRAM crossbar is R.sub.on, and resistance values of remaining resistors are R.sub.off. 2N?1 word lines of the second layer of RRAM crossbar may be connected to the bit line output end O.sub.1,j of the first layer of RRAM crossbar according to a connection relationship shown in FIG. 8. It should be noted that output ends of some bit lines of the first layer of RRAM crossbar require a negation operation before being connected to word lines of the second layer of RRAM crossbar. Referring to ?.sub.1,j shown in FIG. 7, such a negation operation may be implemented by connecting to a device such as a comparator or a phase inverter. This is not specifically limited in this embodiment of the present disclosure. An end of each bit line at the second layer of RRAM crossbar is connected to a comparator circuit. A voltage threshold V.sub.th2 of the comparator circuit may be set to V.sub.r*g.sub.on*R.sub.s/2. In addition, a positive pole and a negative pole of a comparator in an operation circuit need to be swapped (that is, the voltage threshold V.sub.th2 is set at an in-phase input end of the comparator, and a reverse-phase input end is connected to the resistor R.sub.s and the bit line) to obtain an output O.sub.2,j of the second layer, where 0?j?N?1.

[0085] A relationship between the output O.sub.2,j of the second layer of RRAM crossbar and the output of the first layer of RRAM crossbar may be expressed by a formula (5). That is, the formula (5) is a logic function to be implemented by the second layer of the RRAM crossbar.

[00007]$\begin{array}{cc}{\stackrel{\_}{O}}_{2,j}=\{\begin{array}{c}{\stackrel{\_}{O}}_{1,j}+O_{1,j+1},j<N-1\\ {\stackrel{\_}{O}}_{1,j},j=N-1\end{array}& \left(5\right)\end{array}$

[0086] Logic expressed by the formula (5) is actually exclusive-OR logic. That is, an exclusive-OR operation is performed pairwise on the first computing result output by the first layer of RRAM crossbar to obtain an intermediate binary number. The intermediate binary number is an N-dimensional vector. The (K?1).sup.th element of the N-dimensional vector is 1, and remaining elements are 0. K is a result of a point multiplication operation on the Boolean vector [?.sub.0,j,?.sub.1,j . . . ?.sub.N?1,j] and the Boolean vector [x.sub.i,0,x.sub.i,1 . . . x.sub.i,N+1]. That an output result of the first layer of RRAM crossbar is 11100000 is used as an example. An obtained result is 00100000 after the logic operation of the second layer is performed. However, it should be noted that a structure of the RRAM crossbar for implementing the exclusive-OR logic is not specifically limited in this embodiment of the present disclosure, and FIG. 8 is merely an example. In practice, the exclusive-OR logic may alternatively be implemented by configuring resistance values of resistors and voltage thresholds in another manner.

[0087] The second layer of RRAM crossbar transfers the voltage signal corresponding to the intermediate binary number to the word lines of the second layer of RRAM crossbar. The output end O.sub.2,j of the j.sup.th bit line of the second layer of RRAM crossbar is connected to the input end of the j.sup.th word line of the third layer of RRAM crossbar. A logic circuit of the third layer of RRAM crossbar is shown in FIG. 9. The third layer of RRAM crossbar includes an N?n resistor array, where n is greater than or equal to a minimum quantity of bits required for expressing the integer N in binary (for example, N=8, a binary representation of 8 is 1000, that is, the binary representation of 8 requires 4 bits, and therefore, n is greater than or equal to 4). Resistance values of N rows of resistors are set so that the resistors indicate binary 1 to N sequentially from top to bottom. In this way, when the voltage signal corresponding to the intermediate operation result output by the second layer of RRAM crossbar is used as an input voltage signal of the third layer of RRAM crossbar, because the (K?1).sup.th element of the intermediate operation result is a Boolean value 1 and remaining elements are a Boolean value 0, the (K?1).sup.th bit line of the third layer of RRAM crossbar inputs a voltage signal (high level) corresponding to the Boolean value 1, and remaining bit lines each input a voltage signal (low level) corresponding to the Boolean value 0. From a logic perspective, by means of such a configuration, an operation result (corresponding to the second operation result described above) finally output by the third layer of RRAM crossbar is a binary representation of K. That is, a binary representation of an integer corresponding to resistors in the (K?1).sup.th row of the third layer of RRAM crossbar (it may be learned, as described above, that the resistors in the (K?1).sup.th row correspond to the binary representation of the integer K) is selected as a final operation result. An output of the third layer of RRAM crossbar is a voltage signal corresponding to the final operation result.

[0088] Still using N=8 and K=3 as an example, a logic output of the second layer of RRAM crossbar is 00100000. A logic correspondence between an input and an output of the third layer of RRAM crossbar is shown in the following table.

TABLE-US-00002 TABLE 2 Input and output comparison table of a third layer of RRAM crossbar Logic input of a third Row serial Logic output of a third layer of RRAM crossbar number layer of RRAM crossbar 00000000 None 10000000 0 0001 01000000 1 0010 00100000 2 0011 00010000 3 0100 00001000 4 0101 00000100 5 0110 00000010 6 0111 00000001 7 1000

[0089] It may be learned, from the foregoing table, that an output corresponding to 00100000 is 0011, that is, a binary representation of 3.

[0090] It should be noted that if an input matrix is a non-Boolean matrix (for example, the input matrix is a positive real matrix), the matrix may be decomposed into a linear combination of multiple Boolean matrices by means of linear algebra. Then, operations are performed on the multiple Boolean matrices in the foregoing manner, and then results of the operations on the multiple Boolean matrices are linearly combined to obtain a matrix multiplication result corresponding to the real matrix. Details are not described again in this embodiment of the present disclosure.

[0091] A person of ordinary skill in the art may be aware that, in combination with the examples described in the embodiments disclosed in this specification, units and algorithm steps may be implemented by electronic hardware or a combination of computer software and electronic hardware. Whether the functions are performed by hardware or software depends on particular applications and design constraint conditions of the technical solutions. A person skilled in the art may use different methods to implement the described functions for each particular application, but it should not be considered that the implementation goes beyond the scope of the present disclosure. The foregoing descriptions are merely specific embodiments of the present disclosure, but are not intended to limit the protection scope of the present disclosure.