POWER AMPLIFIER WITH LARGE OUTPUT POWER

Abstract

A power amplifier has a number n of power cells A.sub.i, a number n of output transmission lines TL.sub.1i for combining output powers from the power cells, and a number n of impedance transformation network ITN.sub.i, where i=1, . . . n. The number n of output transmission lines are connected in series. The output terminal of each power cells is connected to its output transmission line via its impedance transformation network. Each impedance transformation network is an upward impedance transformation network for transforming an output impedance of each power cell at the input terminal of the impedance transformation network into a higher impedance at the output terminal of the impedance transformation network. A number n of input transmission lines TL.sub.0i (i=1, 2 . . . n)=connected in series. The input terminal of the i-th power cell is connected to the second terminal of the i-th transmission line via a capacitor, where i=1, . . . n.

Claims

1. A power amplifier comprising: a number n of power cells A.sub.i, where i=1, . . . n, each power cell has an input terminal and an output terminal; a number n of output transmission lines TL.sub.1i for combining output powers from the power cells, where i=1, . . . n, each output transmission line having a first terminal and a second terminal, the second terminal of the i-th transmission line is connected to the first terminal of the (i+1)-th transmission line such that the number n of output transmission lines are connected in series; and a number n of impedance transformation network ITN.sub.i, where i=1, . . . n, each impedance transformation network has an input terminal and output terminal; the output terminal of i-th power cell is connected to the input terminal of the i-th impedance transformation network and the output terminal of the i-th impedance transformation network is connected to the first terminal of the i-th output transmission line; and each impedance transformation network is an upward impedance transformation network for transforming an output impedance of each power cell at the input terminal of the impedance transformation network into a higher impedance at the output terminal of the impedance transformation network.

2. The power amplifier according to claim 1, wherein each power cell comprises a common-source configured transistor, and wherein a gate of each transistor is connected to the input terminal of the power cell and a drain of each transistor is connected to the output terminal of the power cell, a source of each transistor is connected to a ground.

3. The power amplifier according to claim 1, wherein each impedance transformation network is a tapped capacitor impedance transformation network comprising a first and second capacitors connected in series, where a second terminal of the first capacitor is connected to a first terminal of the second capacitor to form a tapped node, and wherein the input terminal of the impedance transformation network is connected to the tapped node, the output terminal of the impedance transformation network is connected to a first terminal of the first capacitor, a second terminal of the second capacitor is connected to a ground.

4. The power amplifier according to claim 3, wherein parasitic capacitance of a transistor in each power cell is a part of the tapped capacitor impedance transformation network.

5. The power amplifier according to claim 1, wherein each impedance transformation network is a tapped inductor impedance transformation network comprising a first and second inductors connected in series, where a second terminal of the first inductor is connected to a first terminal of the second inductor to form a tapped node, and wherein the input terminal of the impedance transformation network is connected to the tapped node, the output terminal of the impedance transformation network is connected to a first terminal of the first inductor, a second terminal of the second inductor is connected to a ground.

6. The power amplifier according to claim 1, wherein each impedance transformation network comprises a T-impedance matching network comprising at least three passive components connected in T-shape.

7. The power amplifier according to claim 1, wherein each impedance transformation network comprises a π-impedance matching network comprising at least three passive components connected in π-shape.

8. The power amplifier according to claim 1, wherein each impedance transformation network comprises a transformer.

9. The power amplifier according to claim 1, wherein the output transmission lines have different widths and lengths.

10. The power amplifier according to claim 1, wherein each of the output transmission lines has the same width and length.

11. The power amplifier according to claim 1, further comprising a number n of input transmission lines TL.sub.01 (i=1, 2 . . . n) connected in series, each input transmission line has a first terminal and a second terminal, where the second terminal of the i-th transmission line is connected to the first terminal of the (i+1)-th transmission line, and the input terminal of the i-th power cell is connected to the second terminal of the i-th transmission line via a capacitor, where i=1, . . . n. and an input port of the whole PA is connected with the first terminal of the first transmission line.

12. An electronic device comprising a power amplifier, the power amplifier comprising: a number n of power cells A.sub.i, where i=1, . . . n, each power cell has an input terminal and an output terminal; a number n of output transmission lines TL.sub.1i for combining output powers from the power cells, where i=1, . . . n, each output transmission line having a first terminal and a second terminal, the second terminal of the i-th transmission line is connected to the first terminal of the (i+1)-th transmission line such that the number n of output transmission lines are connected in series; and a number n of impedance transformation network ITN.sub.i, where i=1, . . . n, each impedance transformation network has an input terminal and output terminal; the output terminal of i-th power cell is connected to the input terminal of the i-th impedance transformation network and the output terminal of the i-th impedance transformation network is connected to the first terminal of the i-th output transmission line; and each impedance transformation network is an upward impedance transformation network for transforming an output impedance of each power cell at the input terminal of the impedance transformation network into a higher impedance at the output terminal of the impedance transformation network.

13. The electronic device according to claim 12, wherein the electronic device is one of a transmitter, a transceiver, a base station, a mobile device, and a user equipment in a wireless communication system.

14. The electronic device according to claim 12, wherein each power cell comprises a common-source configured transistor, and wherein a gate of each transistor is connected to the input terminal of the power cell and a drain of each transistor is connected to the output terminal of the power cell, a source of each transistor is connected to a ground.

15. The electronic device according to claim 12, wherein each impedance transformation network is a tapped capacitor impedance transformation network comprising a first and second capacitors connected in series, where a second terminal of the first capacitor is connected to a first terminal of the second capacitor to form a tapped node, and wherein the input terminal of the impedance transformation network is connected to the tapped node, the output terminal of the impedance transformation network is connected to a first terminal of the first capacitor, a second terminal of the second capacitor is connected to a ground.

16. The electronic device according to claim 15, wherein parasitic capacitance of a transistor in each power cell is a part of the tapped capacitor impedance transformation network.

17. The electronic device according to claim 12, wherein each impedance transformation network is a tapped inductor impedance transformation network comprising a first and second inductors connected in series, where a second terminal of the first inductor is connected to a first terminal of the second inductor to form a tapped node, and wherein the input terminal of the impedance transformation network is connected to the tapped node, the output terminal of the impedance transformation network is connected to a first terminal of the first inductor, a second terminal of the second inductor is connected to a ground.

18. The electronic device according to claim 12, wherein each impedance transformation network comprises a T-impedance matching network comprising at least three passive components connected in T-shape.

19. The electronic device according to claim 12, wherein each impedance transformation network comprises a π-impedance matching network comprising at least three passive components connected in π-shape.

20. The electronic device according to claim 12, wherein each impedance transformation network comprises a transformer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The various aspects of embodiments disclosed herein, including particular features and advantages thereof, will be readily understood from the following detailed description and the accompanying drawings, in which:

[0034] FIG. 1 is a schematic block diagram illustrating a 2-way Wilkinson power combiner;

[0035] FIGS. 2 (a)-(c) are schematic block diagrams illustrating power combining by transformers;

[0036] FIG. 3 is a schematic block diagram illustrating an equivalent circuit of a distributed amplifier based on lumped-element artificial transmission lines;

[0037] FIG. 4 is a schematic block diagram illustrating a band-pass distributed amplifier;

[0038] FIG. 5 is a schematic block diagram illustrating a nonuniform distributed power amplifier;

[0039] FIG. 6 is a schematic block diagram illustrating a distributed efficient power amplifier (DEPA) architecture;

[0040] FIG. 7 is a schematic block diagram illustrating power amplifier according to embodiments herein;

[0041] FIGS. 8 (a) and (b) are schematic block diagrams illustrating examples of impedance transformation network (ITN) according to embodiments herein;

[0042] FIGS. 9 (a)-(d) are equivalent circuits of a transistor with a tapped capacitor impedance transformation network;

[0043] FIG. 10 is a schematic block diagram illustrating one example power amplifier according to embodiments herein;

[0044] FIG. 11 is a diagram showing gain of the PA according to embodiments herein;

[0045] FIG. 12 is a diagram showing efficiency of the PA according to embodiments herein; and

[0046] FIG. 13 is a block diagram showing an electronic device in which the power amplifier according to embodiments herein may be implemented.

DETAILED DESCRIPTION

[0047] Throughout the following description similar reference numerals have been used to denote similar features, such as elements, units, modules, circuits, nodes, parts, items or the like, when applicable.

[0048] FIG. 7 shows a schematic of a proposed power amplifier 700 with upward impedance transformation networks according to embodiments herein.

[0049] The power amplifier 700 comprises a number n of power cells Ai, where i=1, . . . n. Each power cell has an input terminal Ain and an output terminal Aout.

[0050] The power amplifier 700 further comprises a number n of output transmission lines TL.sub.1i for combining output powers from the power cells, where i=1, . . . n. Each output transmission line has a first terminal T1 and a second terminal T2. The second terminal of the i-th transmission line TL.sub.1i is connected to the first terminal of the (i+1)-th transmission line TL.sub.1(i+1) such that the number n of output transmission lines are connected in series. For example, the second terminal T2 of the first transmission line TL.sub.11 is connected to the first terminal T1 of the second transmission line TL.sub.12.

[0051] The power amplifier 700 further comprises a number n of impedance transformation network ITN.sub.i, where i=1, . . . n. Each impedance transformation network has an input terminal ITNin and an output terminal INTout. The output terminal Aout of i-th power cell is connected to the input terminal ITNin of the i-th impedance transformation network and the output terminal ITNout of the i-th impedance transformation network is connected to the first terminal T1 of the i-th output transmission line. For example, the output terminal of the second power cell A.sub.2 is connected to the input terminal of the second impedance transformation network and the output terminal of the second impedance transformation network is connected to the first terminal of the second output transmission line TL.sub.12.

[0052] Each impedance transformation network is an upward impedance transformation network for transforming an output impedance of each power cell at the input terminal of the impedance transformation network into a higher impedance at the output terminal of the impedance transformation network.

[0053] Each of the output transmission lines may have the same width and length or may have different widths and lengths.

[0054] The power amplifier may further comprise a number n of input transmission lines TL.sub.0i connected in series. Each input transmission line has a first terminal and a second terminal, where the second terminal of the i-th input transmission line is connected to the first terminal of the (i+1)-th input transmission line, and wherein the input terminal of the i-th power cell is connected to the second terminal of the i-th transmission line via a capacitor, where i=1, . . . n. An input port Pin of the whole PA is connected with the first terminal of the first transmission line TL.sub.01.

[0055] Each impedance transformation network INT may be a tapped capacitor impedance transformation network or a tapped inductor impedance transformation network, as shown in FIGS. 8 (a) and (b). As shown in FIG. 8 (a), the tapped capacitor impedance transformation network may comprise a first and second capacitors C.sub.1, C.sub.2 connected in series, where a second terminal of the first capacitor is connected to a first terminal of the second capacitor to form a tapped node. The input terminal of the impedance transformation network INTin is connected to the tapped node, the output terminal of the impedance transformation network INTout is connected to a first terminal of the first capacitor C.sub.1, a second terminal of the second capacitor C.sub.2 is connected to a ground.

[0056] As shown in FIG. 8 (b), the tapped inductor impedance transformation network may comprise a first and second inductors L.sub.1, L.sub.2 connected in series. A second terminal of the first inductor L.sub.1 is connected to a first terminal of the second inductor L.sub.2 to form a tapped node. The input terminal INTin of the impedance transformation network is connected to the tapped node, the output terminal INTout of the impedance transformation network is connected to a first terminal of the first inductor L.sub.1, a second terminal of the second inductor L.sub.2 is connected to a ground.

[0057] In the following, the principle and performance of the proposed power amplifier 700 will be analysed.

[0058] Each power cell may be a common source configured transistor. Each transistor connected with the junction of two transmission lines TL.sub.1i should be matched to R′.sub.opt, where R′.sub.opt is the output impedance of the ITN with the input impedance of R.sub.opt. The inverse of R′.sub.opt, i.e. 1/R′.sub.opt, needs to be matched to the admittance difference:

[00002]$\begin{array}{cc}\frac{1}{R_{\mathrm{opt}}^{\prime }}=\frac{1}{Z_i}-\frac{1}{Z_{i+1}}\left(i=1,2.Math.n\right)& \left(2\right)\end{array}$

[0059] where Z.sub.i is the impedance looking to left from the junction of two transmission lines, Z.sub.i+1 is the impedance looking to the right from the junction of the two transmission lines, as shown Z.sub.1, Z.sub.2 in FIG. 7. The impedance Z.sub.i depends on the TL's length and width, as well as the loading of the neighboring transistors at either left side or right side. The larger R′.sub.opt is, the easier it is for impedance matching. Unfortunately, to deliver a large output power, a large transistor has a small R.sub.opt. Furthermore, a large transistor has a large parasitic capacitance which loads on transmission lines at drain. Those parasitic capacitors, together with the transmission lines, will form artificial transmission lines.

[0060] An upward impedance transformation network transfers the small R.sub.opt and a large parasitic capacitance into a large R′.sub.opt and a small capacitance, i.e. high impedance. The transistor's parasitic capacitance may be part of upward impedance transformation network.

[0061] A tapped capacitor impedance transformation network connected to a transistor is shown in FIG. 9. The transistor is represented by a Norton-equivalent circuit, i.e., a current source, I.sub.d, with a shunted parasitic capacitor, C.sub.d. While, R.sub.opt is the impedance should be provided by the tapped capacitor impedance transformation network, as shown in FIG. 9 (a). C.sub.1 and C.sub.2 represent two capacitors in the tapped capacitor impedance transformation network.

[0062] FIG. 9 (b) shows the equivalent circuit after merging C.sub.2 and C.sub.d, where R.sub.2=R.sub.opt, C′.sub.2=c.sub.d+C.sub.2. The parasitic capacitance, C.sub.d, becomes a part of the tapped capacitor impedance transformation network, C′.sub.2=C.sub.d+C.sub.2, and R.sub.2 is equal to R.sub.opt.

[0063] FIG. 9 (c) shows the equivalent circuit after transferring parallel connected resistor R.sub.2 and capacitors (C.sub.2+C.sub.d) into series.

[0064] FIG. 9 (d) shows the equivalent circuit after transferring series connected capacitors and resistor into parallel.

[0065] To get the equivalent R.sub.t and C connected in parallel of the tapped capacitor matching network, as shown in FIG. 9 (d), the parallel connected capacitor C′.sub.2 and resistor R.sub.2, as shown in FIG. 9 (b) are replaced by R′.sub.2 and C″.sub.2 connected in series, as shown in FIG. 9 (c), and

[00003]$\begin{array}{cc}{R}_2^{\prime }=\frac{R_2}{1+Q_2^2}& \left(3a\right)\end{array}$$\begin{array}{cc}{C}_2^{″}=\left(C_d+C_2\right)\left(1+\frac{1}{Q_2^2}\right)& \left(3b\right)\end{array}$

[0066] where Q.sub.2 is the Q-factor of the parallel connected R.sub.2 and C′.sub.2:

Q.sub.2=ω.sub.0(C.sub.d+C.sub.2)R.sub.2.

[0067] The equivalent capacitance, C.sub.eq, represents the total capacitance of C.sub.1 and C′.sub.2 in series, which is given by

[00004]$\begin{array}{cc}{C}_{\mathrm{eq}}=\frac{C_1\left(C_d+C_2\right)\left(1+\frac{1}{Q_2^2}\right)}{C_1+\left(C_d+C_2\right)\left(1+\frac{1}{Q_2^2)}\right)}& \left(4\right)\end{array}$$\mathrm{If}{Q}_2^2\gg 1,C_{\mathrm{eq}}\approx \frac{C_1\left(C_d+C_2\right)}{C_1+C_d+C_2}.$

[0068] Furthermore, the Q-factor of the series connected R′.sub.2 and C.sub.eq is defined as

[00005]$\begin{array}{cc}Q=\frac{1}{{\omega }_0{C}_{\mathrm{eq}}{R}_2^{\prime }}=\frac{C_1{Q}_2^2+\left(C_d+C_2\right)\left(1+Q_2^2\right)}{Q_2{C}_1}& \left(5\right)\end{array}$$\mathrm{If}{Q}_2^2\gg 1,Q\approx Q_2\left(1+\frac{C_d+C_2}{C_1}\right).$

[0069] Finally, the equivalent R.sub.t and C.sub.t connected in parallel are given by

[00006]$\begin{array}{cc}{R}_t=R_2^{\prime }\left(1+Q^2\right)& \left(6a\right)\end{array}$$\begin{array}{cc}{C}_t=\frac{C_{\mathrm{eq}}}{1+\frac{1}{Q^2}}& \left(6b\right)\end{array}$$\mathrm{If}{Q}_2^2\gg 1\mathrm{and}{Q}^2\gg 1,$$\begin{array}{cc}{R}_t\approx {R_{\mathrm{opt}}\left[1+\frac{C_d+C_2}{C_1}\right]}^2& \left(7a\right)\end{array}$$\begin{array}{cc}{C}_t\approx \frac{C_1\left(C_d+C_2\right)}{C_1+C_d+C_2}& \left(7b\right)\end{array}$

[0070] From equations (3)-(7), it can be found that, using the tapped capacitor matching network, the resistance is increased approximately by a factor of

[00007]${\left[1+\frac{C_d+C_2}{C_1}\right]}^2,$

and the capacitance is reduced approximately by a factor of

[00008]$\left[\frac{C_1\left(1+\frac{C_2}{C_d}\right)}{C_1+C_2+C_d}\right].$

Note that R.sub.t represents R′.sub.opt in (2).

[0071] It should be pointed out that the tapped capacitor impedance transformation network is just one example embodiment. Other type of upward impedance matching network may be used also. For example, two capacitors may be replaced by two inductors, forming a tapped inductor impedance transformation network. Moreover, an π or T network, may be used too. However, the π or T network is comprised of, at least, 3 passive components, which has a larger footprint than that of a tapped capacitor and inductor impedance transformation network.

[0072] Therefore, according to some embodiments, each upward impedance transformation network may comprise a T-impedance matching network comprising at least three passive components connected in T-shape.

[0073] According to some embodiments, each impedance transformation network may comprise a π-impedance matching network comprising at least three passive components connected in π-shape.

[0074] According to some embodiments, each impedance transformation network may comprise a transformer.

[0075] According to some embodiments, each power cell may comprise a common-source configured transistor, a gate of each transistor is connected to the input terminal of the power cell and a drain of each transistor is connected to the output terminal of the power cell, a source of each transistor is connected to a ground.

[0076] FIG. 10 shows an example embodiment of a 70-88 GHz PA 1000 targeting a large output power. This PA has 4 common-source configured transistors. Each drain of the transistor is connected with a tapped capacitor matching network consisting of C.sub.di and C.sub.dii (i=1, 2, 3, 4). Each tapped capacitor impedance transformation network is connected with the junction of the output transmission lines, TL.sub.1i (i=1, 2, 3, 4), except the first one which is connected with a first terminal of TL.sub.11. The width of the TLs increases from the left side to the right side. Therefore, the characteristic impedance of the TLs decreases correspondingly. The drain bias is provided through an AC choke. Each gate of the transistor is connected with the junction of the input transmission lines TL.sub.0i (i=1, 2, 3, 4) via a capacitor C.sub.gi (i=1, 2, 3, 4), except the last capacitor C.sub.g4 is connected with a second terminal of TL.sub.04. Capacitance of C.sub.gi increases from the left side to the right side, to keep the input signal for all transistors having the same amplitude. The gate resistor R.sub.g is inserted between the transistor's gate and the gate bias, to block the leakage of the RF signal. The input port is connected with the first terminal of the first transmission line TL.sub.01.

[0077] FIG. 11 shows PA's gain versus output power at frequencies 70 GHz, 76 GHz, 82 GHz, as well as 88 GHz. The small signal gain of the PA 1000 is varied between 4.2 dB to 6.6 dB at different frequencies. As output power increases, the gain decreases no more than 2.5 dB for those frequencies. The maximum output power of the PA varies between 33.8 dBm and 34.7 dBm for different frequencies.

[0078] FIG. 12 shows power added efficiency (PAEs) of the PA 1000 at frequencies 70 GHz, 76 GHz, 82 GHz, as well as 88 GHz. The maximum PAEs varies between 16% to 24% at different frequencies.

[0079] In summary, the PA 700, 1000 according to embodiments herein combines the output powers of the multiple power cells or transistors A.sub.i (i=1, 2 . . . n), through transmission lines TL.sub.1i (i=1, 2 . . . n), connected in series. These transmission lines may have different widths and lengths. The transistor's drain is connected with the transmission lines via an impedance transformation network. This impedance transformation network may be a tapped capacitor or inductor network which transfers impedance upward, i.e. transfers a low impedance at the input terminal of the impedance transformation network connecting with the drain into a large impedance at the output terminal of the impedance transformation network. The output terminal of the impedance transformation network is connected with the transmission lines, and releases loading from the transistors to the transmission lines TL.sub.1i. Therefore, it provides impedance matching for large transistors with a small R.sub.opt, to increase output power.

[0080] The input power is distributed though transmission lines TL.sub.0i(i=1, 2 . . . n) connected in series, as well as the capacitors at the gates, C.sub.gi (i=1, 2 . . . n). These capacitors may have different capacitances and help to equalize the input power for each transistor.

[0081] The power amplifier 700, 1000 according to embodiments herein may be employed in various electronic devices. FIG. 13 shows a block diagram for an electronic device 1300, which may be, e.g. a radio frequency transceiver, a transmitter, a wireless communication device, a user equipment, a mobile device, a base station or a radio network node etc. in a wireless communication systems, or any general electronic circuit or equipment which needs a power amplifier. The electronic device 1300 may comprise other units, where a processing unit 1310, a memory 1320 are shown.

[0082] When using the word “comprise” or “comprising” it shall be interpreted as non-limiting, i.e. meaning “consist at least of”.

[0083] The embodiments herein are not limited to the above described embodiments. Various alternatives, modifications and equivalents may be used. Therefore, the above embodiments should not be taken as limiting the scope of the invention, which is defined by the appending claims.