SUBSTRATE WITH BURIED COMPONENT AND MANUFACTURE METHOD THEREOF

Abstract

A substrate is manufactured by drilling a chip containing groove in a composite inner layer circuit structure, having a component connecting end of a circuit layer protruding from a mounting side wall in the chip containing groove, mounting a chip component in the chip containing groove, and connecting the surface bonding pad to the component connecting end. The chip component in the present invention penetrates at least two circuit layers, and the surface bonding pad is bonded to the component connecting end of the circuit layer directly, reducing the occupied area of the chip component in each one of the circuit layers, and increasing the area for circuit disposing and the possible amount of chip components that may be mounted in the substrate.

Claims

1. A substrate with a buried component, comprising: a composite inner layer circuit structure, including a plurality of circuit layers, and having at least one component connecting end; and a chip component, disposed in the composite inner layer circuit structure, penetrating at least two circuit layers of the plurality of circuit layers, having a top surface and a bottom surface opposite to the top surface, and having at least one surface bonding pad at the bottom surface; wherein the at least one surface bonding pad of the chip component is connected to the at least one component connecting end of the plurality of circuit layers.

2. The substrate with a buried component as claimed in claim 1, wherein the composite inner layer circuit structure has a chip containing groove, formed through at least two circuit layers of the plurality of circuit layers and having a mounting side wall; wherein the at least one component connecting end protrudes from the mounting side wall in the chip containing groove; wherein the chip component is disposed in the chip containing groove, the bottom surface of the chip component faces to the mounting side wall in the chip containing groove, and the surface bonding pad is connected to the at least one component connecting end of the at least two circuit layers.

3. The substrate with a buried component as claimed in claim 2, further comprising: an adding layer circuit structure, stacked with the composite inner layer circuit structure and closing an opening of the chip containing groove.

4. The substrate with a buried component as claimed in claim 3, wherein a bottom wall and a lateral wall are disposed in the chip containing groove and the mounting side wall is a part of the lateral wall; wherein the substrate with a buried component further comprises: a metallic shield layer, covering the bottom wall of the chip containing groove and a part of the lateral wall excluding the mounting side wall, connected to the surface circuit structure, and electrically connected to a grounding terminal via the surface circuit structure.

5. A manufacture method of a substrate with a buried component, comprising the following steps: providing a composite inner layer circuit structure, including a plurality of circuit layers; performing a drilling process to drill the composite inner layer circuit structure to form a chip containing groove, having a mounting side wall, penetrating at least two circuit layers of the plurality of circuit layers; performing a desmearing process for the chip containing groove to allow at least one component connecting end of the plurality of circuit layers to protrude from the mounting side wall; disposing a chip component in the chip containing groove to allow the chip component being disposed in the composite inner layer circuit structure to penetrate at least two circuit layers of the plurality of circuit layers and to allow a surface bonding pad of the chip component to align with the at least one component connecting end; and connecting the surface bonding pad of the chip component to the component connecting end of the circuit layer.

6. The manufacture method as claimed in claim 5, further comprising: performing a circuit build-up layer process to dispose an adding layer circuit structure on the composite inner layer circuit structure to close an opening of the chip containing groove.

7. The manufacture method as claimed in claim 6, wherein after forming the chip containing groove, the method further comprises the following steps: performing an electroplating process to form a metallic shield layer on a bottom wall and a lateral wall of the chip containing groove; performing a polishing process to remove the metallic shield layer covering a part of the lateral wall and to expose a part of the lateral wall and the at least one component connecting end of the circuit layer; wherein the exposed lateral wall is the mounting side wall; and performing a desmearing process for the mounting side wall to allow the at least one component connecting end of the circuit layer to protrude from the mounting side wall.

8. The manufacture method as claimed in claim 7, wherein, the circuit build-up layer process comprises the following steps: covering an adding dielectric layer on the composite inner layer circuit structure to close an opening of the chip containing groove; performing a drilling process for the adding dielectric layer to form a trench communicating with an upper edge of the metallic shield layer; and disposing an adding circuit layer on the adding dielectric layer and in the trench, including a shielding layer cover, being a flat circuit; wherein a projection of the shielding layer cover in a perpendicular direction of the composite inner layer circuit structure covers the opening of the chip containing groove; wherein the shielding layer cover is connected to the upper edge of the metallic shield layer in the trench; wherein the metallic shield layer is electrically connected to a grounding terminal via the adding circuit layer.

9. The manufacture method as claimed in claim 6, wherein the surface bonding pad of the chip component is bonded to the at least one component connecting end of the circuit layer by a heat diffusion welding process or an ultrasonic welding process.

10. A manufacture method of a substrate with a buried component, comprising the following steps: providing a first composite inner layer circuit structure; wherein the first composite inner layer circuit structure includes a plurality of first circuit layers, and has a first side; wherein at least one component connecting end of the plurality of first circuit layers protrudes from the first side; providing a chip component; wherein the chip component has a top surface and a bottom surface opposite to the top surface, and has at least one surface bonding pad at the bottom surface of the chip component; facing the bottom surface of the chip component to the first side of the first composite inner layer circuit structure, and connecting the at least one surface bonding pad to the at least one component connecting end of the first composite inner layer circuit structure; providing a second composite inner layer circuit structure; wherein the second composite inner layer circuit structure has a second side; bonding the second side of the second composite inner layer circuit structure with a second surface of the chip component; and performing a circuit build-up layer process for disposing two surface circuit structures at the first composite inner layer circuit structure and the second composite inner layer circuit structure to fix the first composite inner layer circuit structure, the chip component, and the second composite inner layer circuit structure between the two surface circuit structures.

11. The manufacture method as claimed in claim 10, wherein the first composite inner layer circuit structure has a first top surface and a first bottom surface opposite to the first top surface; the second composite inner layer circuit structure has a second top surface and a second bottom surface opposite to the second top surface; wherein the first top surface parallels and faces in the same direction with the second top surface, and the first bottom surface parallels and faces in the same direction with the second bottom surface; wherein the circuit build-up layer process includes the following steps: covering a first build-up dielectric layer on the first top surface of the first composite inner layer circuit structure and the second top surface of the second composite inner layer circuit structure; covering a second build-up dielectric layer on the first bottom surface of the first composite inner layer circuit structure and the second bottom surface of the second composite inner layer circuit structure; and disposing a first build-up circuit layer on the first build-up dielectric layer, and disposing a second build-up circuit layer on the second build-up dielectric layer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0040] FIG. 1 is a side view profile diagram of a substrate with a buried component of the present invention;

[0041] FIG. 2A to FIG. 2H are the profile diagrams of the manufacture method for the substrate with a buried component in the first embodiment of the present invention;

[0042] FIG. 3A to FIG. 3L are the profile diagrams of the manufacture method for the substrate with a buried component in the second embodiment of the present invention;

[0043] FIG. 4 is a partial top view for one step of the manufacture method for the substrate with a buried component in the second embodiment of the present invention;

[0044] FIG. 5A to FIG. 5F are the profile diagrams of the manufacture method for the substrate with a buried component in the third embodiment of the present invention;

[0045] FIG. 6 is another side view profile diagram of the substrate with a buried component of the present invention;

[0046] FIG. 7 is another side view profile diagram of the substrate with a buried component of the present invention; and

[0047] FIG. 8 is a side view profile diagram of the substrate with a buried component of the prior art.

DETAILED DESCRIPTION OF THE INVENTION

[0048] Refer to FIG. 1. The substrate with a buried component of the present invention includes a composite inner layer circuit structure 10 and a chip component 20. The composite inner layer circuit structure 10 includes a plurality of circuit layers 11, wherein the plurality of circuit layers 11 have at least one component connecting end 111. The chip component 20 is disposed in the composite inner layer circuit structure 10 and penetrates at least two circuit layers 11 of the plurality of circuit layers 11. The chip component 20 has a top surface 22, a bottom surface 21, and at least one surface bonding pad 23 at the bottom surface 21. The at least one surface bonding pad 23 of the chip component 20 is directly bonded with the at least one component connecting end 111.

[0049] The substrate with a buried component of the present invention can be manufactured by at least two methods as below.

[0050] Refer to FIG. 2A to FIG. 2E. The first embodiment of the method for manufacturing the substrate with a buried component of the present invention includes the following steps:

[0051] as shown in FIG. 2A, providing a composite inner layer circuit structure 10, including a plurality of circuit layers 11; wherein the plurality of circuit layers 11 has at least one component connecting end 111;

[0052] as shown in FIG. 2B, performing a drilling process for the composite inner layer circuit structure 10 to form a chip containing groove 100; wherein the chip containing groove 100 is formed through at least two circuit layers 11 of the plurality of circuit layers 11 and the chip containing groove 100 has a mounting side wall 101;

[0053] as shown in FIG. 2C, performing a desmearing process for the chip containing groove 100; wherein the at least one component connecting end 111 protrudes from the mounting side wall 101;

[0054] as shown in FIG. 2D, disposing a chip component 20 in the chip containing groove 100; wherein the chip component 20 disposed in the composite inner layer circuit structure 10 penetrates at least two circuit layers 11 of the plurality of circuit layers 11, and at least one surface bonding pad 23 of the chip component 20 aligns with the at least one component connecting end 111; and as shown in FIG. 2E, connecting the surface bonding pad 23 of the chip component 20 to the component connecting end 111 of the circuit layer 11.

[0055] In the embodiment, the method first provides the composite inner layer circuit structure 10 having a plurality of circuit layers 11. The method drills the surface of the composite inner layer circuit structure 10 to form a chip containing groove 100 for embedding the chip component 20 so that the component connecting ends 111 of the plurality of circuit layers 11 are exposed from the chip containing groove 100. It should be noted that the component connecting end 111 of the at least two circuit layers 11 and the space of the chip containing groove 100 are preserved and predetermined according to the circuit layer 11 so that the component connecting end 111 is disposed at the edge of the predetermined space of the chip containing groove 100. In this way, when the composite inner layer circuit structure 10 is processed for the drilling process, the component connecting end 111 of the circuit layer 11 is extremely close to or is exactly exposed from the mounting side wall 101 of the chip containing groove 100. FIG. 2B is an embodiment that the component connecting end 111 is exactly exposed from the chip containing groove 100. After the drilling process, the method desmears the chip containing groove 100 to remove the dielectric residue in the chip containing groove 100. The process erodes the inner wall of the chip containing groove 100 so that the component connecting end 111 extremely close to or exposed from the surface of the mounting side wall 101 protrudes from the mounting side wall 101 to be connected to the bonding pad 23 of the chip component 20. In the preferable embodiment, the surface bonding pad 23 of the chip component 20 and the component connecting end 111 of the circuit layer 11 are directly bonded by the method of heat diffusion welding or the method of ultrasonic welding.

[0056] In the embodiment, the composite inner layer circuit structure 10 has the chip containing groove 100. The chip containing groove 100 is formed through at least two circuit layers 11 and has a mounting side wall 101. The component connecting end 111 of the plurality of circuit layers 11 protrudes from the mounting side wall 101 of the chip containing groove 100. The chip component 20 is disposed in the chip containing groove 100 and penetrates the at least two circuit layers 11. The bottom surface 21 of the chip component 20 faces the mounting side wall 101 of the chip containing groove 100. The surface bonding pad 23 is directly bonded to the component connecting end 111 of the circuit layer 11.

[0057] As shown in FIG. 2F to FIG. 2H. In the first embodiment, after the surface bonding pad 23 of the chip component 20 is bonded to the component connecting end 111 of the circuit layer 11, the method further includes the following steps:

[0058] performing a circuit build-up layer process to dispose an adding layer circuit structure 30 on the composite inner layer circuit structure 10; and

[0059] closing an opening 102 of the chip containing groove 100 to complete the substrate with a buried component.

[0060] The adding layer circuit structure 30 includes at least one adding dielectric layer 31 and at least one adding circuit layer 32. The embodiment takes one single adding dielectric layer 31 and one single adding circuit layer 32 for an example, but is not limited thereto in the present invention. The process for disposing the adding layer circuit structure 30 includes the following steps:

[0061] as shown in FIG. 2F, pressing an adding dielectric layer 31 on the composite inner layer circuit structure 10; wherein the adding dielectric layer 31 closes the opening 102 of the chip containing groove 100; wherein the opening 102 is formed at the drilling process for the composite inner layer circuit structure 10 to form a chip containing groove 100; preferably, when the method performs the step for pressing the adding dielectric layer 31, the material of the adding dielectric layer 31 is squeezed into the chip containing groove 100 and fills the chip containing groove 100;

[0062] as shown in FIG. 2G, disposing an adding circuit layer 32 on the adding dielectric layer 31; and

[0063] as shown in FIG. 2H, disposing a solder mask layer 40 on the adding circuit layer 32; wherein the solder mask layer 40 has at least one solder mask opening to expose a part of the adding circuit layer 32.

[0064] When the method performs the step for pressing the adding dielectric layer 31 on the composite inner layer circuit structure 10, the material of the adding dielectric layer 31 is squeezed from the opening 102 at the surface of the composite inner layer circuit structure 10 to the chip containing groove 100 at the same time so that the material of the adding dielectric layer 31 is filled into the chip containing groove 100. In another embodiment, the method can perform an adhesive-filling process for the chip component 20 disposed in the chip containing groove 100 before pressing the adding dielectric layer 31 to fill the adhesive in the chip containing groove 100.

[0065] After pressing the adding dielectric layer 31, the method further disposes the adding circuit layer 32 and the solder mask layer 40 on the adding dielectric layer 31. The adding circuit layer 32 and the solder mask layer 40 can be disposed by the processes, which include drilling, exposure developing, electroplating, etching, and pressing the solder mask layer 40, and the details are omitted herein.

[0066] As shown in FIG. 3A to FIG. 3E. In a second embodiment, preferably, the chip containing groove 100 further includes a metallic shield layer 12. In details, the chip containing groove 100 has a bottom wall 103 and a lateral wall 104. The mounting side wall 101 mentioned above is a part of the lateral wall 104. The metallic shield layer 12 covers the bottom wall 103 of the chip containing groove 100 and a part of the lateral wall 104 excluding the mounting side wall 101. The method for manufacturing the substrate with a buried component with the metallic shield layer 12 includes the following steps:

[0067] as shown in FIG. 3A, providing a composite inner layer circuit structure 10; wherein the composite inner layer circuit structure 10 includes a plurality of circuit layers 11;

[0068] as shown in FIG. 3B, performing a drilling process for the composite inner layer circuit structure 10 to form a chip containing groove 100; wherein the chip containing groove 100 is formed through at least two circuit layers 11 of the plurality of circuit layers 11; wherein the bottom wall 103 and the lateral wall 104 are disposed in the chip containing groove 100 and a part of the lateral wall 104 is the mounting side wall 101;

[0069] as shown in FIG. 3C, when the method forms the chip containing groove 100, the method further performs an electroplating process for the chip containing groove 100 to form the metallic shield layer 12 on the bottom wall 103 and the lateral wall 104 of the chip containing groove 100;

[0070] after that, as shown in FIG. 3D, performing a polish process for a part of the lateral wall 104 belonging to the mounting side wall 101 in the chip containing groove 100 to remove the metallic shield layer 12; wherein the metallic shield layer 12 covers the part of the lateral wall 104 to expose a part of the lateral wall 104, and to expose the component connecting end 111 of the circuit layer 11; wherein, the exposed lateral wall 104 is the mounting side wall 101; and

[0071] as shown in FIG. 3E, performing a desmearing process for the mounting side wall 101; wherein at least one component connecting end 111 of the circuit layer 11 protrudes from the mounting side wall 101.

[0072] In this way, the metallic shield layer 12 disposed in the chip containing groove 100 is completed. Referring to FIG. 3F and FIG. 3G, after disposing the metallic shield layer 12, the chip component 20 is disposed in the chip containing groove 100. The details for disposing the chip component 20 are similar to the first embodiment and omitted herein.

[0073] As shown in FIG. 3H to FIG. 3J. In the embodiment, similarly, after disposing the chip component 20, the adding layer circuit structure 30 will be disposed on the composite inner layer circuit structure 10. It should be noted, in the embodiment, the adding layer circuit structure 30 further includes a shielding layer cover 321. The metallic shield layer 12 covers the surface in the chip containing groove 100 excluding the mounting side wall 101. The shielding layer cover 321 is a flat circuit, corresponding to the opening 102 disposed in the chip containing groove 100, and covering above the chip component 20. The steps for the adding layer circuit structure 30 are described as below:

[0074] as shown in FIG. 3H, covering an adding dielectric layer 31 on the composite inner layer circuit structure 10; wherein the adding dielectric layer 31 closes the opening 102 of the chip containing groove 100;

[0075] as shown in FIG. 3I, performing a drilling process for the adding dielectric layer 31 to form a trench 310; wherein the trench 310 communicates with an upper edge of the metallic shield layer 12;

[0076] as shown in FIG. 3J, disposing an adding circuit layer 32 on the adding dielectric layer 31 and in the trench 310, including a shielding layer cover 321, which is a flat circuit; wherein the projection of the shielding layer cover 321 of the adding circuit layer 32 in a perpendicular direction of the composite inner layer circuit structure 10 covers the opening 102 of the chip containing groove 100, and the shielding layer cover 321 connects to the upper edge of the metallic shield layer 12 in the trench 310;

[0077] As shown in FIG. 3K and FIG. 3L, the adding layer circuit structure 30 can include multiple adding dielectric layers 31 and multiple adding circuit layers 32. The grounding terminal 33 can be disposed in the outermost adding circuit layer 32 so that the metallic shield layer 12 and the shielding layer cover 321 are electrically connected to the grounding terminal 33. Ultimately, the solder mask layer 40 is disposed on the outermost adding circuit layer 32 to complete the substrate with a buried component. The metallic shield layer 12 with the shielding layer cover 321 are connected to the grounding terminal 33, the metallic shield layer 12 and the shielding layer cover 321 to form a metallic shielding mask with an electromagnetic shielding function for the chip component 20 disposed in chip containing groove 100.

[0078] Preferably, refer to FIG. 4. FIG. 4 is the plan schematic view for the adding dielectric layer 31 after forming the trench 310. Since the metallic shield layer 12 is disposed according to the position of the lateral wall 104 disposed in the chip containing groove 100, failing to cover the mounting side wall 101, an upper edge of the metallic shield layer 12 is in the “n” shape. The shape and the position of the trench 310 correspond to the upper edge of the metallic shield layer 12 so that the bottom of the trench 310 is connected to the entire upper edge of the metallic shield layer 12. As the result, the shielding layer cover 321 in the trench 310 can be entirely connected to the upper edge of the metallic shield layer 12 to form a complete metallic shielding mask, enclosing the chip component 20 disposed in the composite inner layer circuit structure 10 and achieving the superior shielding effect when the shielding layer cover 321 is connected to the grounding terminal 33.

[0079] Refer to FIG. 5A to FIG. 5C. In a third embodiment, the present invention provides another method for manufacturing the substrate with a buried component, including the following steps:

[0080] as shown in FIG. 5A, providing a first composite inner layer circuit structure 10A; wherein the first composite inner layer circuit structure 10A includes a plurality of first circuit layers 11A and has a first side 105A; wherein at least two component connecting ends 111A of at least two first circuit layers 11A in the plurality of first circuit layers 11A protrude from the first side 105A;

[0081] providing a chip component 20; wherein the chip component 20 has a bottom surface 21 and a top surface 22 opposite to the bottom surface 21, and has at least one surface bonding pad 23 on the bottom surface 21;

[0082] as shown in FIG. 5B, facing the bottom surface 21 of the chip component 20 to the first side 105A of the first composite inner layer circuit structure 10A;

[0083] connecting the at least two surface bonding pads 23 to at least two component connecting ends 111A of the first composite inner layer circuit structure 10A; preferably, wherein the surface bonding pad 23 of the chip component 20 and the component connecting end 111A of the first circuit layer 11A are bonded by the method of heat diffusion welding or the method of ultrasonic welding;

[0084] as shown in FIG. 5C, providing a second composite inner layer circuit structure 10B; wherein the second composite inner layer circuit structure 10B includes a plurality of second circuit layers 11B, and has a second side 105B; wherein the second side 105B of the second composite inner layer circuit structure 10B is bonded to the top surface 22 of the chip component 20; preferably, wherein the second side 105B of the second composite inner layer circuit structure 10B is bonded to the top surface 22 of the chip component 20 by an adhesion layer 13.

[0085] Refer to FIG. 5D to FIG. 5F. The method further performs a circuit build-up layer process to respectively dispose two adding layer circuit structures 30A, 30B on and below the first composite inner layer circuit structure 10A and the second composite inner layer circuit structure 10B. Therefore, the first composite inner layer circuit structure 10A, the chip component 20 and the second composite inner layer circuit structure 10B are fixed between the two adding layer circuit structures 30A, 30B.

[0086] As mentioned above, the first composite inner layer circuit structure 10A has a first top surface 106A and a first bottom surface 107A opposite to the first top surface 106A. The second composite inner layer circuit structure 10B has a second top surface 106B and a second bottom surface 107B opposite to the second top surface 106B. The first top surface106A and the second top surface 106B are parallel to the same direction, and the first bottom surface 107A and the second bottom surface 107B are parallel to the same direction. Moreover, the circuit build-up layer process includes the following steps:

[0087] as shown in FIG. 5D, covering a first adding dielectric layer 31A on the first top surface106A of the first composite inner layer circuit structure 10A and the second top surface 106B of the second composite inner layer circuit structure 10B;

[0088] covering a second adding dielectric layer 31B on the first bottom surface 107A of the first composite inner layer circuit structure 10A and the second bottom surface 107B of the second composite inner layer circuit structure 10B;

[0089] as shown in FIG. 5E, disposing a first adding circuit layer 32A on the first adding dielectric layer 31A and disposing a second adding circuit layer 32B on the second adding dielectric layer 31.

[0090] Preferably, referring to FIG. 5F, after the method disposes the first adding circuit layer 32A and second adding circuit layer 32B, the method further respectively disposes the first solder mask layer 40A and the second solder mask layer 40B on the first adding circuit layer 32A and the second adding circuit layer 32B to complete the substrate with a buried component.

[0091] In the third embodiment, the method utilizes two composite inner layer circuit structures with the chip component to form the substrate with a buried component of the present invention. The first circuit layer 11A of the first composite inner layer circuit structure 10A protrudes from the component connecting end 111A of the first side 105A to be connected to the surface bonding pad 23 disposed at the bottom surface 21 of the chip component 200. After the chip component 20 is connected to the first composite inner layer circuit structure 10A, the second side 105B of the second composite inner layer circuit structure 10B is bonded to the top surface 22 of the chip component 20 far away the first composite inner layer circuit structure 10A to form an assembly composite inner layer circuit structure clamping the chip component 20. After that, the adding layer circuit structure 30A and the adding layer circuit structure 30B are respectively disposed on the top surface and the bottom surface of the assembly composite inner layer circuit structure in the circuit build-up layer process to fix the first composite inner layer circuit structure 10A, the second composite inner layer circuit structure 10B and the chip 24 component 20. The first composite inner layer circuit structure 10A can be electrically connected to the second composite inner layer circuit structure 10B via the first adding circuit layer 31A and the second adding circuit layer 31B in the adding layer circuit structure 30A, 30B.

[0092] As shown in FIG. 6, both the substrate with a buried component of the present invention allows the chip component 20 to occupy less horizontal areas of the circuit layer 11 and the surface bonding pad of the chip component 20 is directly connected to the component connecting end 111 of the circuit layer 11. Consequently, the chip component 20 does not have to be perpendicularly connected to the conductive blind hole and the circuit layer 11 via the circuit layer 11. In addition, as shown in FIG. 7, when the substrate with a buried component of the present invention disposes at least two chip components 20, the two chip components 20 can be connected to each other via the component connecting end 111 at the two terminals of the circuit layer 11 to reduce the connection path. In contrast, the two chip components of the prior art are connected to each other via the conductive blind hole, the circuit layer, and the conductive blind hole.

[0093] Even though numerous characteristics and advantages of the present invention have been set forth in the foregoing description, together with details of the structure and function of the invention, the disclosure is illustrative only. Changes may be made in detail, especially in matters of shape, size, and arrangement of parts within the principles of the invention to the full extent indicated by the broad general meaning of the terms in which the appended claims are expressed.