Shift register and display device

Abstract

A shift register and a display device are provided. The shift register includes a pre-charge unit, a pull-up unit, a first pull-down unit and a second pull-down unit. The pre-charge unit receives first and second input signals, and outputs a pre-charge signal via a first node. The pull-up unit receives the pre-charge signal and a clock signal, and outputs a scanning signal via a second node. The first pull-down unit receives the pre-charge signal, first and second pull-down control signals, and controls whether to pull-down the scanning signal to a reference voltage level. The second pull-down unit receives the pre-charge signal and first and second pull-down control signals, and controls whether to keep the scanning signal at the reference voltage level. The period of the first second pull-down control signal and the period of the second pull-down control signal are in a range from 12 frames to 180 frames.

Claims

1. A shift register, comprising: a pre-charge unit configured to receive a first input signal and a second input signal and output a pre-charge signal via a first node based on the first input signal and the second input signal; a pull-up unit that is coupled to the pre-charge unit, the pull-up unit configured to receive the pre-charge signal and a clock signal and output a scan signal via a second node based on the pre-charge signal and the clock signal; a first pull-down unit coupled to the pre-charge unit and the pull-up unit, the first pull-down unit configured to receive the pre-charge signal, a first pull-down control signal and a second pull-down control signal and control whether to pull down the scan signal to a reference voltage level based on the pre-charge signal, the first pull-down control signal and the second pull-down control signal; and a second pull-down unit coupled to the pre-charge unit and the pull-up unit, the second pull-down unit configured to receive the pre-charge signal, the first pull-down control signal and the second pull-down control signal and control whether to keep the scan signal at the reference voltage level based on the pre-charge signal, the first pull-down control signal and the second pull-down control signal; wherein periods of the first pull-down control signal and the second pull-down control signal are in a range from 12 frames to 180 frames, and a time interval between a rising edge of the first pull-down control signal and a falling edge of the second pull-down control signal is in a range from 2 microseconds to 4 microseconds.

2. The shift register of claim 1, wherein the period of the first pull-down control signal is substantially the same as the period of the second pull-down control signal, and the period of the first pull-down control signal and the period of the second pull-down control signal are 120 frames.

3. The shift register of claim 1, wherein the pre-charge unit comprises: a first transistor, wherein a gate of the first transistor is configured to receive a starting signal, a first source/drain of the first transistor is configured to receive a forward input signal, and a second source/drain of the first transistor is configured to output the pre-charge signal; and a second transistor, wherein a gate and a first source/drain of the second transistor are configured to receive another scan signal outputted by a next two stage of shift register to the shift register, and a second source/drain of the second transistor is coupled to the second source/drain of the first transistor.

4. The shift register of claim 1, wherein the pre-charge unit comprises: a first transistor, wherein a gate of the first transistor is configured to receive another scan signal outputted by a previous two stage of shift register to the shift register, a first source/drain of the first transistor is configured to receive a forward input signal, and a second source/drain of the first transistor is configured to output the pre-charge signal; and a second transistor, wherein a gate of the second transistor is configured to receive another scan signal outputted by a next two stage of shift register to the shift register, a first source/drain of the second transistor is configured to receive a backward input signal, and a second source/drain of the second transistor is coupled to the second source/ drain of the first transistor.

5. The shift register of claim 1, wherein the pull-up unit comprises: a third transistor, wherein a gate of the third transistor is configured to receive the pre-charge signal, a first source/drain of the third transistor is configured to receive the clock signal, and a second source/drain of the third transistor is configured to output the scan signal; and a capacitor, wherein a first terminal of the capacitor is coupled to the gate of the third terminal, and a second terminal of the capacitor is coupled to the second source/drain of the third transistor.

6. The shift register of claim 1, wherein the first pull-down unit comprises: a fourth transistor, wherein a gate and a first source/drain of the fourth transistor are configured to input the first pull-down control signal; a fifth transistor, wherein a gate of the fifth transistor is configured to input the second pull-down control signal, a first source/drain of the fifth transistor is configured to input the reference voltage level, and a second source/drain of the fifth transistor is coupled to the second source/drain of the fourth transistor; a sixth transistor, wherein a gate of the sixth transistor is coupled to the first node, a first source/drain of the sixth transistor is configured to input the reference voltage level, and a second source/drain of the sixth transistor is coupled to the second source/drain of the fourth transistor; a seventh transistor, wherein a gate of the seventh transistor is coupled to the second source/drain of the sixth transistor, a first source/drain of the seventh transistor is configured to input the reference voltage level, and a second source/drain of the seventh transistor is coupled to the first node; and an eighth transistor, wherein a gate of the eighth transistor is coupled to the second source/drain of the sixth transistor, a first source/drain of the eighth transistor is configured to input the reference voltage level, and a second source/drain of the eighth transistor is coupled to the second node.

7. The shift register of claim 1, wherein the second pull-down unit comprises: a ninth transistor, wherein a gate and a first source/drain of the ninth transistor are configured to input the second pull-down control signal; a tenth transistor, wherein a gate of the tenth transistor is configured to input the first pull-down control signal, a first source/drain of the tenth transistor is configured to input the reference voltage level, and a second source/drain of the tenth transistor is coupled to the second source/drain of the ninth transistor; an eleventh transistor, wherein a gate of the eleventh transistor is coupled to the first node, a first source/drain of the eleventh transistor is configured to input the reference voltage level, and a second source/drain of the eleventh transistor is coupled to the second source/drain of the ninth transistor; a twelfth transistor, wherein a gate of the twelfth transistor is coupled to the second source/drain of the eleventh transistor, a first source/drain of the twelfth transistor is configured to input the reference voltage level, and a second source/drain of the twelfth transistor is coupled to the first node; and a thirteenth transistor, wherein a gate of the thirteenth transistor is coupled to the second source/drain of the eleventh transistor, a first source/drain of the thirteenth transistor is configured to input the reference voltage level, and a second source/drain of the thirteenth transistor is coupled to the second node.

8. A display device, comprising: a display panel; and a shift register configured to drive the display panel, the shift register comprising: a pre-charge unit configured to receive a first input signal and a second input signal and output a pre-charge signal via a first node based on the first input signal and the second input signal; a pull-up unit that is coupled to the pre-charge unit, the pull-up unit configured to receive the pre-charge signal and a clock signal and output a scan signal via a second node based on the pre-charge signal and the clock signal; a first pull-down unit coupled to the pre-charge unit and the pull-up unit, the first pull-down unit configured to receive the pre-charge signal, a first pull-down control signal and a second pull-down control signal and control whether to pull down the scan signal to a reference voltage level based on the pre-charge signal, the first pull-down control signal and the second pull-down control signal; and a second pull-down unit coupled to the pre-charge unit and the pull-up unit, the second pull-down unit configured to receive the pre-charge signal, the first pull-down control signal and the second pull-down control signal and control whether to keep the scan signal at the reference voltage level based on the pre-charge signal, the first pull-down control signal and the second pull-down control signal; wherein a period of the first pull-down control signal and a period of the second pull-down control signal are in a range from 12 frames to 180 frames, and a time interval between a rising edge of the first pull-down control signal and a falling edge of the second pull-down control signal is in a range from 2 microseconds to 4 microseconds.

9. The display device of claim 8, wherein the period of the first pull-down control signal is substantially the same as the period of the second pull-down control signal, and the period of the first pull-down control signal and the period of the second pull-down control signal are 120 frames.

10. A display device, comprising: a display panel; and a gate driver configured to drive the display panel and having 1.sup.st-N.sup.th stage shift registers, wherein the i.sup.th stage shift register of the 1.sup.st-N.sup.th stage shift registers comprises: a pre-charge unit configured to receive a first input signal and a second input signal and output a pre-charge signal via a first node based on the first input signal and the second input signal; a pull-up unit that is coupled to the pre-charge unit, the pull-up unit configured to receive the pre-charge signal and a clock signal of a plurality of first clock signals and output an i.sup.th stage scan signal via a second node based on the pre-charge signal and the clock signal; a first pull-down unit coupled to the pre-charge unit and the pull-up unit, the first pull-down unit configured to receive the pre-charge signal, a first pull-down control signal and a second pull-down control signal and control whether to pull down the i.sup.th stage scan signal to a reference voltage level based on the pre-charge signal, the first pull-down control signal and the second pull-down control signal; and a second pull-down unit coupled to the pre-charge unit and the pull-up unit, the second pull-down unit configured to receive the pre-charge signal, the first pull-down control signal and the second pull-down control signal and control whether to keep the i.sup.th stage scan signal at the reference voltage level based on the pre-charge signal, the first pull-down control signal and the second pull-down control signal; wherein a period of the first pull-down control signal and a period of the second pull-down control signal are in a range from 12 frames to 180 frames, a time interval between a rising edge of the first pull-down control signal and a falling edge of the second pull-down control signal is in a range from 2 microseconds to 4 microseconds, N is an integer, and i is an integer from 1 to N.

11. The display device of claim 10, wherein the period of the first pull-down control signal is substantially the same as the period of the second pull-down control signal, and the period of the first pull-down control signal and the period of the second pull-down control signal are 120 frames.

12. The display device of claim 10, wherein the pre-charge unit of the i.sup.th stage shift register comprises: a first transistor, wherein a gate of the first transistor is configured to receive a first input signal, a first source/drain of the first transistor is configured to receive a forward input signal, and a second source/drain of the first transistor is configured to output the pre-charge signal; and a second transistor, wherein a gate and a first source/drain of the second transistor are configured to receive a second input signal, and a second source/drain of the second transistor is coupled to the second source/drain of the first transistor; wherein: when i is 1 or 2 ,the first input signal is a starting signal, and the second input signal is an (i+2).sup.th stage scan signal outputted by the (i+2).sup.th stage shift register of the 1.sup.st-N.sup.th stage shift registers; when i is (N1) or N, the first input signal is an (i2)th stage scan signal outputted by the (i2)th stage shift register of the 1.sup.st-N.sup.th stage shift registers, and the second input signal is an ending signal; when i is from 3 to (N2), the first input signal is an (i2).sup.th stage scan signal outputted by the (i2).sup.th stage shift register of the 1.sup.st-N.sup.th stage shift registers, and the second input signal is an (i+2).sup.th stage scan signal outputted by the (i+2).sup.th stage shift register of the 1.sup.st-N.sup.th stage shift registers.

13. The display device of claim 10, wherein the pre-charge unit of the i.sup.th stage shift register comprises: a first transistor, wherein a gate of the first transistor is configured to receive a first input signal, a first source/drain of the first transistor is configured to receive a forward input signal, and a second source/drain of the first transistor is configured to output the pre-charge signal; and a second transistor, wherein a gate of the second transistor is configured to receive a second input signal, a first source/drain of the second transistor is configured to receive a backward input signal, and a second source/drain of the second transistor is coupled to the second source/drain of the first transistor; wherein: when i is 1 or 2, the first input signal is a starting signal, and the second input signal is an (i+2).sup.th stage scan signal outputted by the (i+2).sup.th stage shift register of the 1.sup.st-N.sup.th stage shift registers; when i is (N1) or N, the first input signal is an (i2).sup.th stage scan signal outputted by the (i2).sup.th stage shift register of the 1.sup.st-N.sup.th stage shift registers, and the second input signal is an ending signal; when i is from 3 to (N2), the first input signal is an (i2).sup.thstage scan signal outputted by the (i2).sup.th stage shift register of the 1.sup.st-N.sup.th stage shift registers, and the second input signal is an (i+2).sup.th stage scan signal outputted by the (i+2).sup.th stage shift register of the 1.sup.st-N.sup.th stage shift registers.

14. The display device of claim 10, wherein the pull-up unit of the i.sup.th stage shift register comprises: a third transistor, wherein a gate of the third transistor is configured to receive the pre-charge signal, a first source/drain of the third transistor is configured to receive the clock signal, and a second source/drain of the third transistor is configured to output the scan signal; and a capacitor, wherein a first terminal of the capacitor is coupled to the gate of the third terminal, and a second terminal of the capacitor is coupled to the second source/drain of the third transistor.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The foregoing aspects and many of the accompanying advantages of this invention will become more readily appreciated as the same becomes better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings.

(2) FIG. 1 is a schematic diagram of a display device in accordance with some embodiments of the invention.

(3) FIG. 2 is a schematic structural diagram of a gate driving circuit in accordance with some embodiments of the invention.

(4) FIG. 3 is an equivalent circuit diagram of a shift register of the gate driving circuit in FIG. 2.

(5) FIG. 4 is a time sequential diagram of pull-down control signals in FIG. 3.

(6) FIG. 5 is a schematic diagram of another display device in accordance with some embodiments of the invention.

(7) FIG. 6 is a schematic structural diagram of a gate driving circuit in accordance with some embodiments of the invention.

(8) FIG. 7 is an equivalent circuit diagram of a shift register of the gate driving circuit in FIG. 6.

DETAILED DESCRIPTION OF THE INVENTION

(9) The detailed explanation of the invention is described as following. The described preferred embodiments are presented for purposes of illustrations and description, and they are not intended to limit the scope of the invention.

(10) Please refer to FIG. 1, which is a schematic diagram of a display device 100 in accordance with some embodiments of the invention. The display device 100 includes a display panel 110, a source driver 120 and a gate driver 130. The display panel 110 includes pixels arranged in a matrix for collectively displaying an image. The display panel 110 may be, for example, a liquid crystal display (LCD) panel of twisted nematic (TN) mode, in-plane switching (IPS) mode, fringe-field switching (FFS) mode, vertical alignment (VA) mode or other different modes, or an organic light-emitting diode (OLED) display panel. The source driver 120 is electrically connected to the display panel 110, and is configured to convert image data into source driving signals and transmit the source driving signals to the display panel 110. The gate driver 130 is configured to generate gate driving signals and transmit the gate driving signals to the display panel 110. The display panel 110 displays an image by the driving of the source driving signals and the gate driving signals.

(11) Please refer to FIG. 2, which is a schematic structural diagram of a gate driving circuit 200 in accordance with some embodiments of the invention. The gate driving circuit 200 is applicable to the display device 100 of FIG. 1 or another similar display device. In the following, the display device 100 of FIG. 1 is exemplified for description. The gate driving circuit 200 is a part of the gate driver 130. The gate driving circuit 200 includes clock signal lines L1-L4, a starting signal line S, an ending signal line R and N stage shift registers 210(1)-210(N), where N is an integer greater than or equal to 5. In some embodiments, N is a multiple of 4. The clock signal lines L1-L4 are respectively configured to provide clock signals C1-C4 for the corresponding shift registers 210(1)-210(N). In FIG. 2, the clock signal lines L1-L4 respectively provide the clock signals C1-C4 to the corresponding shift registers 210(1)-210(N). In addition, the starting signal line S provides a starting signal STV to the 1.sup.st stage shift register 210(1) and the 2.sup.nd stage shift register 210(2), and the ending signal line R provides an ending signal RSTV to the (N-1).sup.th stage shift register 210(N-1) and the N.sup.th stage shift register 210(N). The shift registers 210(1)-210(N) respectively generate scan signals OUT(1)-OUT(N). The scan signals OUT(1) and OUT(2) are respectively inputted to the 3.sup.rd stage shift registers 210(3) ant the 4.sup.th stage shift register 210(4), the scan signals OUT(N-1) and OUT(N) are respectively inputted to the (N-3).sup.th stage shift register 210(N-3) and the (N-2).sup.th stage shift register 210(N-2), and each of the other scan signals OUT(3)-OUT(N-2) is inputted to the shift registers previous two stage of shift register thereto and next two stage of shift register thereto. For illustration, the scan signal OUT(3) is inputted to the 1.sup.st stage shift register 210(1) and the 5.sup.th stage shift register 210(5).

(12) FIG. 3 is an equivalent circuit diagram of the i.sup.th stage shift register 210(i) of the gate driving circuit 200 in FIG. 2, where i is an integer from 1 to N. The i.sup.th stage shift register 210(i) includes a pre-charge unit 310, a pull-up unit 320, a first pull-down unit 330 and a second pull-down unit 340.

(13) The pre-charge unit 310 is configured to receive input signals IN1 and IN2, and outputs a pre-charge signal via the node X based on the input signals IN1 and IN2. The pre-charge unit 310 includes transistors M1 and M2. In this embodiment, the gate driving circuit 200 performs one-way scanning, and in each of the shift registers 210(1)-210(N), the gate of the transistor M1 is configured to receive the input signal IN1, the first source/drain of the transistor M1 is configured to receive a forward input signal FW, and the second source/drain of the transistor M1 is configured to output the pre-charge signal. The gate and the first source/drain of the transistor M2 is configured to receive the input signal IN2, and the second source/drain of the transistor M2 is coupled to the second source/drain of the transistor M1.

(14) If the shift register 210(i) is the 1.sup.st stage shift register 210(1) or the 2.sup.nd stage shift register 210(2), the input signal IN1 is the starting signal STV, and the input signal IN2 is the scan signal OUT(i+2) outputted by the (i+2).sup.th stage shift register 210(i+2). If the shift register 210(i) is one of the 3.sup.rd stage shift register 210(3) to the (N-2).sup.th stage shift register 210(N-2), the input signal IN1 is the scan signal OUT(i-2) outputted by the (i-2).sup.th stage shift register 210(i-2), and the input signal IN2 is the scan signal OUT(i+2) outputted by the (i+2).sup.th stage shift register 210(i+2). If the shift register 210(i) is the (N-1).sup.th stage shift register 210(N-1) or the N.sup.th stage shift register 210(N), the input signal IN1 is the scan signal OUT(i-2) outputted by the (i-2).sup.th stage shift register 210(i-2), and the input signal IN2 is the ending signal RSTV.

(15) The pull-up unit 320 is coupled to the pre-charge unit 310, and is configured to receive the pre-charge signal and a clock signal CN and output the scan signal OUT(i) via the node Y based on the pre-charge signal and the clock signal CN, in which the clock signal CN is one of the clock signals C1-C4. The pull-up unit 320 includes a transistor M3 and a capacitor Cx. The gate of the transistor M3 is configured to receive the pre-charge signal, the first source/drain of the transistor M3 is configured to receive the clock signal CN, and the second source/drain of the transistor M3 is configured to output the scan signal OUT(i). The first terminal of the capacitor Cx is coupled to the gate of the transistor M3, and the second terminal of the capacitor Cx is coupled to the second source/drain of the transistor M3.

(16) The first pull-down unit 330 is coupled to the pre-charge unit 310 and the pull-up unit 320. The first pull-down unit 330 is configured to receive the pre-charge signal and the pull-down control signals GPW1 and GPW2 and control whether to pull down the scan signal OUT(i) to the reference voltage level VGL based on the pre-charge signal and the pull-down control signals GPW1 and GPW2. The first pull-down unit 330 includes transistors M4-M8. The transistors M4-M8 can be amorphous silicon (a-Si) TFTs or low temperature polysilicon (LTPS) TFTs, but are not limited thereto. The gate and the first source/drain of the transistor M4 are configured to input the pull-down control signal GPW1. The gate of the transistor M5 is configured to input the pull-down control signal GPW2, the first source/drain of the transistor M5 is coupled to input the reference voltage level VGL, and the second source/drain of the transistor M5 is coupled to the second source/drain of the transistor M4. The gate of the transistor M6 is coupled to the node X, the first source/drain of the transistor M6 is configured to input the reference voltage level VGL, and the second source/drain of the transistor M6 is coupled to the second source/drain of the transistor M4. The gate of the transistor M7 is coupled to the second source/drain of the transistor M6, the first source/drain of the transistor M7 is configured to input the reference voltage level VGL, and the second source/drain of the transistor M7 is coupled to the node X. The gate of the transistor M8 is coupled to the second source/drain of the transistor M6, the first source/drain of the transistor M8 is configured to input the reference voltage level VGL, and the second source/drain of the transistor M8 is coupled to the node Y. When the voltage level of the pull-down control signal GPW1 is low and the voltage level of the pull-down control signal GPW2 is high, the voltage level of the node P is low. When the voltage level of the pull-down control signal GPW1 is high and the voltage level of the pull-down control signal GPW2 is low, the voltage level of the node P is high.

(17) The second pull-down unit 340 is coupled to the pre-charge unit 310 and the pull-up unit 320. The second pull-down unit 340 is configured to receive the pre-charge signal and the pull-down control signals GPW1 and GPW2 and control whether to keep the scan signal OUT(i) at the reference voltage level VGL based on the pre-charge signal and the pull-down control signals GPW1 and GPW2. The second pull-down unit 340 includes transistors M9-M13. The transistors M9-M13 can be a-Si TFTs or LTPS TFTs, but are not limited thereto. The gate and the first source/drain of the transistor M9 are configured to input the pull-down control signal GPW2. The gate of the transistor M10 is configured to input the pull-down control signal GPW1, the first source/drain of the transistor M10 is coupled to input the reference voltage level VGL, and the second source/drain of the transistor M10 is coupled to the second source/drain of the transistor M9. The gate of the transistor M11 is coupled to the node X, the first source/drain of the transistor M11 is configured to input the reference voltage level VGL, and the second source/drain of the transistor M11 is coupled to the second source/drain of the transistor M9. The gate of the transistor M12 is coupled to the second source/drain of the transistor M11, the first source/drain of the transistor M12 is configured to input the reference voltage level VGL, and the second source/drain of the transistor M12 is coupled to the node X. The gate of the transistor M13 is coupled to the second source/drain of the transistor M11, the first source/drain of the transistor M13 is configured to input the reference voltage level VGL, and the second source/drain of the transistor M13 is coupled to the node Y. When the voltage level of the pull-down control signal GPW1 is low and the voltage level of the pull-down control signal GPW2 is high, the voltage level of the node Q is high. When the voltage level of the pull-down control signal GPW1 is high and the voltage level of the pull-down control signal GPW2 is low, the voltage level of the node Q is low.

(18) Please refer to FIG. 4, FIG. 4 is a time sequential diagram of the pull-down control signals GPW1 and GPW2 of the i.sup.th stage shift register 210(i) in FIG. 3. When the voltage level of the pull-down control signal GPW1 is low and the voltage level of the pull-down control signal GPW2 is high, the voltage level of the nodes P and Q are respectively low and high. When the voltage level of the pull-down control signal GPW1 is high and the voltage level of the pull-down control signal GPW2 is low, the voltage level of the nodes P and Q are respectively high and low. The period T of the pull-down control signal GPW1 is the sum of the high level duration T1 and the low level duration T2 of the pull-down control signal GPW1. The period T is in a range from 12 frames to 180 frames. For illustration, if the frame rate of the display device 100 is 60 frames per second, the period T is from 0.2 seconds to 3 seconds. The period of the pull-down control signals GPW1 and GPW2 may be the same, and in some embodiments, the period of the pull-down control signals GPW1 and GPW2 is 120 frames. In some embodiments, as shown in FIG. 4, the time interval TD1 between the rising edge of the pull-down control signal GPW1 and the falling edge of the pull-down control signal GPW2 is in a range from 2 microseconds to 4 microseconds. Similarly, the time interval TD2 between the falling edge of the pull-down control signal GPW1 and the rising edge of the pull-down control signal GPW2 is in a range from 2 microseconds to 4 microseconds. Further, in some embodiments, the pull-down control signals GPW1 and GPW2 are substantially phase-inverted from each other. That is, the time interval TD1 between the rising edge of the pull-down control signal GPW1 and the falling edge of the pull-down control signal GPW2 and the time interval TD2 between the falling edge of the pull-down control signal GPW1 and the rising edge of the pull-down control signal GPW2 are substantially 0. In practice, the duration of the time intervals TD1 and TD2 can be correspondingly adjusted in accordance with various design requirements.

(19) By applying the period settings of the invention to the pull-down control signals GPW1 and GPW2, the period of the voltage level at the nodes P and Q can be correspondingly expanded, so as to effectively adjust the threshold voltage of the transistors M6, M8, M11 and M13 to avoid over-shifting. As such, normal operations of the gate driver 130 are ensured, and the reliability and stableness of the display device 100 are improved.

(20) The configuration to the signals in the aforementioned embodiments may also be applied to a display device which is driven simultaneously at left and right sides. Please refer to FIG. 5, which is a schematic diagram of a display device 500 in accordance with some embodiments of the invention. The display device 500 includes a display panel 510, a source driver 520 and gate drivers 530A and 530B. The display device 500 is similar to the display device 100 of FIG. 1. The difference between the display devices 100 and 500 is that the display device 500 includes two gate drivers 530A and 530B. As shown in FIG. 5, the gate drivers 530A and 530B are disposed at the left and right side of the display panel 510, respectively, and collectively transmit gate driving signals to the display panel 510. In another embodiment, the disposal of the gate drivers 530A and 530B may be adjusted in accordance with various design requirements. The display panel 510 and the source driver 520 are approximately the same as the display panel 110 and the source driver 120 of FIG. 1, respectively, and the description is not repeated herein.

(21) Please refer to FIG. 6, which is a schematic structural diagram of gate driving circuits 600A and 600B in accordance with some embodiment of the invention. The gate driving circuits 600A and 600B are applicable to the display device 500 of FIG. 5 or another similar display device. In the following, the display device 500 of FIG. 5 is exemplified for description. The gate driving circuits 600A and 600B are respectively a part of the gate drivers 530A and 530B. The gate driving circuit 600A includes clock signal lines L1-L4, a starting signal line S, an ending signal line R and odd-numbered stage shift registers 610(1), 610(3), . . . , 610(N-1) of N stage shift registers 610(1)-610(N), and the gate driving circuit 600B includes clock signal lines L1-L4, a starting signal line S, an ending signal line R and even-numbered stage shift registers 610(2), 610(4), . . . , 610(N) of the N stage shift registers 610(1)-610(N), where N is an integer greater than or equal to 9. In some embodiments, N is a multiple of 8. The clock signal lines L1-L4 and L1-L4 are configure to respectively provide clock signals C1-C4 and C1-C4 for the corresponding shift registers 610(1)-610(N). In addition, the starting signal line S provides a starting signal SW to the 1.sup.st stage shift register 610(1) and the 3.sup.rd stage shift register 610(3), the starting signal line S provides a starting signal STV' to the 2.sup.nd stage shift register 610(2) and the 4.sup.th stage shift register 610(4), the ending signal line R provides an ending signal RSTV to the (N-3).sup.th stage shift register 610(N-3) and the (N-1).sup.th stage shift register 610(N-1), and the ending signal line R provides an ending signal RSTV' to the (N-2).sup.th stage shift register 610(N-2) and the N.sup.th stage shift register 610(N). The shift registers 610(1)-610(N) respectively generate scan signals OUT(1)-OUT(N). The scan signals OUT(1)-OUT(4) are respectively inputted to the 5.sup.th to 8.sup.th stage shift registers 610(5)-610(8), the scan signals OUT(N-3)-OUT(N) are respectively inputted to the (N-7).sup.th to (N-4).sup.th stage shift registers 610(N-7)-610(N-4), and each of the other scan signals OUT(5)-OUT(N-4) is inputted to the shift registers previous four stage of shift register thereto and next four stage of shift register thereto. For illustration, the scan signal OUT(5) is inputted to the 1.sup.st stage shift register 610(1) and the 9.sup.th stage shift register 610(9).

(22) FIG. 7 is an equivalent circuit diagram of the i.sup.th stage shift register 610(i) of the gate driving circuits 600A and 600B in FIG. 6, where i is an integer from 1 to N. The i.sup.th stage shift register 610(i) includes a pre-charge unit 710, a pull-up unit 720, a first pull-down unit 730 and a second pull-down unit 740.

(23) The pre-charge unit 710 is configured to receive input signals IN1 and IN2, and outputs a pre-charge signal via the node X based on the input signals IN1 and IN2. The pre-charge unit 710 includes transistors M1 and M2. In this embodiment, the gate driving circuits 600A and 600B perform two-way scanning, and in each of the shift registers 610(1)-610(N), the gate of the transistor M1 is configured to receive the input signal IN1, the first source/drain of the transistor M1 is configured to receive a forward input signal FW, and the second source/drain of the transistor M1 is configured to output the pre-charge signal. The gate of the transistor M2 is configured to receive the input signal IN2, the first source/drain of the transistor M2 is configured to receive a backward input signal BW, and the second source/drain of the transistor M2 is coupled to the second source/drain of the transistor M1.

(24) If the shift register 610(i) is one of the 1.sup.st stage shift register 610(1) to the 4.sup.th stage shift register 610(4), the input signal IN1 is the starting signal STV or the starting signal STV, and the input signal IN2 is the scan signal OUT(i+4) outputted by the (i+4).sup.th stage shift register 610(i+4). If the shift register 610(i) is one of the 5.sup.th stage shift register 610(5) to the (N-4).sup.th stage shift register 610(N-4), the input signal IN1 is the scan signal OUT(i-4) outputted by the (i-4).sup.th stage shift register 610(i-4), and the input signal IN2 is the scan signal OUT(i+4) outputted by the (i+4).sup.th stage shift register 610(i+4). If the shift register 610(i) is one of the (N-3).sup.th stage shift register 610(N-3) to the N.sup.th stage shift register 610(N), the input signal IN1 is the scan signal OUT(i-4) outputted by the (i-4).sup.th stage shift register 610(i-4), and the input signal IN2 is the ending signal RSTV or the ending signal RSTV.

(25) The pull-up unit 720, the first pull-down unit 730 and the second pull-down unit 740 are similar to the pull-up unit 320, the first pull-down unit 330 the second pull-down unit 340 of FIG. 3, respectively, and thus the description of the pull-up unit 720, the first pull-down unit 730 and the second pull-down unit 740 may be referred to the preceding paragraphs and is not described again herein.

(26) Please refer to the time sequential diagram shown in FIG. 4 again, the period T of the pull-down control signal GPW1 is in a range from 12 frames to 180 frames. For illustration, if the frame rate of the display device 100 is 60 frames per second, the period T is from 0.2 seconds to 3 seconds. The period of the pull-down control signals GPW1 and GPW2 may be the same, and in some embodiments, the period of the pull-down control signals GPW1 and GPW2 are 120 frames. In some embodiments, as shown in FIG. 4, the time interval TD1 between the rising edge of the pull-down control signal GPW1 and the falling edge of the pull-down control signal GPW2 is in a range from 2 microseconds to 4 microseconds. Similarly, the time interval TD2 between the falling edge of the pull-down control signal GPW1 and the rising edge of the pull-down control signal GPW2 is in a range from 2 microseconds to 4 microseconds. Further, in some embodiments, the pull-down control signals GPW1 and GPW2 are substantially phase-inverted from each other. By applying the period configurations of the invention to the pull-down control signals GPW1 and GPW2, the period of the voltage level at the nodes P and Q can be correspondingly expanded, so as to effectively adjust the threshold voltage of the transistors M6, M8, M11 and M13 to avoid over-shifting. As such, normal operations of the gate drivers 530A and 530B are ensured, and the reliability and stableness of the display device 500 are improved.

(27) It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the invention cover modifications and variations of this invention provided they fall within the scope of the following claims.