Split RDL Connection Between Die and UBM

Abstract

A semiconductor device has a semiconductor die. A first contact pad, second contact pad, and third contact pad are formed over the semiconductor die. An under-bump metallization layer (UBM) is formed over the first contact pad, second contact pad, and third contact pad. The UBM electrically connects the first contact pad to the second contact pad. The third contact pad is electrically isolated from the UBM. Conductive traces can be formed extending between the first contact pad and second contact pad under the UBM. A fourth contact pad can be formed over the first contact pad and a fifth contact pad can be formed over the second contact pad. The UBM is then formed over the fourth and fifth contact pads.

Claims

1. A method of making a semiconductor device, comprising: providing a semiconductor die; forming a first contact pad over the semiconductor die; forming a second contact pad over the semiconductor die; forming a third contact pad over the semiconductor die; and forming an under-bump metallization layer (UBM) over the first contact pad, second contact pad, and third contact pad, wherein the UBM electrically connects the first contact pad to the second contact pad and the third contact pad is electrically isolated from the UBM.

2. The method of claim 1, further including forming a conductive trace extending between the first contact pad and second contact pad under the UBM.

3. The method of claim 1, further including forming an insulating layer over the first contact pad and second contact pad comprising a buffer feature of the insulating layer disposed over the first contact pad.

4. The method of claim 1, further including: forming a fourth contact pad over the first contact pad; forming a fifth contact pad over the second contact pad; and forming the UBM over the fourth contact pad and fifth contact pad.

5. The method of claim 4, further including: forming a first conductive trace between the first contact pad and second contact pad; and forming a second conductive trace between the fourth contact pad and fifth contact pad.

6. The method of claim 1, further including forming a buffer conductive layer between the semiconductor die and first contact pad.

7. A method of making a semiconductor device, comprising: providing a semiconductor die; forming a first contact pad over the semiconductor die; forming a second contact pad over the semiconductor die; and forming an under-bump metallization layer (UBM) over the first contact pad and second contact pad.

8. The method of claim 7, further including forming a conductive trace extending between the first contact pad and second contact pad under the UBM.

9. The method of claim 7, further including forming an insulating layer over the first contact pad and second contact pad comprising a buffer feature of the insulating layer disposed over the first contact pad.

10. The method of claim 7, further including: forming a third contact pad over the first contact pad; forming a fourth contact pad over the second contact pad; and forming the UBM over the third contact pad and fourth contact pad.

11. The method of claim 7, further including forming a buffer conductive layer between the semiconductor die and first contact pad.

12. The method of claim 7, further including forming a third contact pad under the UBM, wherein the UBM electrically connects the first contact pad to the second contact pad and the third contact pad is electrically isolated from the UBM.

13. The method of claim 7, further including a solder bump formed over the UBM.

14. A semiconductor device, comprising: a semiconductor die; a first contact pad formed over the semiconductor die; a second contact pad formed over the semiconductor die; a third contact pad formed over the semiconductor die; and an under-bump metallization layer (UBM) formed over the first contact pad, second contact pad, and third contact pad, wherein the UBM electrically connects the first contact pad to the second contact pad and the third contact pad is electrically isolated from the UBM.

15. The semiconductor device of claim 14, further including a conductive trace extending between the first contact pad and second contact pad under the UBM.

16. The semiconductor device of claim 14, further including an insulating layer formed over the first contact pad and second contact pad comprising a buffer feature of the insulating layer disposed over the first contact pad.

17. The semiconductor device of claim 14, further including: a fourth contact pad formed over the first contact pad; and a fifth contact pad formed over the second contact pad, wherein the UBM is formed over the fourth contact pad and fifth contact pad.

18. The semiconductor device of claim 17, further including: a first conductive trace formed between the first contact pad and second contact pad; and a second conductive trace formed between the fourth contact pad and fifth contact pad.

19. The semiconductor device of claim 14, further including a buffer conductive layer formed between the semiconductor die and first contact pad.

20. A semiconductor device, comprising: a semiconductor die; a first contact pad formed over the semiconductor die; a second contact pad formed over the semiconductor die; and an under-bump metallization layer (UBM) formed over the first contact pad and second contact pad.

21. The semiconductor device of claim 20, further including a conductive trace extending between the first contact pad and second contact pad under the UBM.

22. The semiconductor device of claim 20, further including an insulating layer formed over the first contact pad and second contact pad comprising a buffer feature of the insulating layer disposed over the first contact pad.

23. The semiconductor device of claim 20, further including: a third contact pad formed over the first contact pad; and a fourth contact pad formed over the second contact pad, wherein the UBM is formed over the third contact pad and fourth contact pad.

24. The semiconductor device of claim 20, further including a buffer conductive layer formed between the semiconductor die and first contact pad.

25. The semiconductor device of claim 20, further including a third contact pad formed under the UBM, wherein the UBM electrically connects the first contact pad to the second contact pad and the third contact pad is electrically isolated from the UBM.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0014] FIGS. 1a-1c illustrate a semiconductor wafer with a plurality of semiconductor die separated by a saw street;

[0015] FIG. 2 illustrates RDL and UBM formed over one of the semiconductor die;

[0016] FIGS. 3a-3c illustrate split RDL pads;

[0017] FIG. 4 illustrates multiple split RDL layers;

[0018] FIGS. 5a and 5b illustrate insulating layers with buffer features;

[0019] FIGS. 6a-6c illustrate additional buffer layer embodiments; and

[0020] FIG. 7 illustrates a conductive layer buffer.

DETAILED DESCRIPTION OF THE DRAWINGS

[0021] The present invention is described in one or more embodiments in the following description with reference to the figures, in which like numerals represent the same or similar elements. While the invention is described in terms of the best mode for achieving the invention's objectives, it will be appreciated by those skilled in the art that it is intended to cover alternatives, modifications, and equivalents as may be included within the spirit and scope of the invention as defined by the appended claims and their equivalents as supported by the following disclosure and drawings. The term “semiconductor die” as used herein refers to both the singular and plural form of the words, and accordingly, can refer to both a single semiconductor device and multiple semiconductor devices.

[0022] FIG. 3a shows a cross-sectional view of semiconductor die 104 with an RDL and UBM formed over active surface 110. An insulating layer 200 is formed over semiconductor die 104 and passivation layer 130. In some embodiments, semiconductor die 104 is a semiconductor die embedded in encapsulant, or an encapsulant is deposited around semiconductor die 104 and passivation layer 130 after singulation, and then insulating layer 200 is also formed over the encapsulant. Insulating layer 200 contains one or more layers of silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), tantalum pentoxide (Ta2O5), aluminum oxide (A12O3), solder resist, polyimide, benzocyclobutene (BCB), polybenzoxazoles (PBO), polymer matrix composite with a filler such as Ajinomoto build-up film (ABF) or molding compound, and other material having similar insulating and structural properties. Insulating layer 200 is formed using spin coating, sputtering, lamination, molding, or any other suitable process. Openings are formed through insulating layer 200 over die pads 112 using photolithography or another suitable patterning process.

[0023] Conductive layer 202 is formed over insulating layer 200. Conductive layer 202 can be one or more layers of Al, Cu, Ti/Cu, TiW/Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. Conductive layer 202 is formed using PVD, CVD, electrolytic plating, electroless plating process, or other suitable metal deposition process. Conductive layer 202 is patterned into a pair of UBM connecting contact pads 204a and 204b, an RDL contact pad 206, conductive traces 208 routing around contact pads 204a and 204b, and conductive traces 210 routing between contact pads 204.

[0024] Insulating layer 220 is formed over conductive layer 202 and insulating layer 200. Insulating layer 220 is formed of similar materials and in a similar manner to insulating layer 200. Openings are formed through insulating layer 220 over contact pads 204a and 204b to expose the contact pads for a subsequent UBM formation.

[0025] UBM 222 is formed over insulating layer 220 and into the openings exposing contact pads 204a and 204b. UBM 222 is formed in a similar manner and of similar materials to conductive layer 202. In one embodiment, UBM 222 includes a wetting layer, barrier layer, and adhesion layer with differing alloy compositions. UBM 222 physically contacts contact pads 204a and 204b in the openings of insulating layer 220. Contact pads 204a and 204b connect UBM 222 to die pads 112a and 112c in parallel, but conductive layer 202 does not otherwise connect contact pad 204a to contact pad 204b or die pad 112a to die pad 112c. UBM 222 electrically couple contact pads 204a and 204b to each other, thus the UBM operates as an RDL coupling die pads 112a and 112c to each other.

[0026] An electrically conductive bump material is deposited over UBM 222 using an evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, with an optional flux solution. For example, the bump material can be eutectic Sn/Pb, high-lead solder, or lead-free solder. The bump material is bonded to UBM 222 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form balls or bumps 224. Bump 224 can also be compression bonded or thermocompression bonded to UBM 222.

[0027] Conductive layer 202 includes a gap between contact pads 204a and 204b that allows for routing of conductive traces and placement of additional contact pads under UBM 222, whereas in the prior art the entire area under UBM was occupied by an RDL contact pad sized the same as the UBM. FIG. 3b shows a plan view of conductive layer 202. Instead of having an RDL with one large contact pad covering both die pads 112a and 112c, a pair of contact pads 204 is formed to interconnect between die 104 and UBM 222. Split contact pads 204a and 204b alleviate routing requirements for RDL because conductive traces 210 can now be routed between the split contact pads without directly connecting to the contact pads. Die pad 112b is usable even with an overlying UBM because contact pad 206 can be formed as part of conductive layer 202 without interference from a large contact pad big enough to cover both die pads 112a and 112c. Split contact pads 204a and 204b allows other contact pads 206 to be formed over die pads 112 that are under the UBM and were unusable in the prior art. While die pad 112b is shown as being directly between die pads 112a and 112b, die pad 112b and contact pad 206 could be anywhere within the footprint of UBM 222 and the same benefit applies.

[0028] Rather than requiring an RDL layer such as conductive layer 202 to connect die pads 112a and 112c as in the prior art, UBM 222 operates as the RDL to connect the die pads to each other. Using UBM 222 as an RDL solves the problem of having underlying conductive layers cross each other to both connect die pads 112a and 112c to each other and route conductive traces 210 under the UBM. Connecting multiple die pads 112 to UBM 222 in parallel also has the benefit of reducing circuit resistance from die 104 to the UBM. Reducing resistance reduces voltage drop, heat generation, and power consumption and ensures that semiconductor die 104 remains in good condition for a longer lifetime. UBM 222 connects die pads 112 to each other horizontally while conductive layer 202 connects die pads 112 to the UBM vertically. UBM 222 acts as a metal bridge to bypass other RDL patterns underneath the UBM and connects die pads 112 from different locations to each other.

[0029] While two die pads 112 are connected to UBM 222 in parallel, any number of die pads can be vertically routed to the UBM through conductive layer 202 by using discrete contact pads 204 instead of one large contact pad. The die pads 112 are not connected to each other through conductive layer 202, but only through UBM 222 and potentially also by die 104. In other embodiments, two die pads 112 can be connected to each other and to UBM 222 by one contact pad 204, while a third die pad 112 is connected in parallel to the UBM through a separate contact pad 204. FIG. 3c shows another embodiment with a rectangular UBM 232. A UBM can be any suitable shape and formed over any number of individually or separately connected die pads 112.

[0030] While FIG. 3a shows only a single RDL layer, i.e., conductive layer 202, between die pads 112 and UBM 222, any suitable number of RDL layers can be stacked to allow for more complex signal routing. FIG. 4 shows a second conductive layer 252 formed over conductive layer 202 as a second RDL layer. Insulating layer 220 has openings formed to expose contact pads 204 and 206. Conductive layer 252 includes two contact pads 254a and 254b corresponding to and stacked on contact pads 204a and 204b. Another contact pad 256 is formed between contact pads 254a and 254b and under the eventual footprint of UBM 222. Contact pad 256 is formed directly over and stacked on contact pad 206 but could also be formed laterally offset and connected by a conductive trace. Conductive traces 260 are routed between contact pads 254a and 254b without being directly electrically connected to contact pads 254a and 254b. Conductive traces 258 are routed outside of contact pads 254a and 254b.

[0031] Insulating layer 262 is formed over conductive layer 252. Openings are formed in insulating layer 262 to expose contact pads 254a and 254b. Contact pad 256 remains covered by insulating layer 262 and is connected elsewhere within the die 104 floorplan by conductive traces 258 and 260. UBM 222 is formed over insulating layer 262 and extends into the openings of insulating layer 262 onto contact pads 254a and 254b. Solder bump 224 is formed on UBM 222.

[0032] Contact pads 204a and 254a are stacked to form one vertical conductive path from die 104 to UBM 222. Contact pads 204b and 254b are stacked to form a second vertical conductive path from die 104 to UBM 222 in parallel with the first path. Contact pads 204a and 254a electrically connect die pad 112a to UBM 222 in series with each other, and in parallel with contact pads 204b and 254b connecting the UBM to die pad 112c. Having separate vertical paths for individual die pads 112 instead of one large pad over multiple die pads allows additional routing flexibility because conductive traces 210 and 230 can be routed between the vertical stacks. Having double layered contact pads connecting UBM 222 in parallel provides even more flexible routing because two layers of conductive traces can be formed through the area between die pads 112a and 112c. Any number of RDL layers can have vertically stacked contact pads to provide split signal routing between die pads 112 and UBM 222.

[0033] FIGS. 5a and 5b illustrate passivation buffers formed over contact pads 204a and 204b. Insulating layer 220 is patterned to form a peninsula 270 over contact pad 204a and an island 272 over contact pad 204b. Any combination of buffers peninsulas and islands can be used on any number of contact pads, but one of each is shown for purposes of illustration. Peninsula 270 could also be formed extending completely across contact pad 204a, which would form a bridge to bisect the contact pad into two discrete exposed portions. Contact pad 204a is optionally elongated in a direction perpendicular to peninsula 270 to create more surface area on either side of the peninsula.

[0034] Peninsula 270 and island 272 are passivation buffers that help relieve physical pressure between UBM 222 and die 104, thus improving resilience to thermal cycling and other physical pressures on semiconductor die 104. Stacked via structures such as vias 204 and 254 have better electrical characteristics than having horizontal conductive traces connecting one via to the other, but also creates higher physical stress at the interface between layers that can cause delamination. The buffers reduce interface stress between conductive layers, including between the top conductive layer and UBM 222.

[0035] FIGS. 6a and 6b illustrate passivation buffers formed over contact pads 254a and 254b. Insulating layer 262 is patterned to form a peninsula 274 over contact pad 254a and an island 276 over contact pad 254b. Both buffers could be peninsulas or islands, but one of each is shown for purposes of illustration. When more than two contact pads 254 are formed over die 104, any combination of islands and peninsulas can be used. Contact pad 254a is optionally elongated in a direction perpendicular to peninsula 274 to create more surface area on the sides of the peninsula.

[0036] FIG. 6c shows a bridge 280 bisecting contact pad 254a into two discrete exposed portions. Contact pad 254a is elongated perpendicularly to bridge 280 in other embodiments to increase the size of the discrete exposed portions. Any combination of bridges, peninsulas, and islands can be used on any of the stacked contact pads of conductive layers 202 and 252 as buffer layers to relieve physical pressure between UBM 222 and die 104. Both conductive layer 202 and conductive layer 252 could have buffers on their respective contact pads. The buffers reduce interface stress between conductive layers.

[0037] FIG. 7 illustrates a buffer conductive layer 290 formed between die pads 112 and conductive layer 202. Conductive layer 290 is typically formed from a softer metal, such as copper, to add some flexibility into the contact pad stacks. The slight compressibility of conductive layer 290 helps relieve some of the physical stress on stacked contact pads 204 and 254. The interface between contact pads 204, which are typically aluminum, and die pads 112 can commonly be the weakest link in the stack. Conductive layer 290 includes contact pads 290 and traces 290b. Adding a copper layer between contact pads 204 and die pads 112 increases reliability.

[0038] After encapsulating die 104, building up all desired RDL layers, forming all desired UBM 222 and solder bumps 224, and performing any other desired packaging steps, a completed semiconductor package with semiconductor die 104 is formed. The semiconductor package can be any suitable type of package, e.g., multi-chip module (MCM), system-in-package (SiP) module, ball grid array (BGA), or embedded wafer-level ball grid array (eWLB). In the completed package, one or more solder bumps 224 are exposed to allow subsequent integration into a larger electrical system. A device manufacturer will integrate the package by picking and placing the package over a larger substrate and reflowing solder bumps 224 onto contact pads of the larger substrate.

[0039] While one or more embodiments of the present invention have been illustrated in detail, the skilled artisan will appreciate that modifications and adaptations to those embodiments may be made without departing from the scope of the present invention as set forth in the following claims.