Signal generator with self-calibration

Abstract

The present disclosure relates to a signal generator with self-calibration including a main digital-to-analog converter (DAC), a calibration DAC, a summing buffer structure, a two-path filter structure, an analog-to-digital converter (ADC), and a control system. The main DAC provides a main DAC output signal with main DAC distortion. The main DAC output signal is calibrated by a calibration DAC output signal to correct at least a portion of the main DAC distortion. The calibration DAC output signal includes information about the main DAC distortion and is generated by a feedback loop including the summing buffer structure, the two-path filter structure, the filter buffer, the ADC, the control system, and the calibration DAC.

Claims

1. A signal generator comprising: a main digital-to-analog converter (DAC) providing a main DAC output signal with main DAC distortion; a calibration DAC providing a calibration DAC output signal, which includes information about the main DAC distortion; a summing buffer structure configured to sum the main DAC output signal and the calibration DAC output signal and provide a summing output signal, which corrects at least a portion of the main DAC distortion; a two-path filter structure including a first filter path and a second filter path, wherein: when the first filter path is conducted, the two-path structure is configured to provide a first filter output signal based on the summing output signal; and when the second filter path is conducted, the two-path structure is configured to provide a second filter output signal based on the summing output signal; an analog-to-digital converter (ADC) providing a first ADC output signal based on the first filter output signal and providing a second ADC output signal based on the second filter output signal; and a control system coupled between the ADC and the calibration DAC, wherein: the control system is configured to provide a calibration DAC input signal to the calibration DAC to update the calibration DAC output signal, wherein the updated calibration DAC output signal includes updated information about the main DAC distortion; and the calibration DAC input signal is calculated from the first ADC output signal and the second ADC output signal.

2. The signal generator of claim 1 wherein the summing output signal corrects at least 95% of the main DAC distortion.

3. The signal generator of claim 1 wherein the control system includes at least one of a group consisting of a microcontroller, application specific integrated circuit (ASIC), and a computer.

4. The signal generator of claim 1 wherein the control system is embedded in a same printed circuit board (PCB) as the main DAC, the ADC, and the calibration DAC.

5. The signal generator of claim 1 wherein the control system is off a PCB board, in which the main DAC, the ADC, and the calibration are embedded.

6. The signal generator of claim 1 wherein the control system includes a first portion and a second portion, wherein: a first portion of the control system is embedded in a same PCB as the main DAC, the ADC, and the calibration DAC; and a second portion of the control system is off the PCB board.

7. The signal generator of claim 1 wherein the control system is configured to selectively conduct the first filter path and the second filter path.

8. The signal generator of claim 1 wherein the summing buffer structure comprises a summing unit and an operational amplifier (op-amp) buffer coupled to the summing unit, wherein the summing unit is configured to receive the main DAC output signal and the calibration DAC output signal and the op-amp buffer is configured to provide the summing output signal.

9. The signal generator of claim 1 further comprising a filter buffer coupled between the two-path filter structure and the ADC.

10. The signal generator of claim 9 wherein the filter buffer is an op-amp buffer.

11. The signal generator of claim 1 wherein the first filter path comprises a low-pass filter and the second filter path comprises a signal attenuator.

12. The signal generator of claim 11 wherein the signal attenuator is frequency independent.

13. The signal generator of claim 11 wherein the signal attenuator is frequency dependent.

14. The signal generator of claim 1 wherein the first filter path comprises a first signal attenuator and the second filter path comprises a second signal attenuator, wherein the first signal attenuator and the second signal attenuator are different.

15. The signal generator of claim 1 wherein the first filter path comprises a first low-pass filter and the second filter path comprises a second low-pass filter, wherein the first low-pass filter and the second low-pass filter are different.

16. The signal generator of claim 1 wherein the first low-pass filter and the second low-pass filter have a same order.

17. The signal generator of claim 1 wherein the first low-pass filter and the second low-pass filter have different orders.

18. The signal generator of claim 1 further comprises a signal attenuator coupled between the calibration DAC and the summing buffer structure.

19. The signal generator of claim 18 wherein the signal attenuator is a voltage divider.

20. The signal generator of claim 1 wherein the main DAC, the calibration DAC, and the ADC have a same resolution.

21. The signal generator of claim 1 wherein the main DAC, the calibration DAC, and the ADC have different resolutions.

22. A method comprising: generating a main digital-to-analog converter (DAC) output signal by a main DAC, wherein the main DAC output signal has main DAC distortion; generating a summing output signal by a summing buffer structure, wherein the summing output signal is generated based on the main DAC output signal and a calibration DAC output signal that equals to zero; sequentially generating a first filter output signal and a second filter output signal by a two-path filter structure that includes a first filter path and a second filter path, wherein the first filter output signal is generated when the first filter path is conducted, and the second filter output signal is generated when the second filter path is conducted; sequentially generating a first analog-to-digital converter (ADC) output signal and a second ADC output signal by an ADC, wherein: the first ADC output signal is generated based on the first filter output signal, and the second ADC output signal is generated based on the second filter output signal; and each of the first ADC output signal and the second ADC output signal includes both the main DAC distortion and ADC distortion from the ADC; generating a calibration DAC input signal by a control system, wherein the calibration DAC input signal includes information about the main DAC distortion; updating the calibration DAC output signal by the calibration DAC, wherein the updated calibration DAC output signal is calculated based on the calibration DAC input signal; and calibrating the main DAC output signal with the updated calibration DAC output signal to correct at least a portion of the main DAC distortion.

23. The method of claim 22 wherein generating the calibration DAC input signal is provided by: separating the main DAC distortion and the ADC distortion based on the first ADC output signal and the second ADC output signal; and calculating the calibration DAC input signal based on the main DAC distortion.

24. The method of claim 22 wherein the main DAC output signal and the updated calibration DAC output signal have inverted phases.

25. The method of claim 22 further comprising selectively conducting the first filter path and the second filter path by the control system.

26. The method of claim 22 wherein generating the calibration DAC input signal is implemented by a first portion of the control system, which is a microcontroller embedded in a same PCB as the main DAC, the ADC, and the calibration DAC.

27. The method of claim 22 wherein generating the calibration DAC input signal is implemented by a first portion of the control system, which is a computer off a PCB that the main DAC, the ADC, and the calibration are embedded in.

Description

BRIEF DESCRIPTION OF THE DRAWING FIGURES

(1) The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure.

(2) FIG. 1 shows an exemplary signal generator according to one embodiment of the present disclosure.

(3) FIG. 2 provides a flow diagram that illustrates an exemplary operation process to generate a high purity-level signal by the signal generator illustrated in FIG. 1.

(4) It will be understood that for clear illustrations, FIGS. 1-2 may not be drawn to scale.

DETAILED DESCRIPTION

(5) The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

(6) It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term and/or includes any and all combinations of one or more of the associated listed items.

(7) It will be understood that when an element such as a layer, region, or substrate is referred to as being on or extending onto another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being directly on or extending directly onto another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being over or extending over another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being directly over or extending directly over another element, there are no intervening elements present. It will also be understood that when an element is referred to as being connected or coupled to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being directly connected or directly coupled to another element, there are no intervening elements present.

(8) Relative terms such as below or above or upper or lower or horizontal or vertical may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.

(9) The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms a, an, and the are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms comprises, comprising, includes, and/or including when used herein specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

(10) Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

(11) The present disclosure relates to a signal generator with self-calibration. FIG. 1 shows an exemplary signal generator 10 according to one embodiment of the present disclosure and FIG. 2 provides a flow diagram that illustrates an exemplary operation process to generate a high purity-level signal by the signal generator 10 illustrated in FIG. 1. The RF signal generator 10 includes a main digital-to-analog converter (DAC) 12, a summing buffer structure 14, a two-path filter structure 16, a filter buffer 18, an analog-to-digital converter (ADC) 20, a control system 22, and a calibration DAC 24. In different applications, the main DAC 12, the ADC 20, and the calibration DAC 24 may have a same resolution or different resolutions.

(12) Herein, the main DAC 12 has an input terminal INa and an output terminal OUTa; the summing buffer structure 14 has a first input terminal INb1, a second input terminal INb2 and an output terminal OUTb; the two-path filter structure 16 has an input terminal INc and an output terminal OUTc; the filter buffer 18 has an input terminal INd and an output terminal OUTd; the ADC 20 has an input terminal INe and an output terminal OUTe; the control system 22 has an input terminal INf, an output terminal OUTf, and a control terminal CTR; and the calibration DAC 24 has an input terminal INg and an output terminal OUTg. The output terminal OUTa of the main DAC 12 is coupled to the first input terminal INb1 of the summing buffer structure 14 and the output terminal OUTg of the calibration DAC 24 is coupled to the second input terminal INb2 of the summing buffer structure 14. The input terminal INc of the two-path filter structure 16 is coupled to the output terminal OUTb of the summing buffer structure 14 and the output terminal OUTc of the two-path filter structure 16 is coupled to the input terminal INd of the filter buffer 18. The input terminal INe of the ADC 20 is coupled to the output terminal OUTd of the filter buffer 18 and the output terminal OUTe of the ADC 20 is coupled to the input terminal INf of the control system 22. The output terminal OUTf of the control system 22 is coupled to the input terminal INg of the calibration DAC 24.

(13) The main DAC 12 is configured to provide a main DAC output signal V.sub.outM(t), which normally has distortion. The main DAC output signal V.sub.outM(t) with distortion may be calibrated by a calibration DAC output signal V.sub.outC(t) generated from a feedback loop including the summing buffer structure 14, the two-path filter structure 16, the filter buffer 18, the ADC 20, the control system 22, and the calibration DAC 24. Herein, the calibration DAC output signal V.sub.outC(t) includes distortion information in the main DAC output signal V.sub.outM(t) and normally has an inverted phase (180 difference) to the main DAC output signal V.sub.outM(t). The summing buffer structure 14 sums the main DAC output signal V.sub.outM(t) and the calibration DAC output signal V.sub.outC(t) to provide a summing output signal V.sub.sum(t) at the output terminal OUTb of the summing buffer structure 14, such that the summing output signal V.sub.sum(t) corrects at least a portion of the distortion included in the main DAC output signal V.sub.outM(t). Therefore, the summing output signal V.sub.sum(t) has a higher purity level than the main DAC output signal V.sub.outM(t). After a number of calibration iterations (more details are described later), the summing output signal V.sub.sum(t) may correct substantially all distortion in the main DAC output signal V.sub.outM(t) and may be used as a high-purity output signal of the signal generator 10.

(14) At initial calibration iteration, the main DAC 12 receives an initial digital input signal C.sub.in(1)[n] at the input terminal INa of the main DAC 12 and generates an initial main DAC output signal V.sub.outM(1)(t) at the output terminal OUTa of the main DAC 12 (step 100). The initial digital input signal C.sub.in(1)[n] is an ideal digital sinusoidal/cosinusoidal signal with essentially no noise or distortion. The initial main DAC output signal V.sub.outM(1)(t), however, includes the distortion from the main DAC 12. At the initial calibration iteration, the calibration DAC 24 is turned off and an initial calibration DAC output signal V.sub.outc(1)(t) equals zero. See mathematic details in Section A below.

(15) The summing buffer structure 14 then provides an initial summing output signal V.sub.sum(1)(t) based on the initial main DAC output signal V.sub.outM(1)(t) (step 102). The initial summing output signal V.sub.sum(1)(t) does not correct the distortion in the initial main DAC output signal V.sub.outM(1)(t), because the calibration DAC 24 is turned off at the initial calibration iteration. See mathematic details in Section A below. Next, the two-path filter structure 16 sequentially generates an initial first filter output signal V.sub.Filter1(1)(t) and an initial second filter output signal V.sub.Filter2(1)(t) based on the initial summing output signal V.sub.sum(1)(t) (step 104). The two-path filter structure 16 has a first filter path 30 and a second filter path 32, which are selectively conducted by a control signal CS provided by the control system 22 at the control terminal CTR. In this embodiment, the first filter path 30 includes a signal attenuator, like a voltage divider (R1, R2, and R3) and the second filter path 32 includes a second order low-pass filter (R1, R2, C1, and C2). In different applications, the signal attenuator within the first filter path 30 may or may not be frequency dependent. The second filter path 32 may include a lower order or high order low-pass filter to adjust filter responses according to a filter input frequency (herein the filter input frequency is the frequency of the initial summing output signal V.sub.sum(1)(t)). Further, the first filter path 30 may include another low-pass filter instead of a signal attenuator. The low-pass filter in the first filter path 30 and the low-pass filter in the second filter path 32 may have a same or different order. Alternatively, the second filter path 32 may include another signal attenuator instead of a low-pass filter. When the first filter path 30 is conducted, the initial first filter output signal V.sub.Filter1(1)(t), which is an attenuated version of the initial summing output signal V.sub.sum(1)(t), is provided at the output terminal OUTc of the two-path filter structure 16. When the second filter path 32 is conducted, the initial second filter output signal V.sub.Filter2(1)(t), which is a low-pass filtered version of the initial summing output signal V.sub.sum(1)(t), is provided at the output terminal OUTc of the two-path filter structure 16. See mathematic details in Section C below.

(16) The ADC 20 sequentially receives the initial first filter output signal V.sub.Filter1(1)(t) and the initial second filter output signal V.sub.Filter2(1)(t) through the filter buffer 18, and sequentially provides an initial first ADC output signal V.sub.ADC1(1)[n] based on the initial first filter output signal V.sub.Filter1(1)(t) and an initial second ADC output signal V.sub.ADC2(1)[n] based on the initial second filter output signal V.sub.Filter2(1)(t) (step 106). Herein, each of the initial first ADC output signal V.sub.ADC1(1)[n] and the initial second ADC output signal V.sub.ADC2(1)[n] includes distortions generated from both the main DAC 12 and the ADC 20. The filter buffer 18 may be an op-amp buffer. See mathematic details in Section D below.

(17) After the initial first ADC output signal V.sub.ADC1(1)[n] and the initial second ADC output signal V.sub.ADC2(1)[n] are generated by the ADC 20 and transferred to the control system 22, an initial calibration input signal C.sub.C(1)(t) is generated and stored in the control system 22 (step 108). Herein, the control system 22 is configured to implement both control functions and calculation functions. For the control functions, the control system 22 is configured to generate the control signal CS that is used to selectively conduct the first filter path 30 and the second filter path 32 in the two-path filter structure 16. In addition, the control system 22 may be configured to turn off the calibration DAC 24 at the initial calibration iteration, such that the initial calibration DAC output signal V.sub.outc(1)(t) equals zero. For the calculation functions, the control system 22 is configured to separate the distortion from the main DAC 12 and the distortion from the ADC 20 based on the initial first ADC output signal V.sub.ADC1(1)[n] and the initial second ADC output signal V.sub.ADC2(1)[n], and configured to calculate the initial calibration input signal C.sub.C(1)(t) based on the distortion from the main DAC 12. Herein, the initial calibration input signal C.sub.C(1)(t) is also stored in the control system 22 and will be used to calculate a second calibration input signal C.sub.C(2)(t). See mathematic details in Section E below.

(18) The control system 22 may include at least one computing device providing firmware, hardware, and/or executable software (such as C++, Matlab, etc.), such as a microcontroller, application specific integrated circuit (ASIC), a personal computer, a computation engine, and the like. In one embodiment, the control system 22 is a microcontroller, which implements both the control functions and the calculation functions, and is embedded in a same printed circuit board (PCB) or overall system as the main DAC 12, the ADC 20, and the calibration DAC 24. In one embodiment, the control system 22 is a computer, which implements both the control functions and the calculation functions, and is off the board, where the main DAC 12, the ADC 20, and the calibration DAC 24 are embedded. Further, in one embodiment, a first portion of the control system 22, which is configured to implement the control functions, may be a microcontroller, an ASIC, or a central processing unit (CPU). The first portion of the control system 22 is embedded in the same PCB board as the main DAC 12, the ADC 20, and the calibration DAC 24. A second portion of the control system 22, which is configured to implement the calculation functions, may be a computer and is off the PCB board, where the main DAC 12, the ADC 20, and the calibration DAC 24 are embedded.

(19) At the end of the first iteration, the calibration DAC 24 receives the initial calibration input signal C.sub.C(1)(t) and generates the second calibration DAC output signal V.sub.outc(2)(t) based on the initial calibration input signal C.sub.C(1)(t) (step 110). The second calibration DAC output signal V.sub.outc(2)(t) will be used in the second calibration iteration. Further, the second calibration DAC output signal V.sub.outc(2)(t) may pass through a signal attenuator 34 before it is provided to the summing buffer structure 14. The signal attenuator 34 helps to reduce distortion introduced by the calibration DAC 24 itself. In this embodiment, the signal attenuator 34 may be a voltage divider. See mathematic details in Section F below.

(20) At i.sup.th (i2) calibration iteration, the main DAC 12 receives an i.sup.th digital input signal C.sub.in(i)[n] and generates an i.sup.th main DAC output signal V.sub.outM(i)(t) (step 112). The i.sup.th digital input signal C.sub.in(i)[n] is an ideal digital sinusoidal/cosinusoidal signal with essentially no noise and distortion. The i.sup.th main DAC output signal V.sub.outM(i)(t) includes the distortion from the main DAC 12.

(21) The summing buffer structure 14 then generates an i.sup.th summing output signal V.sub.sum(i)(t) by summing the main DAC output signal V.sub.outM(i)(t) and the calibration DAC output signal V.sub.outc(i)(t), which is provided by the calibration DAC 24 and generated in (i1).sup.th calibration iteration (step 114). Herein, the i.sup.th main DAC output signal V.sub.outM(i)(t) is provided to the first input terminal INb1 of the summing buffer structure 14, and the i.sup.th calibration DAC output signal V.sub.outc(i)(t) is provided to the second input terminal INb2 of the summing buffer structure 14. Since the i.sup.th calibration DAC output signal V.sub.outC(i)(t) includes the distortion information in the main DAC output signal V.sub.outM(t), the i.sup.th summing output signal V.sub.sum(i)(t) corrects at least a portion of the distortion in the i.sup.th main DAC output signal V.sub.outM(i)(t). If the i.sup.th summing output signal V.sub.sum(i)(t) achieves a desired purity-level (depending on different applications) and includes essentially no distortion from the main DAC 12 (at least 95% distortion in the i.sup.th main DAC output signal V.sub.outM(i)(t) has been eliminated), the i.sup.th summing output signal V.sub.sum(i)(t) may be used as a high-purity output signal of the signal generator 10. If the i.sup.th summing output signal V.sub.sum(i)(t) does not achieve the desired purity-level and still includes some distortion from the main DAC 12, the i.sup.th summing output signal V.sub.sum(i)(t) is provided to the two-path filter structure 16. The process will be iterated until the signal generator 10 is fully calibrated (at least 95% distortion in the main DAC output signal V.sub.outM(t) has been eliminated). See mathematic details in Section G below.

(22) It is clear to those skilled in the art that even if the main DAC 12, the ADC 20 and the calibration DAC 24 are not ideal and have unneglectable nonlinearities, the signal generator 10 will still generate a high-purity output signal. The purity of the output signal of the signal generator 10 no longer relies on the performances of the main DAC 12, the ADC 20 and the calibration DAC 24. The output signal of the signal generator 10 (a certain summing output signal V.sub.sum(t)) may have a much higher purity level than the original main DAC output signal V.sub.outM(t).

(23) Next, the two-path filter structure 16 sequentially generates an i.sup.th first filter output signal V.sub.Filter1(i)(t) and an i.sup.th second filter output signal V.sub.Filter2(i)(t) based on the i.sup.th summing output signal V.sub.sum(i)(t) (step 116). When the first filter path 30 is conducted, the i.sup.th first filter output signal V.sub.Filter1(i)(t), which is an attenuated version of the i.sup.th summing output signal V.sub.sum(i)(t), is provided at the output terminal OUTc of the two-path filter structure 16. When the second filter path 32 is conducted, the i.sup.th second filter output signal V.sub.Filter2(i)(t), which is a low-pass filtered version of the i.sup.th summing output signal V.sub.sum(i)(t), is provided at the output terminal OUTc of the two-path filter structure 16.

(24) The ADC 20 sequentially receives the i.sup.th first filter output signal V.sub.Filter1(i)(t) and the i.sup.th second filter output signal V.sub.Filter2(i)(t) through the filter buffer 18, and sequentially provides an i.sup.th first ADC output signal V.sub.ADC1(i)[n] and an i.sup.th second ADC output signal V.sub.ADC2(i)[n], respectively (step 118). At the i.sup.th calibration iteration, the i.sup.th main DAC output signal V.sub.outM(i)(t) is at least partially calibrated by the i.sup.th calibration DAC output signal V.sub.outc(i)(t), and consequently, the i.sup.th summing output signal V.sub.sum(i)(t) has less distortion from the main DAC 12 than the i.sup.th main DAC output signal V.sub.outM(i)(t). As such, each of the i.sup.th first ADC output signal V.sub.ADC1(i)[n] and the i.sup.th second ADC output signal V.sub.ADC2(i)[n] includes remaining distortion from the main DAC 12 in the i.sup.th summing output signal V.sub.sum(i)(t) and the distortion from the ADC 20.

(25) After the i.sup.th first ADC output signal V.sub.ADC1(i)[n] and the i.sup.th second ADC output signal V.sub.ADC2(i)[n] are generated by the ADC 20 and transferred to the control system 22, an i.sup.th calibration input signal C.sub.C(i)(t) is generated and stored in the control system 22 (step 120). Herein, the control system 22 is configured to implement both the control functions and the calculation functions. For the control functions, the control system 22 is configured to generate the control signal CS that is used to selectively conduct the first filter path 30 and the second filter path 32 in the two-path filter structure 16. In addition, the control system 22 is also configured to turn on the calibration DAC 24, such that the calibration DAC output signal V.sub.outC (t) is allowed to feed back to the summing buffer structure 14. For the calculation functions, the control system 22 is configured to separate the remaining distortion from the main DAC 12 and the distortion from the ADC 20 based on the i.sup.th first ADC output signal V.sub.ADC1(i)[n] and the i.sup.th second ADC output signal V.sub.ADC2(i)[n]. The i.sup.th calibration input signal C.sub.C(i)(t), which includes the distortion information in the i.sup.th main DAC output signal V.sub.outM(i)(t), is calculated by adding the (i1).sup.th calibration input signal C.sub.C(i1)(t), which is stored in the control system 22, and an i.sup.th calibration update signal that represents the remaining distortion from the main DAC 12 in the i.sup.th summing output signal V.sub.sum(i)(t). In addition, the i.sup.th calibration input signal C.sub.C(i)(t) is stored in the control system 22 and will be used to calculate an (i+1).sup.th calibration input signal C.sub.C(i+1)(t).

(26) At the end of the i.sup.th calibration iteration, the calibration DAC 24 generates the (i+1).sup.th calibration DAC output signal V.sub.outc(i+1)(t) based on the i.sup.th calibration input signal C.sub.C(i)(t) (step 122). The (i+1).sup.th calibration DAC output signal V.sub.outc(i+1)(t) will be used in the (i+1).sup.th calibration iteration. See mathematic details in Section G below.

(27) Section A

(28) At initial calibration iteration, the initial digital input signal C.sub.in(1)[n] is an ideal digital sinusoidal/cosinusoidal signal with essentially no noise and distortion, given by:

(29) $\begin{array}{cc}{C}_{\mathrm{IN}\left(1\right)}\left[n\right]=\mathrm{round}\left(\left(\frac{V_{\mathrm{RDAC}}}{2}+.Math.A.Math.\cos \left({}_o{\mathrm{nT}}_{\mathrm{SDAC}}+\right)\right)2^{N_{\mathrm{DAC}}}\right)& \left(1\right)\end{array}$
Where n=0, 1, 2 . . . M.sub.DAC1, M.sub.DAC is the data record length of the initial digital input signal C.sub.in(1)[n]. T.sub.SDAC stands for the sampling period of the main DAC 12.

(30) $.Math.A.Math.\frac{V_{\mathrm{RDAC}}}{2};$
the main DAC 12 output range is [0 V.sub.RDAC] and has resolution of N.sub.DAC bit; is the initial phase of initial digital input signal C.sub.in(1)[n], and

(31) $f_{\mathrm{sig}}=\frac{{}_o}{2}$
is a frequency of the initial digital input signal C.sub.in(1)[n]. If the main DAC 12 is ideal, the initial main DAC output signal V.sub.outM(1)(t) is given by:

(32) $\begin{array}{cc}{V}_{\mathrm{outM}\left(1\right)}\left(t\right)=\frac{V_{\mathrm{RDAC}}}{2}+.Math.A.Math.\cos \left({}_{o}t+\right)+Q_{\mathrm{DAC}}& \left(2\right)\end{array}$
where t[nT.sub.sDAC, (n+1)T.sub.sDAC], n=0, 1, 2 . . . M.sub.DAC 1, and Q.sub.DAC is a quantization error of the main DAC 12, given by:

(33) $\begin{array}{cc}{Q}_{\mathrm{DAC}}=\mathrm{round}\left(\left(\frac{V_{\mathrm{RDAC}}}{2}+.Math.A.Math.\cos \left({}_{o}t+\right)\right)2^{N_{\mathrm{DAC}}}\right)-\frac{V_{\mathrm{RDAC}}}{2}-.Math.A.Math.\cos \left({}_{o}t+\right))& \left(3\right)\end{array}$

(34) In reality, noise and nonlinearities will be added to the initial main DAC output signal V.sub.outM(1)(t), given by:

(35) $\begin{array}{cc}{V}_{\mathrm{outM}\left(1\right)}\left(t\right)=\frac{V_{\mathrm{RDAC}}}{2}+.Math.A.Math.\cos \left({}_{o}t+\right)+Q_{\mathrm{DAC}}+\underset{k=2}{\overset{+}{.Math.}}{A}_k\cos \left(k{}_{o}t+{}_k\right)+w\left(t\right)& \left(4\right)\end{array}$
where w(t) is the distortion of the main DAC 12, A.sub.k and .sub.k are amplitude and initial phase of the k.sup.th harmonic, respectively. As such, if the resolution of the main DAC 12 is N-bit, the purity level of the main DAC output signal V.sub.outM(t) may only achieve (N1)-bit or (N2)-bit.
Section B

(36) Since the initial calibration DAC output signal V.sub.outc(1)(t) equals zero, the initial summing output signal V.sub.sum(1)(t) is based on the initial main DAC output signal V.sub.outM(1)(t), given in exponential form:

(37) $\begin{array}{cc}{V}_{\mathrm{sum}\left(1\right)}\left(t\right)=D_0+\underset{k=1}{\overset{H}{.Math.}}.Math.D_k.Math.e^{j.Math.k{}_{o}t}{e}^{j.Math.{}_k}+W_{\mathrm{MDAC}}\left(t\right)& \left(5\right)\end{array}$
where

(38) $D_0=\frac{V_{\mathrm{RDAC}}}{2},.Math.D_1.Math.=.Math.D_{-1}.Math.=\frac{.Math.A.Math.}{2},.Math.D_k.Math.=.Math.D_{-k}.Math.=\frac{.Math.A_k.Math.}{2},$
.sub.1, .sub.k are fundamental's and k.sup.th harmonics phase, respectively. W.sub.MDAC(t) is the total noise including the quantization errors Q.sub.DAC and the distortion of the main DAC 12 and the summing buffer structure 14. k=1, 2, . . . H, and first H harmonics are considered for analysis, assuming that higher order harmonics have negligible power. The initial summing output signal V.sub.sum(1)(t) does not correct the distortion in the initial main DAC output signal V.sub.outM(1)(t), because the calibration DAC 24 is turned off at the initial calibration iteration.
Section C

(39) When the first filter path 30 is conducted, the first filter output signal V.sub.Filter1(1)(t), which is an attenuated version of the summing output signal V.sub.sum(1)(t), is given by:

(40) $\begin{array}{cc}{V}_{\mathrm{Filter}1\left(1\right)}\left(t\right)=D+\underset{k=1}{\overset{H}{.Math.}}.Math.D_k{H}_1\left(\mathrm{jk}{}_o\right).Math.e^{j.Math.k{}_{o}t}{e}^{j.Math.\left({}_k+{}_k\right)}+W_1\left(t\right)& \left(6\right)\end{array}$
When the second filter path 32 is conducted, the second filter output signal V.sub.Filter2(1)(t), which is a low-pass filtered version of the summing output signal V.sub.sum(1)(t), is given by:

(41) 0$\begin{array}{cc}{V}_{\mathrm{Filter}2\left(1\right)}\left(t\right)=D+\underset{k=1}{\overset{H}{.Math.}}.Math.D_k{H}_2\left(\mathrm{jk}{}_o\right).Math.e^{j.Math.k{}_{o}t}{e}^{j.Math.\left({}_k+{}_k\right)}+W_2\left(t\right)& \left(7\right)\end{array}$
where D is the offset voltage, which is essentially the same for both the initial first filter output signal V.sub.Filter1(1)(t) and the initial second filter output signal V.sub.Filter2(1)(t). W.sub.1(t) is a sum of w.sub.MDAC(t) and harmonic noise of the first filter path 30. W.sub.2(t) is a sum of W.sub.MDAC(t) and harmonic noise of the second filter path 32. Once the filter structure is known, the harmonic noise of the first filter path 30 and the harmonic noise of the second filter path 32 are known. The frequency response of the filters are H.sub.1(j) and H.sub.2(j), respectively:

(42) $\begin{array}{c}{H}_1\left(j\right)=.Math.H_1\left(j\right).Math.e^{\left(\right)}\left(8\right)\\ =\frac{R_3{R}_4}{R_1+R_2+R_3{R}_4}\left(9\right)\\ H_2\left(j\right)=.Math.H_2\left(j\right).Math.e^{\left(\right)}\left(10\right)\\ =\frac{1}{\left(\frac{R_1}{R_4}+\frac{R_2}{R_4}+1\right)+j.Math.\left[\begin{array}{c}{R}_1{C}_1\left(\frac{R_2}{R_4}+1\right)\\ +C_2\left(R_1+R_2\right)\end{array}\right]+{\left(j\right)}^2{R}_1{R}_2{C}_1{C}_2}\left(11\right)\end{array}$
Herein, the capacitors C1C2 and the resistors R1R3 in the two-path filter structure 16 and an output resistor R4 adjacent to the output terminal OUTc of the two-path filter structure 16 need to be chosen carefully, such that the initial first filter output signal V.sub.Filter1(1)(t) and the initial second filter output signal V.sub.Filter2(1)(t) have essentially the same amplitude (at most 5% amplitude difference). In addition, the capacitors C1C2 and the resistors R1R3 in the two-path filter structure 16 and the output resistor R4 are required to have superior linearity performance.
Section D

(43) With amplitude matched between the initial first filter output signal V.sub.Filter1(1)(t) and the initial second filter output signal V.sub.Filter2(1)(t), the initial first ADC output signal V.sub.ADC1(1)[n] and the initial second ADC output signal V.sub.ADC2(1)[n) are given by:

(44) $\begin{array}{cc}{V}_{\mathrm{ADC}1\left(1\right)}\left[n\right]=D+\underset{k=1}{\overset{H}{.Math.}}.Math.D_k{H}_1\left(\mathrm{jk}{}_o\right).Math.e^{j.Math.k{}_o{\mathrm{nT}}_{\mathrm{sADC}}}{e}^{j.Math.\left({}_k+{}_k\right)}+\underset{k=2}{\overset{H}{.Math.}}.Math.{\mathrm{HD}}_k.Math.e^{j.Math.k{}_o{\mathrm{nT}}_{\mathrm{sADC}}}{e}^{j.Math.k\left({}_1+{}_1\right)+{}_k}+W_{\mathrm{ADC}1}\left[n\right]& \left(12\right)\\ V_{\mathrm{ADC}2\left(1\right)}\left[n\right]=D+\underset{k=1}{\overset{H}{.Math.}}.Math.D_k{H}_2\left(\mathrm{jk}{}_o\right).Math.e^{j.Math.k{}_o{\mathrm{nT}}_{\mathrm{sADC}}}{e}^{j.Math.\left({}_k+{}_k\right)}+\underset{k=2}{\overset{H}{.Math.}}.Math.{\mathrm{HD}}_k.Math.e^{j.Math.k{}_o{\mathrm{nT}}_{\mathrm{sADC}}}{e}^{j.Math.k\left({}_1+{}_1\right)+{}_k}+W_{\mathrm{ADC}2}\left[n\right]& \left(13\right)\end{array}$
where W.sub.ADC1[n] is a total noise of W.sub.1(t) and noise of the ADC 20 based on the first filter output signal V.sub.Filter1(t), and W.sub.ADC2[n] is a total noise of W.sub.2(t) and noise of the ADC 20 based on the first filter output signal V.sub.Filter2(t). Since the initial first filter output signal V.sub.Filter1(1)(t) and the initial second filter output signal V.sub.Filter2(1)(t) are amplitude matched and the initial first filter output signal V.sub.Filter1(1)(t) and the initial second filter output signal V.sub.Filter2(1)(t) pass through the same filter buffer 18 and the ADC 20, the initial first ADC output signal V.sub.ADC1(1)[n] and the initial second ADC output signal V.sub.ADC2(1)[n] are also amplitude matched.
Section E

(45) In order to generate the initial calibration DAC input signal C.sub.C(1)(t) properly, which only includes distortion information about the main DAC 20, the initial first ADC output signal V.sub.ADC1(1)[n] and the initial second ADC output signal V.sub.ADC2(1)[n] need to be phase matched. The phase shift between the initial first ADC output signal V.sub.ADC1(1)[n] and the initial second ADC output signal V.sub.ADC2(1)[n] is due to different filter transfer functions of the first filter path 30 and the second filter path 32.

(46) To achieve the best phase matching possible, a first couple of consecutive points of the initial first ADC output signal V.sub.ADC1(1)[n] are chosen (herein five points are chosen), given by x.sub.1[1], x.sub.1[2], x.sub.1[3], x.sub.1[4], x.sub.1[5], and a same length of consecutive points of the initial second ADC output signal V.sub.ADC2(1)[n] are chosen, given by x.sub.2[i], x.sub.2[i+1], x.sub.2[i+3], x.sub.2[i+4]. These points (x.sub.1[1], x.sub.1[2], x.sub.1[3], x.sub.1[4], x.sub.1[5], x.sub.2[i], x.sub.2[i+1], x.sub.2[i+3], x.sub.2[i+4]) need to be chosen from the data points that are settled, which means the initial data points that are in transient process will be discarded. The best matching between x.sub.1[1], x.sub.1[2], x.sub.1[3], x.sub.1[4], x.sub.1[5] and x.sub.2[i], x.sub.2[i+1], x.sub.2[i+3], x.sub.2[i+4], may be found by minimizing the square root mean:

(47) $\begin{array}{cc}\sqrt{\begin{array}{c}{\left(x_2\left[i\right]-x_1\left[1\right]\right)}^2+{\left(x_2\left[i+1\right]-x_1\left[2\right]\right)}^2+{\left(x_2\left[i+2\right]-x_1\left[3\right]\right)}^2+\\ {\left(x_2\left[i+3\right]-x_1\left[4\right]\right)}^2+{\left(x_2\left[i+4\right]-x_1\left[5\right]\right)}^2\end{array}}{.Math.}_{\mathrm{Min}}& \left(14\right)\end{array}$

(48) After the index i is found, the initial filter output signal V.sub.Filter2(1)(t) will start from i to the end M, with a total data record length M1+1. Also, the initial first filter output signal V.sub.Filter1(1)(t) will be shortened to data record length M1+1, from 1 to Mi+1. An updated initial first ADC output signal V.sub.ADC1(1)[n] based on the shortened initial first filter output signal V.sub.Filter1(1)(t) and an updated initial second ADC output signal V.sub.ADC2(1) [n] based on the shortened initial second filter output signal V.sub.Filter2(1)(t) are given by:

(49) $\begin{array}{cc}{V}_{\mathrm{ADC}1\left(1\right)}\left[n\right]=D+.Math.D_1{H}_1\left(j{}_o\right).Math.e^{j{}_o{\mathrm{nT}}_{\mathrm{sADC}}}{e}^{j.Math.\left({}_1+{}_1\right)}+.Math.D_{-1}{H}_1\left(-j{}_o\right).Math.e^{-j{}_o{\mathrm{nT}}_{\mathrm{sADC}}}{e}^{j.Math.\left({}_1+{}_1\right)}+\underset{k=2}{\overset{H}{.Math.}}.Math.D_k{H}_1\left(jk{}_o\right).Math.e^{j.Math.k{}_o{\mathrm{nT}}_{\mathrm{sADC}}}{e}^{j.Math.\left({}_k+{}_k\right)}+\underset{k=2}{\overset{H}{.Math.}}.Math.{\mathrm{HD}}_k.Math.e^{j.Math.k{}_o{\mathrm{nT}}_{\mathrm{sADC}}}{e}^{j.Math.k\left({}_1+{}_1\right)+{}_k}+W_{\mathrm{ADC}1}\left[n\right]& \left(15\right)\\ V_{\mathrm{ADC}2\left(1\right)}\left[n\right]=D+.Math.D_1{H}_2\left(j{}_o\right).Math.e^{j{}_o{\mathrm{nT}}_{\mathrm{sADC}}}{e}^{j.Math.\left({}_1+{}_1\right)}+.Math.D_{-1}{H}_2\left(-j{}_o\right).Math.e^{-j{}_o{\mathrm{nT}}_{\mathrm{sADC}}}{e}^{j.Math.\left({}_1+{}_1\right)}+\underset{k=2}{\overset{H}{.Math.}}.Math.D_k{H}_2\left(jk{}_o\right).Math.e^{j.Math.k{}_o{\mathrm{nT}}_{\mathrm{sADC}}}{e}^{j.Math.\left({}_k+{}_k+k.Math.\left({}_1-{}_1\right)\right)}+\underset{k=2}{\overset{H}{.Math.}}.Math.{\mathrm{HD}}_k.Math.e^{j.Math.k{}_o{\mathrm{nT}}_{\mathrm{sADC}}}{e}^{j.Math.k\left({}_1+{}_1\right)+{}_k}+W_{\mathrm{ADC}2}\left[n\right]& \left(16\right)\end{array}$

(50) Herein, since the shortened initial first filter output signal V.sub.Filter1(1)(t) and the shortened initial second filter output signal V.sub.Filter2(1) (t) are matched in both amplitude and phase and pass through the same filter buffer 18 and the ADC 20, a nonlinearity error, which is caused by the ADC 20, in the initial first ADC output signal V.sub.ADC1(1)[n] and a nonlinearity error, which is caused by the ADC 20, in the initial second ADC output signal V.sub.ADC2(1)[n] are essentially the same.

(51) After identification, an estimated fundamental from the ADC 20 is given by:

(52) $\begin{array}{cc}{\hat{V}}_{\mathrm{Fund}}\left[n\right]=\hat{A}\sin \left(\frac{2\left(J_{\mathrm{int}}+\hat{}\right)}{M}n+\hat{}\right)+{\stackrel{}{V}}_{\mathrm{os}}& \left(17\right)\end{array}$
where J.sub.int stands for the integer part of sampled periods, {circumflex over ()} is the estimated fractional part of sampled periods, is the estimated fundamental amplitude, {circumflex over ()} is the estimated initial phase and V.sub.os is the estimated DC offset.

(53) After the fundamental in the initial first ADC output signal V.sub.ADC1(1)[n] and the fundamental in the initial second ADC output signal V.sub.ADC2(1)[n] are estimated, they are subtracted from the initial first ADC output signal V.sub.ADC1(1)[n] and the initial second ADC output signal V.sub.ADC2(1)[n], respectively.
r.sub.1[n]=V.sub.ADC1(1)[n]{circumflex over (V)}.sub.Fund[n](18)
r.sub.2[n]=V.sub.ADC2(1)[n]{circumflex over (V)}.sub.Fund[n](19)
Since the initial first ADC output signal V.sub.ADC1(1)[n] and the initial second ADC output signal V.sub.ADC2(1)[n] have the same ADC nonlinearities, when subtracting two residues, the ADC nonlinearities are subtracted, leaving only DAC's nonlinearities.
R.sub.3[n]=r.sub.1[n]r.sub.2[n](20)
Now in R.sub.3[n], it can be viewed as summations of a fundamental and harmonics in the form of sines and cosines. By using least square again, without the error introduced by the leakage of the fundamental, the accurate estimation of each harmonic component can be obtained similarly. The estimated harmonics are given by:

(54) $\begin{array}{cc}{\mathrm{xh}}_2\left[n\right]=\underset{k=2}{\overset{H}{.Math.}}\left[\begin{array}{c}{\hat{a}}_k\cos \left(2k\frac{J_{\mathrm{int}}+\hat{}}{M}n\right)\\ +\widehat{b_k}\sin \left(2k\frac{J_{\mathrm{int}}+\hat{}}{M}n\right)\end{array}\right]& \left(21\right)\end{array}$
The estimated k.sup.th harmonic component is given by:

(55) $.Math.\sqrt{{\hat{a}}_k^2+{\hat{b}}_k^2}.Math.e^{j{}_k},$
where

(56) ${}_k={\tan }^{-1}\left(\frac{{\hat{b}}_k}{{\hat{a}}_k}\right).$

(57) By subtracting (15) and (16) from (6) and (7), respectively, the ADC 20 introduced errors are subtracted, so do the fundamental and DC components, leaving only subtractions of nonlinearities from the two outputs of the ADC 20. For k=2, 3 . . . H, each k.sup.th nonlinearity subtraction is obtained by

(58) $.Math.\sqrt{{\hat{a}}_k^2+{\hat{b}}_k^2}.Math.e^{j{}_k}$
derived above. Ignoring the noise effect, and by re-arranging terms, the nonlinearity of the main DAC 12 can therefore be estimated:

(59) 0$\begin{array}{cc}2.Math.{\hat{D}}_k.Math.e^{j.Math.{\hat{}}_k}=\frac{.Math.\sqrt{{\hat{a}}_k^2+{\hat{b}}_k^2}.Math.e^{j{}_k}}{.Math.{\hat{H}}_1\left(jk{}_o\right).Math.e^{j.Math.\left({\hat{}}_k-k{\hat{}}_1\right)}-.Math.{\hat{H}}_2\left(jk{}_o\right).Math.e^{j.Math.\left({\hat{}}_k-k{\hat{}}_1\right)}}& \left(22\right)\end{array}$
where k.sup.th DAC's harmonic amplitude and phase is 2|{circumflex over (D)}.sub.k|, {circumflex over ()}.sub.k.

(60) The initial calibration input signal C.sub.C(1)(t) will be the estimated nonlinearity of the main DAC 12, multiplied by the estimated attenuation factor 6

(61) $\begin{array}{cc}{C}_{\mathrm{CC}\left(1\right)}\left[n\right]=\mathrm{round}\left(\left(\begin{array}{c}-\hat{G}\underset{k=2}{\overset{H}{.Math.}}2.Math.{\hat{D}}_k.Math.\cos \left(k{}_o{\mathrm{nT}}_{\mathrm{sDAC}}+{\hat{}}_k\right)\\ +\frac{V_{\mathrm{RDAC}}}{2}\end{array}\right)2^{N_{\mathrm{DAC}}}\right)& \left(23\right)\end{array}$
Similar to the initial main DAC output signal V.sub.outM(1)(t), the second calibration DAC output signal V.sub.outc(2)(t), which will be used in the second calibration iteration, is given by:

(62) $\begin{array}{cc}{V}_{\mathrm{outC}\left(2\right)}\left(t\right)\frac{V_{\mathrm{RDAC}}}{2}+\left(-\hat{G}\right)\underset{k=2}{\overset{H}{.Math.}}2.Math.{\hat{D}}_k.Math.\cos \left(k{}_{o}t+{\hat{}}_k\right)+\underset{k=2}{\overset{H}{.Math.}}{A}_{\mathrm{CDACk}}\cos \left(k{}_{o}t+{}_{\mathrm{CDACk}}\right)+W_{\mathrm{CDAC}}\left(t\right)& \left(24\right)\end{array}$
where w.sub.CDAC(t) contains a noise and quantization error of the calibration DAC 24.

(63) After the signal attenuator 34, the attenuated calibration DAC output is given by:

(64) $\begin{array}{cc}{V}_{\mathrm{outC}\_\mathrm{att}\left(2\right)}\left(t\right)=D_C-\frac{\hat{G}}{G}\underset{k=2}{\overset{H}{.Math.}}.Math.{\hat{D}}_k.Math.e^{j.Math.k{}_{o}t}{e}^{j.Math.{\hat{}}_k}+E_{\mathrm{CDAC}}\left(t\right)/G& \left(25\right)\\ E_{\mathrm{CDAC}}\left(t\right)=\underset{k=2}{\overset{H}{.Math.}}{A}_{\mathrm{CDACk}}\cos \left(k{}_{o}t+{}_{\mathrm{CDACk}}\right)+W_{\mathrm{CDAC}}\left(t\right)& \left(26\right)\end{array}$
As can be seen from eq. (25), the error introduced by the calibration DAC 24 is attenuated by the factor of G, the error introduced by the calibration DAC 24 itself will be small enough, and may be neglected. One thing to be mentioned is that the attenuation needs to be controlled to some level so that the calibration input signal C.sub.C(1)(t) range will near the full range of the calibration DAC input. However, if the attenuation factor G is too large, the calibration DAC input will be clipped, which will lead to the wrong output and not only will the nonlinearities of the main DAC not be cancelled, but will also introduce extra distortions to the combined signal.
Section G

(65) The second summing output signal V.sub.sum(2)(t) is given by:

(66) $\begin{array}{cc}{V}_{\mathrm{sum}\left(2\right)}\left(t\right)=D_0-D_C+.Math.D_1.Math.\left(e^{j.Math.k{}_{o}t}+e^{-j.Math.k{}_{o}t}\right)e^{j.Math.{}_k}+\underset{k=2}{\overset{H}{.Math.}}\left(.Math.D_k.Math.e^{j.Math.k{}_{o}t}{e}^{j.Math.{}_k}-\left(1+{\mathrm{GE}}_F\right)\left(-\frac{\hat{G}}{G}\right).Math.{\hat{D}}_k.Math.e^{j.Math.k{}_{o}t}{e}^{j.Math.{\hat{}}_k}\right)+W_{\mathrm{MDAC}}\left(t\right)-E_{\mathrm{CDAC}}\left(t\right)/G& \left(27\right)\end{array}$
Once the digital input signal C.sub.in[n] is fed into the main DAC 12 and the signal generator 10 is turned on accordingly, the whole iteration of generating the calibration input signal C.sub.C[n] may be automatically performed to produce ultra-pure sine/cos wave. Therefore, the signal generator 10 is capable of self-calibration. If the 2.sup.nd summing output signal V.sub.sum(2)(t) achieves a desired purity-level (depending on different applications) and includes essentially no distortion from the main DAC 12, the 2.sup.nd summing output signal V.sub.sum(2)(t) may be used as a high-purity output signal of the signal generator 10. If the 2.sup.nd summing output signal V.sub.sum(2)(t) does not achieve the desired purity-level and still includes some distortion from the main DAC 12, more iterations may be used to improve the signal purity.
Section H

(67) In this section, mathematical analysis will be shown to demonstrate that the iteration process is guaranteed to converge and the nonlinearity of the main DAC 12 will eventually be calibrated, which is only limited by noise.

(68) Let HD.sub.k,i stand for k.sup.th input harmonic distortion in i.sup.th iteration (i=1, 2, . . . ). At 1.sup.st iteration, the true value of k.sup.th input harmonic distortion is: HD.sub.k,1=|D.sub.k|e.sup.j.Math.k.sup.o.sup.te.sup.j.Math..sup.k. And the estimated k.sup.th input harmonic distortion is given by:

(69) $\begin{array}{cc}{\mathrm{HD}}_{k,1}=.Math.{\hat{D}}_{k,1}.Math.e^{j.Math.{\hat{}}_{k,1}}& \left(28\right)\\ =\frac{.Math.\sqrt{{\hat{a}}_{k,1}^2+{\hat{b}}_{k,1}^2}.Math.e^{j{\hat{}}_{k,1}}}{2\left(.Math.{\hat{H}}_1\left(\mathrm{jk}{}_o\right).Math.e^{j.Math.\left({\hat{}}_k-k{\hat{}}_1\right)}-.Math.{\hat{H}}_2\left(\mathrm{jk}{}_o\right).Math.e^{j.Math.\left({\hat{}}_k-k{\hat{}}_1\right)}\right)}& \left(29\right)\end{array}$
At 2.sup.nd iteration, the true value of k.sup.th input harmonic distortion is given by:

(70) $\begin{array}{cc}{\mathrm{HD}}_{k,2}={\mathrm{HD}}_{k,1}-\frac{\hat{G}}{G}{\mathrm{HD}}_{k,1}+\frac{.Math.D_{\mathrm{CDACk}}.Math.e^{j.Math.k{}_{o}t}{e}^{j.Math.{}_{\mathrm{CDACk}}}}{G}& \left(30\right)\end{array}$
Therefore, at (i+1).sup.th iteration, the k.sup.th harmonic distortion is:

(71) $\begin{array}{cc}{\mathrm{HD}}_{k,i+1}={\mathrm{HD}}_{k,i}-\frac{\hat{G}}{G}{\mathrm{HD}}_{k,i}+\frac{.Math.D_{\mathrm{CDACk}}.Math.e^{j.Math.k{}_{o}t}{e}^{j.Math.{}_{\mathrm{CDACk}}}}{G}& \left(31\right)\end{array}$
Assume
HD.sub.k,i=HD.sub.k,i+HD.sub.k,i(32)
where HD.sub.k,i contain the i.sup.th iteration's estimation. Then eq. (31) can be rewritten as:

(72) $\begin{array}{cc}{\mathrm{HD}}_{k,i+1}=\left(1-\frac{\hat{G}}{G}\right){\mathrm{HD}}_{k,i}+\frac{\hat{G}.Math.{\mathrm{HD}}_{k,i}+.Math.D_{\mathrm{CDACk}}.Math.e^{j.Math.k{}_{o}t}{e}^{j.Math.{}_{\mathrm{CDACk}}}}{G}& \left(33\right)\end{array}$
HD.sub.k,i can also be given by:

(73) $\begin{array}{cc}{\mathrm{HD}}_{k,i}=\frac{.Math.\sqrt{a_{k,i}^2+b_{k,i}^2}.Math.e^{j{}_{k,i}}}{2\left(.Math.H_1\left(\mathrm{jk}{}_o\right).Math.e^{j.Math.\left({}_k-k{}_1\right)}-.Math.H_2\left(\mathrm{jk}{}_o\right).Math.e^{j.Math.\left({}_k-k{}_1\right)}\right)}+W_{\mathrm{HD}\_\mathrm{ADC}+N}& \left(34\right)\end{array}$
where W.sub.HD.sub._.sub.ADC+N contains the ADC harmonics and noise subtraction between two ADC outputs, and error from true and estimated filters values.

(74) On the numerator,

(75) 0$.Math.\sqrt{a_{k,i}^2+b_{k,i}^2}.Math.e^{j{}_{k,i}}$
is linearly proportional to HD.sub.k,i, let:

(76) $.Math.\sqrt{a_{k,i}^2+b_{k,i}^2}.Math.e^{j{}_{k,i}}=.Math.{\mathrm{HD}}_{k,i},$
and

(77) $\frac{1}{}=2\left(.Math.H_1\left(\mathrm{jk}{}_o\right).Math.e^{j.Math.\left({}_k-k{}_1\right)}-.Math.H_2\left(\mathrm{jk}{}_o\right).Math.e^{j.Math.\left({}_k-k{}_1\right)}\right),$
which is independent of iterations. Similarly, let ={circumflex over ()}+, ={circumflex over ()}+. contains the estimation error from a slight inequality of two outputs ADC nonlinearity; contains the estimation error from FIRE and Least Square computational errors. Then eq. (34) can be written as:

(78) $\begin{array}{cc}{\mathrm{HD}}_{k,i}=.Math..Math.{\mathrm{HD}}_{k,i}+W_{\mathrm{HD}\_\mathrm{ADC}+N}& \left(35\right)\\ {\mathrm{HD}}_{k,i}+\left(+\right).Math.{\mathrm{HD}}_{k,i}+W_{\mathrm{HD}\_\mathrm{ADC}+N}& \left(36\right)\end{array}$
Plugging eq. (36) into eq. (33),

(79) $\begin{array}{cc}.Math.{\mathrm{HD}}_{k,i+1}.Math.=.Math.\frac{G+\hat{G}.Math.\left(+\right)}{G}.Math..Math..Math.{\mathrm{HD}}_{k,i}.Math.+.Math.\frac{\hat{G}.Math.W_{\mathrm{HD}\_\mathrm{ADC}+N}+.Math.D_{\mathrm{CDACk}}.Math.e^{j.Math.k{}_{o}t}{e}^{j.Math.{}_{\mathrm{CDACk}}}}{G}.Math.& \left(37\right)\end{array}$
where

(80) $0<.Math.\frac{G+\hat{G}.Math.\left(+\right)}{G}.Math.1,$
and

(81) $\mathrm{.Math.}=.Math.\frac{\hat{G}.Math.W_{\mathrm{HD}\_\mathrm{ADC}+N}+.Math.D_{\mathrm{CDACk}}.Math.e^{j.Math.k{}_{o}t}{e}^{j.Math.{}_{\mathrm{CDACk}}}}{G}.Math.$
is the small error term due to various error sources mentioned earlier. Therefore,

(82) $\begin{array}{cc}\underset{i.fwdarw.}{\lim }.Math.{\mathrm{HD}}_{k,i}.Math.=\mathrm{.Math.}& \left(38\right)\end{array}$
It demonstrates that as the iteration process continues, eventually the source nonlinearity will be calibrated and converge.

(83) Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.