RADAR SYSTEM

Abstract

Radar System The disclosure relates to a radar system having multiple radar transceiver modules, in which each module has a clock signal that is synchronised with a clock signal generated by a leader transceiver module. Example embodiments include a radar system (400) comprising a plurality of radar transceiver modules (401, 402) mounted to a common PCB (404), the plurality of radar transceiver modules comprising a leader module (401) and one or more follower modules (402), the leader module (401) comprising a first oscillator (403) configured to provide a first clock signal at a first frequency to each follower module (402), each of the leader and follower modules comprising a phase locked loop, PLL, clock signal generator (300), the PLL clock signal generator (300) comprising a divide by n clock divider (304) arranged to output 2n phase shifted clock signals (314) at a third frequency and a multiplexer (306) connected to receive the 2n phase shifted clock signals from the divide by n clock divider (304) and output a third clock signal (308) selected by an input phase select signal (307).

Claims

1. A radar system comprising a plurality of radar transceiver modules mounted to a common PCB, the plurality of radar transceiver modules comprising a leader module and one or more follower modules, the leader module comprising a first oscillator configured to provide a first clock signal at a first frequency to each follower module, each of the leader and follower modules comprising a phase locked loop, PLL, clock signal generator comprising: a phase comparator connected to receive the first clock signal and a feedback signal; a loop filter connected to receive an output signal from the phase comparator; a second oscillator connected to receive an output signal from the loop filter and generate a second clock signal at a second frequency; a divide by n clock divider connected to receive the second clock signal from the second oscillator and to output 2n phase shifted clock signals at a third frequency; a feedback device connected to receive one of the phase shifted clock signals from the divide by n clock divider and provide the feedback signal to the phase comparator; and a multiplexer connected to receive the 2n phase shifted clock signals from the divide by n clock divider and output a third clock signal selected by an input phase select signal.

2. The radar system of claim 1, wherein the output of the multiplexer in each of the plurality of radar transceiver modules is connected to an analog to digital converter, ADC, arranged to receive signals from a radar signal receiver.

3. The radar system of claim 1, wherein n is an odd integer of 3 or more.

4. The radar system of claim 3, wherein n=3, 5 or 7.

5. The radar system of claim 1, wherein the divide-by-n clock divider in each of the plurality of radar transceiver modules comprises a divider core configured to divide the second clock signal into an intermediate clock signal, a chain of flip-flops configured to receive alternating edges of the intermediate clock signal and a plurality of logic gates arranged to combine outputs from consecutive pairs of the chain of flip-flops to provide the output phase shifted clock signals at the third frequency.

6. The radar system of claim 5, wherein the divide by n clock divider five flip-flops FFs, arranged to receive the second clock signal from the second oscillator, three OR gates and one AND gate arranged to receive outputs from the FFs.

7. The radar system of claim 6 wherein the divide by n clock divider comprises three inverters connected to a respective OR gate output, 3 of the phase shifted clock signals being output by the OR gates and another 3 of the phase shifted clock signals being output by the inverters.

8. The radar system of claim 5, wherein the divide by n clock divider comprises eight FFs arranged to receive the second clock signal from the second oscillator and six OR gates arranged to receive outputs from the FFs and provide the 2n phase shifted clock signals.

9. The radar system of claim 5, wherein the divide by n clock divider comprises five FFs arranged to receive the second clock signal from the second oscillator, three OR gates arranged to receive outputs from the FFs and provide n of the 2n phase shifted clock signals and three AND gates arranged to receive outputs from the FFs and provide another n of the 2n phase shifted clock signals.

10. The radar system of claim 1, wherein the first frequency is in a range of between around 1 and 100 MHz.

11. The radar system of claim 1, wherein the third frequency is in a range between around 1 and 10 GHz.

12. The radar system of claim 1, comprising a non-volatile memory configured to store a value of the input phase select signal, the radar system being configured to retrieve a stored value of the input phase select signal for each module during operation of the radar system.

13. The radar system of any claim 1, wherein the feedback device in each of the plurality of radar transceiver modules is a divide-by-m clock divider and/or a time-to-digital converter.

14. A method of calibrating a radar system according to claim 1, the method comprising: operating each of the plurality of radar transceiver modules to detect a target; determine a phase select signal for the divide by n clock divider of the PLL clock signal generator in each module to minimize a difference in phase between the third clock signal in each follower module and in the leader module; and storing the determined phase select signal for each of the plurality of radar transceiver modules in a non-volatile memory.

15. A method of operating a radar system according to of claim 1, the method comprising: retrieving a phase select signal for each of the plurality of radar transceiver modules from a non-volatile memory; and operating each of the plurality of radar transceiver modules while providing the retrieved phase select signal to the divide by n clock divider of the PLL clock signal generator in each module.

16. The method of claim 15, wherein the divide-by-n clock divider in each of the plurality of radar transceiver modules comprises a divider core configured to divide the second clock signal into an intermediate clock signal, a chain of flip-flops configured to receive alternating edges of the intermediate clock signal and a plurality of logic gates arranged to combine outputs from consecutive pairs of the chain of flip-flops to provide the output phase shifted clock signals at the third frequency.

17. The method of claim 15, wherein the output of the multiplexer in each of the plurality of radar transceiver modules is connected to an analog to digital converter, ADC, arranged to receive signals from a radar signal receiver.

18. The method of claim 15, wherein the radar system comprises a non-volatile memory configured to store a value of the input phase select signal, the radar system being configured to retrieve a stored value of the input phase select signal for each module during operation of the radar system.

19. The method of claim 15, wherein the feedback device in each of the plurality of radar transceiver modules is a divide-by-m clock divider and/or a time-to-digital converter.

20. The method of claim 15, wherein the first frequency is in a range of between around 1 and 100 MHz.

Description

BRIEF DESCRIPTION OF DRAWINGS

[0036] Embodiments will be described, by way of example only, with reference to the drawings, in which:

[0037] FIG. 1 is a schematic diagram of an example radar system comprising multiple radar transceiver modules;

[0038] FIG. 2 is a schematic diagram illustrating a leader clock signal and multiple phase shifted clock signals;

[0039] FIG. 3 is a schematic diagram of an example PLL clock signal generator;

[0040] FIG. 4 is an example radar system having a leader transceiver module and one follower transceiver module;

[0041] FIGS. 5, 6 and 7 are schematic diagrams of example logic circuits for providing a divide-by-3 clock signal divider with multiple phase outputs;

[0042] FIG. 8 is a plot of a series of clock signals in an example divide-by-3 clock signal divider;

[0043] FIG. 9 is a schematic flow diagram of an example method of calibrating a radar system of the type disclosed herein; and

[0044] FIG. 10 is a schematic flow diagram of an example method of operating a radar system of the type disclosed herein.

[0045] It should be noted that the Figures are diagrammatic and not drawn to scale. Relative dimensions and proportions of parts of these Figures have been shown exaggerated or reduced in size, for the sake of clarity and convenience in the drawings. The same reference signs are generally used to refer to corresponding or similar feature in modified and different embodiments.

DETAILED DESCRIPTION OF EMBODIMENTS

[0046] If the reference phase between the radar transceiver modules 101a-d is fixed and stable on the PCB 102 and does not vary after mounting the modules on the PCB, for example due to aging, the sampling clock in each follower module can be phase aligned with respect to the sampling clock of the leader module. The aim of the present disclosure is to generate ADC sampling clocks for a radar system comprising one or more follower transceiver modules that can be phase-aligned to a reference clock signal from a leader module, preferably with a resolution of less than 100 ps and with a duty cycle of 50% derived from a divide-by-3 clock divider.

[0047] An example implementation of a PLL 300 for generating a clock signal with a selectable phase is illustrated in FIG. 3. The PLL 300 comprises a divide-by-3 clock divider 304 as part of the feedback loop of the PLL 300, which ensures a constant phase relation between the reference clock of the PLL and not only the output clock of the divider 304 but with all signal phases output by the divider 304. A differential clock divider system with a clk_p and a clk_n input signal may be obtained from the oscillator 303 which have an accurate 180° phase relation, which is typically available from differential circuits and signal processing. This can be achieved by design measures. A multiplexer 306 with a phase select control signal 307 determines the phase of the output clock signal 308.

[0048] The PLL clock signal generator 300 comprises a phase comparator 301, a loop filter 302, an oscillator 303, which may be a voltage controlled oscillator (VCO) or digitally controlled oscillator (DCO), a divide-by-n clock divider 304, a feedback device 305 and a multiplexer 306. The feedback device 305 may for example be a divide-by-m clock divider, a time-to-digital converter or a combination of both. The phase comparator 301 receives a first clock signal 309 from an oscillator at the leader module, which in this example is a reference clock signal at a reference frequency fret, and a feedback signal 310 at the same frequency from the feedback device 305. An output signal 311 of the phase comparator 301 is provided to the loop filter 302, which provides a control signal 312 to the oscillator 303. The oscillator 303 generates a second clock signal 313 that is provided to the divide-by-n clock divider 304. In a typical example n may be 3, such that the divider 304 outputs a series of clock signals 314 at different phases, each having a frequency of ⅓ that of the second clock signal. One of the clock signals 315 is provided to the feedback device, which divides the clock signal 315 to result in a feedback signal 310 at the same frequency fret as the input first clock signal 309.

[0049] The multiple clock signals 314 are input to a multiplexer 306, which selects one of the clock signals 314 according to a phase select signal 307, providing a third clock signal 308 that is provided to an ADC of the transceiver module.

[0050] The PLL clock signal generator 300 may be operated by determining the correct phase for each module during product testing of each transceiver module once mounted on the common PCB and then storing the correct setting in a memory. The required phase will be dominantly determined by the layout of the modules on the PCB and can therefore be assumed to be constant.

[0051] FIG. 4 is a schematic diagram of an example radar system 400 comprising a plurality of radar transceiver modules 401, 402 mounted on a common PCB 404, a first module 401 being a leader module and a second module 402 being a follower module. The leader module 401 comprises a first oscillator 403, which provides a first clock signal at a first frequency. The first clock signal is provided via connection paths 404, 405 between the modules 401, 402 to each of the modules 401, 402. The connection paths 404, 405 are configured to provide the first clock signal as an input to a PLL clock signal generator 4061, 4062 in each module. The clock signal generator 4061, 4062 in each module 401, 402 is of the form described above in relation to FIG. 3, with the phase select signal 307 being indicated by the signals Sel_Phase_L (for the leader module 401) and Sel_Phase_F (for the follower module 402). The clock signal generator 4061, 4062 in each module provides an output clock signal at the appropriate phase to an analog to digital converter 4071, 4072, which receives signals from a radar receiver 4081, 4082 in each module 401, 402. Matching the phases of the clock signals provided to each ADC allows the radar system 400 to combine the signals from each module 401, 402 to obtain a finer resolution. Other components of the radar transceiver modules 401, 402 such as the local oscillator (LO), transmitter (TX), chirp signal generator (Chirp PLL) and signal processor (CSI2) that are required to ensure a high resolution radar system will be known to the skilled person and are therefore not described in detail here.

[0052] In a test and calibration procedure during manufacture and assembly, once the modules 401, 402 are mounted on the PCB 404 the modules 401, 402 are operated to detect a known target 409. Signals received from the target by the receivers 4081, 4082 in each module can be used to select the appropriate phase signal provided to the ADC in each follower module 402. Although only one follower module 402 is shown in FIG. 4, it will be appreciated that more than one follower module may be provided, with each additional follower module being essentially identical to the follower module 402 shown and receiving the same first clock signal from the leader module 401. Once the appropriate phase is selected for each module, the phase select signal 307 is saved in non-volatile memory on the radar system 400 to be used when the radar system 400 is subsequently operated. Each module 401, 402 may for example comprise a non-volatile memory 409.sub.1, 409.sub.2 for storing a phase select value to be used when operating the radar system 400. In alternative arrangements a single non-volatile memory may be provided common to each of the radar modules 401, 402 and may be provided on one of the modules or separately from the modules.

[0053] FIGS. 5, 6 and 7 illustrate three different example divider structures for a divide-by-3 clock divider providing a 50% duty cycle output clock signal, each of which receives the second clock signal 313 from the VCO/DCO 303 and outputs the 2n phase shifted clock signals 314. Each of these examples have in common a differential clock input provided by the VCO/DCO 303 and a divide-by-3 arrangement using multiple flip-flops (FFs) providing output signals with a duty cycle of 33% (i.e. ⅓) or 66% (⅔), which is then used to generate multiple output clock signals with a duty cycle of 50%. A differential input clock signal allows the FFs to operate at rising or falling clock edges by just swapping the clock inputs. To achieve a 50% output duty cycle at the divider requires: i) a clock signal from the VCO or DCO with a 50% duty cycle; ii) a divider core providing the clock division (i.e. the first two FFs in the examples shown); iii) a chain of FFs which operate at alternating edges; and iv) logic gates (AND/NAND, OR/NOR) which combine the output signals of two consecutive FFs in the chain of alternatingly clocked FFs. In a general aspect therefore, the second clock signal has a 50% duty cycle and the divide-by-n clock divider comprises a divider core configured to divide the second clock signal into an intermediate clock signal, a chain of flip-flops configured to receive alternating edges of the intermediate clock signal and a plurality of logic gates arranged to combine outputs from consecutive pairs of the chain of flip-flops to provide the output phase shifted clock signals at the third frequency. The intermediate clock signal will have either a ⅓ or ⅔ duty cycle if n is an odd integer, while the output phase shifted clock signals will have a 50% duty cycle. The divider core may be a pair of flip-flops.

[0054] The divider output is delayed by half an input clock cycle a number of times. The output with a 50% duty cycle is generated by combining two delayed signals such that the result provides a 50% duty cycle at the divided frequency. FIG. 8 illustrates a series of clock signals with the input clock signal 801, three intermediate clock signals 802, 803, 804 with a 33% duty cycle and differing phases, various delayed versions 805 of the intermediate clock signals and the 50% duty cycle output signals 806, 807, 808, 809, 810, 811 at successive phases ranging from 0° to 300° at 60° intervals, resulting from combinations of the intermediate and delayed signals 802-805.

[0055] In the example divider 500 in FIG. 5, a combination of five flip flops (FFs) 501.sub.1-5, three OR gates 502.sub.1-3, an AND gate 503 and three inverters 504.sub.1-3 is used to generate six output clock signals 314 having a uniformly distributed range of phases in 60° increments. The divider core of the divider 500 consists of the first two FFs 501.sub.1,2 and the chain of FFs consists of FFs 501.sub.3-5. Opposing phases (0° and 180°, 60° and 240°, 120° and) 300° are created by inversion using inverters 504.sub.1-3. If the divider structure 500 is completely differential, the inversion can be achieved instead simply by wiring and without any additional gates. This way also accurate phase alignment is achieved. The load for all of the FFs 501.sub.1-5 may be identical, which may for example be achieved by loading the final FF 501.sub.5 with a further FF or an equivalent dummy load.

[0056] FIG. 6 shows an alternative clock divider structure 600 with 8 FFs 601.sub.1-8, one AND gate 603 and 6 OR gates 602.sub.1-6. The divider core of the divider 600 consists of the first two FFs 601.sub.1,2 and the chain of FFs consists of FFs 601.sub.3-8. This structure can be implemented in either single ended or differential versions.

[0057] In both cases, the expected duty cycle is 50%. As with the divider 500 in FIG. 5, 60° phase alignment can be achieved from the output clock signals 314. However, the number of components in terms of gates and FFs is larger than in the example in FIG. 5. The final FF 601.sub.8 may be loaded by a dummy device to balance the load of the FFs and therefore the propagation delay of the clock phases.

[0058] FIG. 7 illustrates a further alternative clock divider structure 700 that needs 5 FFs 701.sub.1-5, 4 AND-gates 702.sub.1-3 and 3 OR-gates 703.sub.1-3. The OR gates 703.sub.1-3 output the 0°, 60° and 120° phases, while three of the AND gates 702.sub.1-3 output inverted versions of these phases, i.e. the 180°, 240° and 300° phases. The divider core of the divider 700 consists of the first two FFs 701.sub.1,2 and the chain of FFs consists of FFs 701.sub.3-5. In this case, care needs to be taken to ensure an equal load on each branch and to minimise any different delays of the AND and OR-gates to achieve proper phase- and duty-cycle alignment. If delays of AND- and OR-gates can be balanced, the circuit is advantageous compared to the implementation in FIG. 5 because it does not use inverters for creating the inverted signals, thereby getting rid of the additional inverter delay that may reduce phase accuracy at high operating frequencies.

[0059] In each of the clock divider designs described above and shown in FIGS. 5, 6 and 7, careful design and layout is essential to ensure that every FF and every gate gets the same load, which may include the usage of dummy load stages not shown in FIGS. 5, 6 and 7. Further care needs to be taken to minimize the phase noise contribution of the divider.

[0060] It will be appreciated that each of the clock divider structures 500, 600, 700 are only examples where n=3 and each may be extended further to higher values for n (where n is an odd integer) by adding further FFs and gates to achieve a higher number of phases in the output signals 314. The concept of overlaying differential phases with a duty cycle that differs from 50% can be extended to any odd divider ratio such as a divide-by-5 or divide-by-7 divider to achieve a duty cycle of 50% and to allow phase selection with a resolution up to 360°/2n, where n is the divider ratio, i.e. a resolution of 60° for a divide by three divider, a resolution of 36° for a divide by 5 divider, a resolution of around 25.7° for a divide by 7 divider and so on.

[0061] Using such a divider enables a solution to the problem of generating a 50% duty cycle clock signal with an odd division ratio and including a phase shifter for multi-module phase alignment without additional costly circuits such as delay lines.

[0062] The clock signal dividers disclosed herein can be used to generate phase coherent sampling clocks for ADCs located in different modules by selecting a clock phase of a feedback differential multiphase divider in a PLL. The phases generated can have an accurate duty cycle of 50% from a divide-by-n divider where n is an odd integer of 3 or more.

[0063] FIG. 9 is a schematic diagram illustrating a method of calibrating a radar system of the type disclosed herein. In a first step 901, each of the plurality of radar transceiver modules is operated, and in a second step 902 a known target is detected. In step 903, a phase select signal is determined that minimises a difference in phase between the third clock signal in each follower module and in the leader module. In step 904, the phase select signal is stored in memory for each of the radar transceiver modules.

[0064] FIG. 10 is a schematic diagram illustrating a method of operating a radar system of the type disclosed herein. In a first step 1001, a phase select signal is retrieved from memory for each of the radar transceiver modules. In a second step 1002, the radar transceiver modules are operated using the retrieved phase select signals for the divide by n clock signal divider of each module.

[0065] From reading the present disclosure, other variations and modifications will be apparent to the skilled person. Such variations and modifications may involve equivalent and other features which are already known in the art of radar systems, and which may be used instead of, or in addition to, features already described herein.

[0066] Although the appended claims are directed to particular combinations of features, it should be understood that the scope of the disclosure of the present invention also includes any novel feature or any novel combination of features disclosed herein either explicitly or implicitly or any generalisation thereof, whether or not it relates to the same invention as presently claimed in any claim and whether or not it mitigates any or all of the same technical problems as does the present invention.

[0067] Features which are described in the context of separate embodiments may also be provided in combination in a single embodiment. Conversely, various features which are, for brevity, described in the context of a single embodiment, may also be provided separately or in any suitable sub-combination. The applicant hereby gives notice that new claims may be formulated to such features and/or combinations of such features during the prosecution of the present application or of any further application derived therefrom.

[0068] For the sake of completeness it is also stated that the term “comprising” does not exclude other elements or steps, the term “a” or “an” does not exclude a plurality, a single processor or other unit may fulfil the functions of several means recited in the claims and reference signs in the claims shall not be construed as limiting the scope of the claims.