RF AMPLIFIER WITH A CASCODE DEVICE

Abstract

An RF amplifier comprises a first ‘transconductance’ transistor (N.sub.CS) arranged to receive an RF input voltage (RFIN) at its gate terminal. A second ‘cascode’ transistor (N.sub.CG) has its source terminal connected to the drain terminal of the first transistor (N.sub.CS) at a node (MID). A feedback circuit portion is configured to measure a node voltage at the node (MID), to determine an average of the node voltage, to compare said average node voltage to a predetermined reference voltage (V.sub.BCG), and to generate a control voltage (CGGATE) dependent on the difference between the average node voltage and the predetermined reference voltage (V.sub.BCG). The feedback circuit portion applies the control voltage (CGGATE) to the gate terminal of the second transistor (N.sub.CG).

Claims

1. An RF amplifier comprising: a first transistor having respective first, second, and control terminals, wherein the first transistor is arranged to receive an RF input voltage at the control terminal thereof; a second transistor having respective first, second, and control terminals, wherein the second terminal of the second transistor is connected to the first terminal of the first transistor at a node; a feedback circuit portion configured to: measure a node voltage at said node; determine an average of said node voltage; compare said average node voltage to a predetermined reference voltage; generate a control voltage dependent on a difference between said average node voltage and predetermined reference voltage; and apply said control voltage to the control terminal of the second transistor.

2. The RF amplifier of claim 1, wherein the feedback circuit portion comprises an operational amplifier configured to determine the difference between the average node voltage and the predetermined reference voltage and to generate the control voltage.

3. The RF amplifier of claim 2, wherein the operational amplifier has an inverting input and a non-inverting input, wherein the average node voltage is supplied to the inverting input, and wherein the predetermined reference voltage is supplied to the non-inverting input.

4. The RF amplifier of claim 1, further comprising a filter network connected between the node and the inverting input of the op-amp, the filter network comprising a resistor and a capacitor arranged such that: a first terminal of the resistor is connected to the node; a second terminal of the resistor is connected to a first terminal of the capacitor and to the inverting input of the operational amplifier; and a second terminal of the capacitor is connected to a supply rail or ground.

5. The RF amplifier of claim 1, wherein a second filter network is connected between an input to the amplifier and the control terminal of the first transistor, wherein the second filter network comprises a second resistor and a second capacitor arranged such that: a first terminal of the second capacitor is connected to the input of the amplifier; a second terminal of the second capacitor is connected to a first terminal of the second resistor and to the control terminal of the first transistor; and a second terminal of the second resistor is connected to a second predetermined reference voltage.

6. The RF amplifier of claim 1, wherein the second terminal of the first transistor is connected to a first predetermined voltage level or supply rail.

7. The RF amplifier of claim 1, wherein the first terminal of the second transistor is connected to a second predetermined voltage level or supply rail via an impedance, wherein the first terminal of the second transistor is connected to a positive supply rail.

8. The RF amplifier of claim 7, wherein the impedance comprises an inductor connected between the first terminal of the second transistor and the second predetermined voltage level or supply rail.

9. The RF amplifier of claim 1, comprising a third capacitor connected between the control terminal of the second transistor and a supply rail or ground.

10. The RF amplifier of claim 1, further comprising: a third transistor having respective first, second, and control terminals, wherein the RF input voltage is connected across the control terminals of the first and third transistors; a fourth transistor having respective first, second, and control terminals, wherein the second terminal of the fourth transistor is connected to the first terminal of the third transistor at a second node; wherein the feedback circuit portion is further configured to: measure a second node voltage at said second node; determine an average of a sum of the first and second node voltages to produce an average summed node voltage; compare said average summed node voltage to the predetermined reference voltage; generate the control voltage dependent on a difference between said average summed node voltage and predetermined reference voltage; and apply said control voltage to the respective control terminals of the second and fourth transistors.

11. The RF amplifier of claim 10, wherein a differential RF output is taken across the first terminals of the second and fourth transistors.

12. The RF amplifier of claim 1, further comprising a fifth transistor having respective first, second, and control terminals, wherein the second terminal of the fifth transistor is connected to the first terminal of the second transistor, and wherein the output of the RF amplifier is connected to the first terminal of the fifth transistor.

13. The RF amplifier of claim 12, wherein the feedback circuit portion is configured to apply the control voltage to the respective control terminal of the fifth transistor.

14. The RF amplifier of claim 12, further comprising one or more further transistors connected between the second terminal of the fifth transistor and the first terminal of the second transistor, such that said transistors are arranged such that the first terminal of each transistor is connected to the second terminal of the transistor above it.

15. The RF amplifier of claim 14, wherein the feedback circuit portion is configured to apply the control voltage to at least one of the one or more further transistors connected between the fifth transistor and the second transistor.

16. The RF amplifier of claim 10, further comprising a sixth transistor having respective first, second, and control terminals, wherein the second terminal of the sixth transistor is connected to the first terminal of the fourth transistor.

17. The RF amplifier of claim 16, wherein the feedback circuit portion is configured to apply the control voltage to the respective control terminal of the sixth transistor.

18. The RF amplifier of claim 16, wherein a differential RF output is taken across the first terminals of the fifth and sixth transistors.

19. The RF amplifier of claim 16, further comprising one or more further transistors connected between the second terminal of the sixth transistor and the first terminal of the fourth transistor, such that said transistors are arranged such that the first terminal of each transistor is connected to the second terminal of the transistor above it.

20. The RF amplifier of claim 19, wherein the feedback circuit portion is configured to apply the control voltage to at least one of the one or more further transistors connected between the sixth transistor and the fourth transistor.

21. The RF amplifier of claim 1, wherein the RF amplifier is an RF power amplifier.

Description

BRIEF DESCRIPTION OF DRAWINGS

[0050] Certain embodiments of the invention will now be described, by way of non-limiting example only, with reference to the accompanying drawings in which:

[0051] FIG. 1 is a schematic diagram of a prior art amplifier;

[0052] FIGS. 2a and 2b are plots respectively showing the harmonic content of the MID-node voltage and the compressive behaviour of the power amplifier of FIG. 1;

[0053] FIGS. 3a and 3b are plots respectively showing an ideal rectified sine wave representing the drain current for different input drives and the harmonic content of the rectified sine wave;

[0054] FIG. 4 is a schematic diagram of an electronic device having an RF amplifier constructed from cascaded transconductance and transimpedance amplifier stages in accordance with an embodiment of the present invention;

[0055] FIG. 5 is a plot showing the waveform at the MID-node for two input drive levels with and without using the improvements of the present invention;

[0056] FIG. 6 is a plot showing the compression curve with and without using the improvements of the present invention;

[0057] FIG. 7 is a schematic diagram of a differential RF amplifier in accordance with another embodiment of the present invention; and

[0058] FIG. 8 is a schematic diagram of an RF amplifier using multiple stacked cascode devices in accordance with another embodiment of the present invention.

DETAILED DESCRIPTION

[0059] FIG. 1 shows a typical prior-art RF amplifier 100, known in the art per se. A transconductance g.sub.m device N.sub.CS translates a received RF input voltage ‘RFIN’ to an RF output current ‘RFOUT’. Typically, this g.sub.m device N.sub.CS is a short channel device because it needs to provide high transconductance in order to be efficient. However, short channel devices tend to have low breakdown voltages and thus often require cascode device for protection.

[0060] In the amplifier 100 of FIG. 1, a cascode device N.sub.CG protects N.sub.CS by controlling the average voltage level at the node 101 between them, labelled ‘MID’ (referred to herein as the ‘MID node’ 101). Depending on the voltage levels and output power requirements, more than one of these cascode devices may be stacked.

[0061] A voltage source V.sub.BCG biases the cascode device N.sub.CG via a resistor R.sub.CG. A capacitor C.sub.CG provides a small impedance path at RF frequencies to avoid or control capacitive modulation of the RF signal. A further capacitor C.sub.MOD (which may be a physical capacitor or simply the parasitic capacitance from N.sub.CG device) tends to modulate C.sub.GGATE node, which can be alleviated or adjusted with the capacitor C.sub.CG. If C.sub.GGATE is allowed to be modulated with RF, it can be used to share the stress or excess voltage between cascode devices and the g.sub.m device N.sub.CS. However, this tends to degrade the compression behaviour of the amplifier 100.

[0062] When the RF input level is increased, the average current level from the g.sub.m device N.sub.CS increases, as it is generally not biased to class-A but somewhere in class-AB operation. When the current level is increased, the voltage V.sub.gs_NCG of the cascode device N.sub.CG increases, which causes the voltage at the MID node 101 to decrease. As the voltage at the MID node 101 decreases, it modulates the transconductance in the g.sub.m device N.sub.CS, eventually compressing and saturating the input voltage to output current transfer function, thereby causing the whole amplifier 100 to compress too early.

[0063] FIG. 2a shows the amplitude of the harmonics at the MID node 101 as a function of the input power. FIG. 2b shows the output power as a function of the input power. It can be seen from Figs. 2a and 2b that the DC component (i.e. average) of the voltage at the MID node 101 decreases with increased input drive, which contributes to the compression of the amplifier 100, and thus a drop in output power. As mentioned above, this is caused by the increase of the DC (i.e. average) level of the clipped drain current with increased input drive, which is illustrated in FIGS. 3a and 3b.

[0064] In particular, FIGS. 3a and 3b illustrate the harmonic content of a theoretical rectified sine wave whose amplitude is being constantly increased, simulating increased input drive of the amplifier 100. FIG. 3a shows the drain current amplitude as a function of time. In FIG. 3b, it can be seen that the amplitude of the harmonics of the drain current (both the average and the fundamental) increase as the input drive voltage is increased.

[0065] FIG. 4 is a schematic diagram of an RF amplifier 400 in accordance with an embodiment of the present invention. Here, a feedback circuit portion 402 including an op-amp 404 is used to measure the voltage at the MID-node 401 and adjust the voltage CGGATE applied to the gate terminal (i.e. control terminal) of the cascode device N.sub.CG.

[0066] Specifically, the op-amp 404 is arranged such that its non-inverting input terminal is connected to V.sub.BCG and such that its inverting input terminal is connected to the MID node via a low-pass filter constructed from a resistor R.sub.FILT and a capacitor C.sub.FILTThis drives the average voltage at the MID node equal to the V.sub.BCG voltage. As outlined in further detail below, the low-pass filter R.sub.FILT, C.sub.FILT acts to ‘average’ the voltage at the MID node such that RF frequency components are removed, while allowing the DC component (i.e. the average) of the MID node voltage to pass to the inverting input of the op-amp 404.

[0067] The op-amp 404 acts to compare the average voltage at the MID node 401 to the predetermined voltage V.sub.BCG at the non-inverting input of the op-amp 404, and outputs a control voltage CGGATE that is proportional to the difference between them.

[0068] RF modulated signals such as those used in LTE® cellular communication systems may have varying envelope power, i.e. they have non-zero peak-to-average power ratio (PAPR). The filtering provided by R.sub.FILT and C.sub.FILT removes the RF component of the MID node voltage, leaving only the average component of the voltage at the MID node 401. In order for the closed loop to follow the RF envelope, the filter also preserves the slowly varying envelope component of the voltage at the MID node 401.

[0069] The capacitor C.sub.CG connected to the gate terminal of the cascode device N.sub.CG controls the cascode device gate impedance at RF frequencies, i.e. to avoid gate modulation due to parasitic capacitances. This capacitor C.sub.CG can also be used as a loop stability compensation for the closed loop response.

[0070] Thus in this closed loop implementation, as the input RF level increases, CGGATE is biased to a higher voltage level leaving more operation voltage margin for the g.sub.m device N.sub.CS and consequently avoiding early compression. As the average level of the MID node voltage is driven to V.sub.BCG at all times, this also provides good protection for the g.sub.m device N.sub.CS.

[0071] FIG. 5 shows the difference in voltage at the MID node 401 for two different input powers P.sub.IN—at 0 dBm and 4 dBm. The solid lines illustrate the performance of a conventional amplifier without the improvement of the present invention, while the dashed lines illustrate performance of the RF power amplifier 400 having the improvement of the present invention. As can be seen in FIG. 5, when using this invention the voltage at the MID node 401 is not reduced as much, delaying the compression of the transconductance of the g.sub.m device N.sub.CS.

[0072] The effect of this invention in the compression behaviour of the RF amplifier 400 is presented in FIG. 6, where the solid line with cross-shaped markers illustrates the output power curve associated with a conventional amplifier and where the solid line with circular markers illustrates the output power curve associated with the RF amplifier having the improvement of the present invention. The dashed line illustrates ideal uncompressed power, which is a straight, diagonal line. It can be seen from FIG. 6 that the slope of the output power curve for the amplifier in accordance with the present invention is steeper than that of the conventional amplifier, increasing the 1 dB compression point of the amplifier.

[0073] This invention can be applied also in differential implementations, where an embodiment of such a differential amplifier 700 is shown in FIG. 7. In the differential amplifier 700 of FIG. 7, there is a positive branch and a negative branch. The positive branch is constructed from a g.sub.m device N.sub.CSP and a cascode device N.sub.CGP. Similarly the negative branch is constructed from a g.sub.m device N.sub.CSN and a cascode device N.sub.CGN Each branch has a respective MID node 701P, 701N (labelled ‘MIDP’ and ‘MIDN’ respectively) between the g.sub.m and cascode devices of that branch.

[0074] Each of these branches is alike in function and structure to the stacked g.sub.m device N.sub.CS and cascode device N.sub.CG described previously with respect to FIG. 4, except now the RF input voltage RFIN is differential and is applied across the gate terminals of the positive and negative branch g.sub.m devices N.sub.CSP, N.sub.CSN; and the RF output voltage is taken across the drain terminals of the positive and negative branch cascode devices N.sub.CGP, N.sub.CGN.

[0075] In such an arrangement, a separate feedback circuit portion could be provided for each branch, or they could be controlled with the same closed loop feedback circuit portion. In the particular embodiment of FIG. 7, a single feedback circuit portion 701 is used for both branches, and is arranged such that the dedicated resistors R.sub.FILTP, R.sub.FILTN are respectively connected to the MIDP and MIDN nodes 701P, 701N at one terminal, and together at their other terminal, which are also connected to the inverting input of the op-amp 704. A filter capacitor C.sub.FILT is connected between the inverting input of the op-amp 704 and ground or a supply rail (e.g. the negative supply rail), like in the arrangement of FIG. 4. The resistors R.sub.FILTP, R.sub.FILTN and capacitor C.sub.FILT act as a low-pass filter, averaging the voltages at the MIDP and MIDN nodes 701P, 701N. Due to the arrangement of the resistors R.sub.FILTP, R.sub.FILTN, the voltages at the MIDP and MIDN nodes 701P, 701N are summed and averaged, i.e. equivalently the average voltages at the MIDP and MIDN nodes 701P, 701N are averaged.

[0076] The op-amp 704 compares the average voltage at the MIDP and MIDN nodes 701P, 701N to the reference voltage V.sub.BCG and generates at its output a control voltage CGGATE that is proportional to the difference between them. This control voltage CGGATE is applied to the gate terminals of the cascode devices N.sub.CGP, N.sub.CGN in each of the positive and negative branches.

[0077] FIG. 8 is a schematic diagram of an amplifier 800 using multiple stacked cascode devices in accordance with another embodiment of the present invention. In this arrangement, an additional cascode device N.sub.CG2 is stacked on top of the first cascode device N.sub.CG1 (equivalent to the cascode device N.sub.CG of FIG. 4), such that the source terminal of the second cascode device N.sub.CG2 is connected to the drain terminal of the first cascode device N.sub.CG1 at a second mid node 803 (or ‘MID2’) and the drain terminal of the second cascode device N.sub.CG2 is connected to AVDD_PA via the choke inductor L.sub.CHOKE (rather than the choke inductor L.sub.CHOKE being connected to the drain terminal of the first cascode device N.sub.CG1 as per FIG. 4). The RF output RFOUT is now taken from the drain terminal of the second cascode device N.sub.CG2, rather than from the drain terminal of the first cascode device N.sub.CG1.

[0078] With case of a stack of two or more cascode devices, there could be a separate closed loop for each device, or there could be a common control as is the case in the amplifier 800 of FIG. 8 (or some combination of both).

[0079] In the common control approach shown in FIG. 8, the feedback circuit portion 802 measures the voltage at the MID1 node 801 (i.e. between the drain terminal of the g.sub.m device N.sub.CS and the source terminal of the first cascode device N.sub.CG1), and averages it using the low-pass filter R.sub.FILT, C.sub.FILT in the same manner described previously. This average MID1 node voltage is compared to the reference level V.sub.BCG by the op-amp 804, which produces a voltage at its output proportional to the difference between them.

[0080] A potential divider constructed from R.sub.B1 and R.sub.B2 divides the output of the op-amp 804 and distributes control voltages CGGATE1 and CGGATE2 to the gate terminals of the first cascode device N.sub.CG1 and second cascode device N.sub.CG2 respectively, where these are dependent on the ratio of R.sub.B1 and R.sub.B2.

[0081] The techniques shown in FIGS. 7 and 8 may, of course, be combined such that the differential amplifier has multiple stacked cascode devices on each of its positive and negative branches.

[0082] Thus it will be appreciated that embodiments of the present invention provide an improved RF amplifier which utilises closed loop feedback to measure the voltage at the MID node and to drive the average voltage at the MID node toward a predetermined reference voltage. This arrangement may provide improved operation voltage margins for the g.sub.m device and avoid early compression.

[0083] While specific embodiments of the present invention have been described in detail, it will be appreciated by those skilled in the art that the embodiments described in detail are not limiting on the scope of the claimed invention.