RECONFIGURABLE POWER AMPLIFIER BASED ON PIN SWITCH AND DESIGN METHOD THEREOF

Abstract

The present disclosure provides a reconfigurable power amplifier (PA) based on a PIN switch and a design method thereof. The reconfigurable PA based on a PIN switch includes an input port, an input matching circuit, the PIN switch, a gate bias circuit, a transistor, a drain bias circuit, an output matching circuit and an output port, where the input matching network includes an input end connected to a power input end, and an output end connected to a gate of the transistor, the gate bias circuit is connected in parallel with the gate, the drain bias circuit is connected in parallel with a drain, the drain of the transistor is connected to an input end of the output matching circuit, and an output end of the output matching circuit serves as a power output.

Claims

1. A reconfigurable power amplifier (PA) based on a PIN switch, at least comprising an input port, a reconfigurable input matching circuit, a gate bias circuit, a transistor, a reconfigurable output matching circuit, a drain bias circuit and an output port, wherein the reconfigurable input matching network comprises an input end adapted and connected to the input port, and an output end connected to a gate of the transistor, and the gate bias circuit is connected in parallel with the gate of the transistor; a drain of the transistor is connected in parallel with the drain bias circuit, and connected to an input end of the output matching network; the reconfigurable input matching circuit comprises a trunk microstrip and reconfigurable structures, and the trunk microstrip is connected to the input port, the transistor and the bias circuits; the trunk microstrip is connected to a plurality of reconfigurable structures; and the reconfigurable structures each are composed of a PIN switch and a microstrip by connecting in series; the output port is adapted and connected to the output matching circuit; the reconfigurable output matching circuit comprises a PIN switch 1, a PIN switch 2, a first microstrip TL1, a second microstrip TL2, a third microstrip TL3, a fourth microstrip TL4, a fifth microstrip TL5, a sixth microstrip TL6 and a seventh microstrip TL7, wherein the TL1, the TL2, the TL3 and the TL4 each are a series microstrip, while the TL5, the TL6 and the TL7 each are a parallel microstrip; the drain of the transistor is connected to one end of the first microstrip TL1, the other end of the first microstrip TL1 is connected to one end of the second microstrip TL2 and one end of the fifth microstrip TL5, the other end of the second microstrip TL2 is connected to one end of the third microstrip TL3 and one end of the PIN switch 1, the other end of the PIN switch 1 is connected to the sixth microstrip TL6, the other end of the third microstrip TL3 is connected to one end of the fourth microstrip TL4 and one end of the PIN switch 2, and the other end of the PIN switch 2 is connected to the seventh microstrip TL7; when the PIN switch 1 is closed, and the PIN switch 2 is open, the first microstrip TL1, the second microstrip TL2, the third microstrip TL3, the fourth microstrip TL4, the fifth microstrip TL5 and the sixth microstrip TL6 are jointly formed into a matching circuit, but the seventh microstrip TL7 is unavailable for matching; and when the PIN switch 1 is open, and the PIN switch 2 is closed, the first microstrip TL1, the second microstrip TL2, the third microstrip TL3, the fourth microstrip TL4, the fifth microstrip TL5 and the seventh microstrip TL7 are jointly formed into a matching circuit, but the sixth microstrip TL6 is unavailable for matching; and the drain bias circuit comprises an eighth microstrip TL8, a ninth microstrip TL9, a tenth microstrip TL10 and a blocking capacitor C1, wherein one end of the eighth microstrip TL8 is connected to the drain of the transistor, the other end of the eighth microstrip TL8 is connected to the ninth microstrip TL9 and the tenth microstrip TL10, the ninth microstrip TL9 is a parallel open-circuited microstrip, and the other end of the tenth microstrip TL10 is connected to a drain power supply.

2. The reconfigurable PA based on a PIN switch according to claim 1, wherein the reconfigurable output matching circuit comprises a reconfigurable structure.

3. The reconfigurable PA based on a PIN switch according to claim 1, wherein the reconfigurable structures each are combined and switched to implement band switching at 1.75 GHz and 2.6 GHz.

4. The reconfigurable PA based on a PIN switch according to claim 1, wherein the gate bias circuit is structurally identical to the drain bias circuit.

5. A design method of a reconfigurable power amplifier (PA) based on a PIN switch, comprising the following steps: step S1: repeatedly performing load pull and source pull on a gallium nitride (GaN) high electron mobility transistor (HEMT) CGH40010F transistor to obtain an optimum load impedance and an optimum source impedance of the transistor at a power-added efficiency (PAE) and a maximum output power; step 2: designing a gate bias network and a drain bias network based on a concept of implementing impedance transformation with a quarter-wave microstrip, to ensure a stable direct-current (DC) power voltage of the PA, wherein three microstrips TL8, TL9, TL10 and a short-circuited capacitor C1 are used, the microstrips TL8 and TL10 each are a series microstrip, and the microstrip TL9 is a parallel microstrip; step S3: designing a reconfigurable output matching circuit, optimizing a reconfigurable output matching structure through loci along a Smith chart after optimum load impedances at different frequencies pass through microstrips, and searching suitable electrical length and characteristic impedance of each of the microstrips, wherein the reconfigurable output matching circuit comprises a PIN switch 1, a PIN switch 2, a first microstrip TL1, a second microstrip TL2, a third microstrip TL3, a fourth microstrip TL4, a fifth microstrip TL5, a sixth microstrip TL6 and a seventh microstrip TL7, wherein the TL1, the TL2, the TL3 and the TL4 each are a series microstrip, while the TL5, the TL6 and the TL7 each are a parallel microstrip; the drain of the transistor is connected to one end of the first microstrip TL1, the other end of the first microstrip TL1 is connected to one end of the second microstrip TL2 and one end of the fifth microstrip TL5, the other end of the second microstrip TL2 is connected to one end of the third microstrip TL3 and one end of the PIN switch 1, the other end of the PIN switch 1 is connected to the sixth microstrip TL6, the other end of the third microstrip TL3 is connected to one end of the fourth microstrip TL4 and one end of the PIN switch 2, and the other end of the PIN switch 2 is connected to the seventh microstrip TL7; when the PIN switch 1 is closed, and the PIN switch 2 is open, the first microstrip TL1, the second microstrip TL2, the third microstrip TL3, the fourth microstrip TL4, the fifth microstrip TL5 and the sixth microstrip TL6 are jointly formed into a matching circuit, but the seventh microstrip TL7 is unavailable for matching; and when the PIN switch 1 is open, and the PIN switch 2 is closed, the first microstrip TL1, the second microstrip TL2, the third microstrip TL3, the fourth microstrip TL4, the fifth microstrip TL5 and the seventh microstrip TL7 are jointly formed into a matching circuit, but the sixth microstrip TL6 is unavailable for matching; step S4: designing a reconfigurable structure, wherein the reconfigurable structure is composed of a PIN switch and a reconfigurable stub, the output matching network is reconfigured by changing an on-off state of the PIN switch in the reconfigurable structure, and since an electrical length and a characteristic impedance of each of the microstrips TL1, TL2, TL3, TL4, TL5 are determined, continuously adjusting a characteristic impedance and an electrical length of the microstrip TL6 at 1.75 GHz makes an output impedance at a point G to be right 50Ω; and likewise, continuously adjusting a characteristic impedance and an electrical length of the microstrip TL7 at 2.6 GHz makes the output impedance at the point G to be right 50 Ω; step S5: designing a reconfigurable input matching network in a method same as that of the output matching circuit, to make the reconfigurable PA perform better; and step S6: constructing an overall circuit structure in combination with steps S1, S2, S3, S4, S5, and performing circuit simulation and optimization with advanced design system (ADS) software, thereby implementing optimal performance.

6. The design method of a reconfigurable PA based on a PIN switch according to claim 1, wherein the drain bias circuit comprises an eighth microstrip TL8, a ninth microstrip TL9, a tenth microstrip TL10 and a blocking capacitor C1, wherein one end of the eighth microstrip TL8 is connected to the drain of the transistor, the other end of the eighth microstrip TL8 is connected to the ninth microstrip TL9 and the tenth microstrip TL10, the ninth microstrip TL9 is a parallel open-circuited microstrip, and the other end of the tenth microstrip TL10 is connected to a drain power supply.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0030] FIG. 1 illustrates a schematic structural view of a reconfigurable PA based on a PIN switch according to the present disclosure.

[0031] FIG. 2 illustrates a schematic view of a network topology of a bias circuit according to the present disclosure.

[0032] FIG. 3a illustrates a schematic structural view of a conventional reconfigurable matching circuit.

[0033] FIG. 3b illustrates a schematic structural view of an optimized reconfigurable matching circuit.

[0034] FIG. 4a illustrates a schematic view of a simulation result of an S parameter of a reconfigurable matching circuit at f.sub.1 according to the present disclosure.

[0035] FIG. 4b illustrates a schematic view of a simulation result of an S parameter of a reconfigurable matching circuit at f.sub.2 according to the present disclosure.

[0036] FIG. 5a illustrates a schematic view of a simulation result for an output power, an efficiency and a gain of a reconfigurable PA based on a PIN switch at f.sub.1 according to the present disclosure.

[0037] FIG. 5b illustrates a schematic view of a simulation result for an output power, an efficiency and a gain of a reconfigurable PA based on a PIN switch at f.sub.1 according to the present disclosure.

DETAILED DESCRIPTION OF THE EMBODIMENTS

[0038] To make the objectives, technical solutions and advantages of the present disclosure clearer and more comprehensible, specific implementations of the present disclosure will be further described below in detail in conjunction with the embodiments and accompanying drawings.

[0039] Existing reconfigurable PAs mainly present the following defects in design, namely reconfigurable devices are designed hardly and undesirably with certain influences on the circuits, matching circuits of the reconfigurable PAs are structured simply and implemented hardly, and the PAs are also obstructed by difficult debugging because influences from changes of matching circuit structures on overall performance cannot be observed simultaneously during debugging.

[0040] In view of the above problems, an objective of the present disclosure is to provide a reconfigurable PA based on a PIN switch and a design method thereof. The present disclosure changes the structure of the output matching circuit network by changing a working state of the PIN switch in the output matching circuit, thereby implementing the reconfigurable function, and achieving desirable working performance of the PA at different modes and bands; and in order to further improve the performance of the reconfigurable PA, the present disclosure uses the same method to design the input matching circuit.

[0041] FIG. 1 illustrates a schematic structural view of a reconfigurable PA based on a PIN switch according to the present disclosure. The reconfigurable PA based on a PIN switch includes a reconfigurable input matching network, a gate bias network, a transistor, a drain bias network and a reconfigurable output matching network, where

[0042] the reconfigurable input matching network includes an input end adapted and connected to an input port, and an output end connected to a gate of the transistor, and the gate bias circuit is connected in parallel with the gate of the transistor;

[0043] a drain of the transistor is connected in parallel with the drain bias circuit, and connected to an input end of the reconfigurable output matching network;

[0044] the reconfigurable input matching circuit includes a trunk microstrip and reconfigurable structures;

[0045] the trunk microstrip is respectively connected to the input port, the transistor and the bias circuits, and the trunk microstrip is connected to a plurality of reconfigurable structures;

[0046] the reconfigurable structures each are composed of a PIN switch and a microstrip by connecting in series; and

[0047] an output port is adapted and connected to the reconfigurable output matching circuit.

[0048] FIG. 2 illustrates a network topology of a drain bias circuit. While the drain bias circuit supplies power to the transistor, a loss on a band where the reconfigurable PA works is minimum, and the drain bias circuit includes an eighth microstrip TL8, a ninth microstrip TL9, a tenth microstrip TL10 and a blocking capacitor C1, where one end of the eighth microstrip TL8 is connected to the drain of the transistor, the other end of the eighth microstrip TL8 is connected to the ninth microstrip TL9 and the tenth microstrip TL10, the ninth microstrip TL9 is a parallel open-circuited microstrip, and the other end of the tenth microstrip TL10 is connected to a drain power supply.

[0049] The gate bias circuit is structurally identical to the drain bias circuit.

[0050] Further, the descriptions are made to parameter calculation of the microstrips of the drain bias circuit:

[0051] The microstrips each involve two specific parameters, namely the characteristic impedance Z.sub.n and an electrical length θ.sub.n where the characteristic impedance Z.sub.n is the free parameter, and the electrical length θ.sub.n is the parameter to be sought. For ease of description, when the working band has the working frequency points of f.sub.1 and f.sub.2, corresponding electrical lengths and characteristic impedances are θ.sub.1 and θ.sub.2, Z.sub.1 and Z.sub.2, n=f.sub.2/f.sub.1.

[0052] The network topology of the drain bias circuit includes series microstrips TL8 and TL10, a parallel microstrip TL10 and a short-circuited capacitor C1. As the TL8 and the TL9 each have an electrical length of 90°, a characteristic impedance of 50Ω, and a frequency of 2.6 GHz, the point B at 2.6 GHz has an impedance of 0Ω; and through the TL8 having the electrical length of 90°, the impedance of the point C at 2.6 GHz is infinitely great. With no RF signal passing through the bias circuit, the DC power supply is damaged. However, the RF open circuit hasn't been implemented at 1.75 GHz, and in this case, the electrical length of the TL10 needs to be calculated. As the point A is grounded through the short-circuited capacitor C1, the point A has an impedance of 0Ω.

[0053] The impedance from the point A to the point B is given by

[00001]$\begin{array}{cc}{Z}_{B1}\left(f_1\right)=Z_{10}*\frac{Z_A+{\mathrm{jZ}}_{10}*\tan \left({\theta }_{10}\right)}{Z_{10}+{\mathrm{jZ}}_A*\tan \left({\theta }_{10}\right)}& \left(1\right)\end{array}$

[0054] The impedance from the ninth microstrip TL9 to the point B is given by

[00002]$\begin{array}{cc}{Z}_{B2}\left(f_1\right)=Z_9*\frac{Z_L+{\mathrm{jZ}}_9*\tan \left({\theta }_9/n\right)}{Z_9+{\mathrm{jZ}}_L*\tan \left({\theta }_9/n\right)}& \left(2\right)\end{array}$

[0055] The impedance of the point B at f.sub.1 is given by

[00003]$\begin{array}{cc}{Z}_B=\frac{Z_{B1}*Z_{B2}}{Z_{B1}+Z_{B2}}& \left(3\right)\end{array}$

[0056] The impedance from the point B to the point C is given by

[00004]$\begin{array}{cc}{Z}_C\left(f_1\right)=Z_8*\frac{Z_B+j{Z}_8*\tan \left({\theta }_8/n\right)}{Z_8+j{Z}_B*\tan \left({\theta }_8/n\right)}& \left(4\right)\end{array}$

[0057] To implement the RF open circuit, the impedance Z.sub.c of the point C at 1.75 GHz must be infinitely great. With the known Z.sub.A, the known characteristic impedance and electrical length of each of the eighth microstrip TL8 and the ninth microstrip TL9, and the known characteristic impedance of the tenth microstrip TL10, the electrical length of the tenth microstrip TL10 can be calculated with the above equation.

[0058] FIG. 3a illustrates a network topology of a matching structure of a conventional reconfigurable matching circuit. Matching networks for required bands are sequentially designed, and integrated together through PIN switches, thereby forming the reconfigurable matching circuits. The matching circuits are approximately independent of each other and are not affected to each other; and the matching networks are selected by the switches to implement normal work at different modes and different frequencies. Compared with other reconfigurable matching structures, the reconfigurable matching structure herein is designed simply. Nevertheless, its disadvantages are also obvious, namely, frequency points that can be integrated in the same PA are very limited; and with the increase in the working frequency points of the PA, the corresponding matching networks are also added and the number of required switches is also rising gradually, which will enlarge the size of the PA with a higher cost.

[0059] FIG. 3b illustrates a schematic topological view of an optimized reconfigurable output matching network. The reconfigurable output matching network implements band switching by adding the reconfigurable structure composed of the PIN switch and the reconfigurable microstrip, and includes a PIN switch 1, a PIN switch 2, a first microstrip TL1, a second microstrip TL2, a third microstrip TL3, a fourth microstrip TL4, a fifth microstrip TL5, a sixth microstrip TL6 and a seventh microstrip TL7, where the TL1, the TL2, the TL3 and the TL4 each are a series microstrip, while the TL5, the TL6 and the TL7 each are a parallel microstrip; the drain of the transistor is connected to the first microstrip TL1, the other end of the first microstrip TL1 is connected to one end of the second microstrip TL2 and one end of the fifth microstrip TL5, one end of the second microstrip TL2 is connected to one end of the third microstrip TL3 and one end of the PIN switch 1, the other end of the PIN switch 1 is connected to the sixth microstrip TL6, the other end of the third microstrip TL3 is connected to one end of the fourth microstrip TL4 and one end of the PIN switch 2, and the other end of the PIN switch 2 is connected to the seventh microstrip TL7; when the PIN switch 1 is closed, and the PIN switch 2 is open, the first microstrip TL1, the second microstrip TL2, the third microstrip TL3, the fourth microstrip TL4, the fifth microstrip TL5 and the sixth microstrip TL6 are jointly formed into a matching circuit, but the seventh microstrip TL7 is unavailable for matching, thereby implementing output matching at 1.75 GHz; and when the PIN switch 1 is open, and the PIN switch 2 is closed, the first microstrip TL1, the second microstrip TL2, the third microstrip TL3, the fourth microstrip TL4, the fifth microstrip TL5 and the seventh microstrip TL7 are jointly formed into a matching circuit, but the sixth microstrip TL6 is unavailable for matching, thereby implementing output matching at 2.6 GHz. The optimized reconfigurable output matching structure has the smaller circuit size, better debugging, less loss and simpler structure over the conventional reconfigurable matching structure.

[0060] Further, the descriptions are further made to the working principle of the reconfigurable matching network:

[0061] The specific parameters of the microstrips are the electrical length θ.sub.n and the characteristic impedance Z.sub.n. In order to determine specific parameters of each microstrip, load pull is used to obtain optimum fundamental impedances at central frequencies f.sub.1 and f.sub.2, specifically, the optimum fundamental impedances Z.sub.f1 and Z.sub.f2 at the central frequencies 1.75 GHz and 2.6 GHz.

[0062] The impedance from the point C to the point D through the first microstrip TL1 is given by

[00005]$\begin{array}{cc}{Z}_{D1}\left(f_1\right)=Z_1*\frac{Z_{C1}+j{Z}_1*\tan \left({\theta }_1\right)}{Z_1+j{Z}_{C1}*\tan \left({\theta }_1\right)}& \left(5\right)\end{array}$$\begin{array}{cc}{Z}_{D1}\left(f_2\right)=Z_1*\frac{Z_{C2}+j{Z}_1*\tan \left(n*{\theta }_1\right)}{Z_1+j{Z}_{C2}*\tan \left(n*{\theta }_1\right)}& \left(6\right)\end{array}$

[0063] The impedance from the open-circuited point to the point D through the fifth microstrip TL5 is given by

[00006]$\begin{array}{cc}{Z}_{D2}\left(f_1\right)=\frac{-j{Z}_5}{\tan \left({\theta }_5\right)}& \left(7\right)\end{array}$$\begin{array}{cc}{Z}_{D2}\left(f_2\right)=\frac{-j{Z}_5}{\tan \left(n*{\theta }_5\right)}& \left(8\right)\end{array}$

[0064] Therefore, the total impedance of the point D is

[00007]$\begin{array}{cc}{Z}_D\left(f_1\right)=\frac{Z_{D1}\left(f_1\right)*Z_{D2}\left(f_1\right)}{Z_{D1}{f}_1)+Z_{D2}{f}_1)}& \left(9\right)\end{array}$$\begin{array}{cc}{Z}_D\left(f_2\right)=\frac{Z_{D1}\left(f_2\right)*Z_{\mathrm{D2}}\left(f_2\right)}{Z_{D1}\left(f_2\right)+Z_{D2}\left(f_2\right)}& \left(10\right)\end{array}$

[0065] The impedance from the point D to the point E through the second microstrip TL2 is given by

[00008]$\begin{array}{cc}{Z}_{E1}\left(f_1\right)=Z_2*\frac{Z_D\left(f_1\right)+j{Z}_2*\tan \left({\theta }_2\right)}{Z_2+j{Z}_D\left(f_1\right)*\tan \left({\theta }_2\right)}& \left(11\right)\end{array}$$\begin{array}{cc}{Z}_{E1}\left(f_2\right)=Z_2*\frac{Z_D\left(f_2\right)+j{Z}_2*\tan \left(n*{\theta }_2\right)}{Z_2+j{Z}_D\left(f_2\right)*\tan \left(n*{\theta }_2\right)}& \left(12\right)\end{array}$

[0066] The impedance from the open-circuited point to the point E through the sixth microstrip TL6 is given by

[00009]$\begin{array}{cc}{Z}_{E2}\left(f_1\right)=\frac{-j{Z}_6}{\tan \left({\theta }_6\right)}& \left(13\right)\end{array}$

[0067] Therefore, the total impedance of the point E at the f.sub.2, is

[00010]$\begin{array}{cc}{Z}_E\left(f_1\right)=\frac{Z_{E1}\left(f_1\right)*Z_{E2}\left(f_1\right)}{Z_{E1}{f}_1)+Z_{E2}{f}_1)}& \left(14\right)\end{array}$

[0068] Moreover, as the sixth microstrip TL6 is unavailable for matching at the f.sub.2, the impedance of the point E at the f.sub.2 is given by

Z.sub.E(f.sub.2)=Z.sub.E1(f.sub.2)  (15)

[0069] The impedance from the point E to the point F through the third microstrip TL3 is given by

[00011]$\begin{array}{cc}{Z}_F\left(f_1\right)=Z_3*\frac{Z_E\left(f_1\right)+j{Z}_3*\tan \left({\theta }_3\right)}{Z_3+j{Z}_E\left(f_1\right)*\tan \left({\theta }_3\right)}& \left(16\right)\end{array}$$\begin{array}{cc}{Z}_{F1}\left(f_2\right)=Z_3*\frac{Z_E\left(f_2\right)+j{Z}_3*\tan \left(n*{\theta }_3\right)}{Z_3+j{Z}_E\left(f_2\right)*\tan \left(n*{\theta }_3\right)}& \left(17\right)\end{array}$

[0070] The impedance from the open-circuited point to the point E through the seventh microstrip TL7 is given by

[00012]$\begin{array}{cc}{Z}_{F2}\left(f_2\right)=\frac{-j{Z}_7}{\tan \left(n*{\theta }_7\right)}& \left(18\right)\end{array}$

[0071] Moreover, as the seventh microstrip TL7 is unavailable for matching at the f.sub.1, the impedance of the point F at the f.sub.1 is given by

Z.sub.F(f.sub.1)=Z.sub.F1(f.sub.1)  (19)

[0072] Therefore, the total impedance of the point F at the f.sub.2 is

[00013]$\begin{array}{cc}{Z}_F\left(f_2\right)=\frac{Z_{F1}\left(f_2\right)*Z_{F2}\left(f_2\right)}{Z_{F1}{f}_2)+Z_{F2}{f}_2)}& \left(20\right)\end{array}$

[0073] The impedance from the point F to the point G through the fourth microstrip TL4 is given by

[00014]$\begin{array}{cc}{Z}_G\left(f_1\right)=Z_4*\frac{Z_F\left(f_1\right)+j{Z}_4*\tan \left({\theta }_4\right)}{Z_4+j{Z}_F\left(f_1\right)*\tan \left({\theta }_4\right)}& \left(21\right)\end{array}$$\begin{array}{cc}{Z}_{F1}\left(f_2\right)=Z_4*\frac{Z_F\left(f_2\right)+j{Z}_4*\tan \left(n*{\theta }_4\right)}{Z_4+j{Z}_F\left(f_2\right)*\tan \left(n*{\theta }_4\right)}& \left(22\right)\end{array}$

[0074] Through the reconfigurable output matching network, the actual impedance Z.sub.in.sub.opt is used as the designed output impedance. However, as the switches are not ideal devices and will affect to each other, the impedance is to be tuned depending on the power and the efficiency.

[0075] If the point G has an impedance of 50Ω at two frequencies, it is indicated that the transistor and the load are well matched.

[0076] The present disclosure provides a design method of a reconfigurable PA based on a PIN switch, including the following steps:

[0077] Step S1: Repeatedly perform load pull and source pull on a GaN HEMT CGH40010F transistor to obtain an optimum load impedance and an optimum source impedance of the transistor at a PAE and a maximum output power.

[0078] Step 2: Design a gate bias network and a drain bias network based on a concept of implementing impedance transformation with a quarter-wave microstrip, to ensure a stable DC power voltage of the PA. However, since a single quarter-wave microstrip cannot implement the RF open circuit on two bands, the bias circuit is optimized with three microstrips TL8, TL9, TL10 and a short-circuited capacitor C1, where the microstrips TL8 and TL10 each are a series microstrip, the microstrip TL9 is a parallel microstrip, and the microstrips TL8, TL9, TL10 have the electrical length and the characteristic impedance of θ.sub.8, θ.sub.9, θ.sub.10 and Z.sub.8, Z.sub.9, Z.sub.10, respectively. In order to implement the RF open circuit at 1.75 GHz and 2.6 GHz, and prevent the RF signal from damaging the current source, the above Equations (1) (2) (3) need to be met at the same time to be equivalent to the quarter-wave line. The transmission matrix of the quarter-wave line is

[00015]$\left[\begin{array}{cc}A& B\\ C& D\end{array}\right]=\left[\begin{array}{cc}0& \pm {\mathrm{jZ}}_T\\ \frac{\pm j}{Z_T}& 0\end{array}\right]=\left[\begin{array}{cc}\cos {\theta }_8& {\mathrm{jZ}}_8\sin {\theta }_8\\ j\frac{1}{Z_8\sin {\theta }_8}& \cos {\theta }_8\end{array}\right]*\left[\begin{array}{cc}1& {\mathrm{jZ}}_9\tan {\theta }_9\\ 0& 1\end{array}\right]*\left[\begin{array}{cc}\cos {\theta }_{10}& {\mathrm{jZ}}_8\sin {\theta }_{10}\\ j\frac{1}{Z_{10}\sin {\theta }_{10}}& \cos {\theta }_{10}\end{array}\right]$

(23)

[0079] The characteristic parameters of the microstrips are obtained by calculation.

[0080] Step S3: Design a reconfigurable output matching circuit, observe loci along a Smith chart after optimum load impedances at different frequencies pass through microstrips, and search suitable electrical length and characteristic impedance of each of the microstrips with an optimized reconfigurable output matching structure. In response to the central frequency f.sub.1, the output matching network is equivalently composed of the series microstrips TL1, TL2, TL3, TL4 and the parallel microstrips TL5, TL6; and in response to the central frequency f.sub.2, the output matching network is equivalently composed of the series microstrips TL1, TL2, TL3, TL4 and the parallel microstrips TL5, TL7. The electrical length and the characteristic impedance of the microstrip TL1 are θ.sub.1 and Z.sub.1, and the impedance of the point D through the microstrip TL1 is given by

[00016]$\begin{array}{cc}{Z}_{D1}\left(f_1\right)=Z_1*\frac{Z_{C1}+j{Z}_1*\tan \left({\theta }_1\right)}{Z_1+j{Z}_{C1}*\tan \left({\theta }_1\right)}& \left(24\right)\end{array}$$\begin{array}{cc}{Z}_{D1}\left(f_2\right)=Z_1*\frac{Z_{C2}+j{Z}_1*\tan \left(n*{\theta }_1\right)}{Z_1+j{Z}_{C2}*\tan \left(n*{\theta }_1\right)}& \left(25\right)\end{array}$

[0081] The results are substituted into the Equations (7)-(22). Due to the heavy calculation burden, the characteristic parameter and electrical length of each microstrip are calculated with matlab, and the final impedance at the point G is near the standard 50Ω.

[0082] Step S4: Design a reconfigurable structure, where the reconfigurable structure is composed of a PIN switch and a reconfigurable stub, the output matching network is reconfigured by changing an on-off state of the PIN switch in the reconfigurable structure, and since electrical lengths θ and characteristic impedances Z of the reconfigurable microstrips are determined upon determination of a trunk line of the matching circuit, namely an electrical length and a characteristic impedance of each of the microstrips TL1, TL2, TL3, TL4, TL5 are determined, continuously adjusting a characteristic impedance and an electrical length of the microstrip TL6 at 1.75 GHz makes an output impedance at a point G to be right 50Ω; and likewise, continuously adjusting a characteristic impedance and an electrical length of the microstrip TL7 at 2.6 GHz makes the output impedance at the point G to be right 50Ω;

[0083] Step S5: Design a reconfigurable input matching network in a method same as that of the output matching circuit, to make the reconfigurable PA perform better.

[0084] Step S6: Construct an overall circuit structure in combination with Steps S1, S2, S3, S4, S5, and perform circuit simulation and optimization with ADS software, thereby implementing optimal performance.

[0085] The technical effects of the present disclosure are further described below in conjunction with simulation experiments. FIG. 4a illustrates a schematic view of a simulation result of an S parameter of a reconfigurable matching circuit at f.sub.1 according to the present disclosure; FIG. 4b illustrates a schematic view of a simulation result of an S parameter of a reconfigurable matching circuit at f.sub.2 according to the present disclosure; FIG. 5a illustrates a schematic view of a simulation result for an output power, an efficiency and a gain of a reconfigurable PA based on a PIN switch at f.sub.1 according to the present disclosure; and FIG. 5b illustrates a schematic view of a simulation result for an output power, an efficiency and a gain of a reconfigurable PA based on a PIN switch at f.sub.1 according to the present disclosure. As can be seen from the simulation results, when the central frequency is 1.75 GHz, the saturated output power is 41.63 dBm, the gain is 11.63 dB, and the drain efficiency is 69%; when the central frequency is 2.6 GHz, the saturated output power is 40.48 dBm, the gain is 10.48 dB, and the drain efficiency is 65%; and compared with other dual-band PAs which have the drain efficiency of about 60% and the output power of about 40 dBm, the present disclosure obviously improves the performance and achieves the expected effects.

[0086] The above description of examples is merely provided to help illustrate the method of the present disclosure and a core idea thereof. It should be noted that several improvements and modifications may be made by persons of ordinary skill in the art without departing from the principle of the present disclosure, and these improvements and modifications should also fall within the protection scope of the present disclosure. Various amendments to these embodiments are apparent to those of professional skill in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present disclosure. Thus, the present disclosure is not limited to the embodiments shown herein but falls within the widest scope consistent with the principles and novel features disclosed herein.