Double-masking technique for increasing fabrication yield in superconducting electronics

Abstract

An improved microfabrication technique for Josephson junctions in superconducting integrated circuits, based on the use of a double-layer lithographic mask for partial anodization of the side-walls and base electrode of the junctions. The top layer of the mask is a resist material, and the bottom layer is a dielectric material chosen so to maximize adhesion between the resist and the underlying superconducting layer, be etch-compatible with the underlying superconducting layer, and be insoluble in the resist and anodization processing chemistries. The superconductor is preferably niobium, under a silicon dioxide layer, with a conventional photoresist or electron-beam resist as the top layer. This combination results in a substantial increase in the fabrication yield of high-density superconducting integrated circuits, increase in junction uniformity and reduction in defect density. A dry etch more compatible with microlithography may be employed.

Claims

1. An integrated circuit based on a plurality of Nb-based Josephson junctions, comprising: a Josephson junction trilayer comprising a lower Nb-containing superconductive layer, an insulating layer, an upper Nb-containing superconductive layer, and sidewalls thereof, on a substrate, fabricated into at least one Josephson junction having a defined junction area less than 1 square micron, the at least one Josephson junction comprising an anodized double oxide layer of AlOx on top of NbOx, wherein the double oxide is patterned in a vacuum processing chamber using a dry etch process to provide a structure surrounding the defined junction comprising a continuous NbOx layer which extends vertically along the sidewalls of the lower Nb-containing superconductive layer, the insulating layer, and the upper Nb-containing superconductive layer; and a silicon dioxide layer formed directly on top of the upper Nb-containing superconductor layer.

2. The integrated circuit of claim 1, wherein the dry etch process comprises ion milling with a neutral beam of argon atoms.

3. The integrated circuit of claim 1, wherein the dry etch process comprises the two sequential steps of: using a chlorine-based plasma etch to remove the top layer of AlOx; and using a fluorine-based plasma etch to remove the bottom layer of NbOx.

4. The integrated circuit of claim 1, wherein the defined junction area comprises a layer of photoresist on top of the silicon dioxide, wherein the photoresist has a higher adhesion for the silicon dioxide than the upper Nb-containing superconductive layer.

5. The integrated circuit of claim 1, wherein the Josephson junction trilayer comprises a sequence of Nb, Al, AlOx, and Nb, wherein the AlOx layer is between 1-2 nm thick.

6. The integrated circuit of claim 1, wherein the at least one Josephson junction comprises at least one thousand Josephson junctions.

7. The integrated circuit of claim 6, wherein the at least one thousand Josephson junctions each have operating superconducting critical currents that are within about 1% of a respective design specification.

8. The integrated circuit of claim 6, wherein the integrated circuit comprises a plurality of functional circuits, each configured to operate at clock frequency of at least 100 GHz.

9. The integrated circuit of claim 1, wherein the integrated circuit comprises at least one functional circuit configured to operate at clock frequency of at least 100 GHz.

10. A Josephson junction integrated circuit, produced by a process comprising: depositing a Josephson junction trilayer comprising a lower superconductor layer, an insulating layer, and an upper superconductor layer, on a substrate; depositing a silicon dioxide layer directly on top of the upper superconductor layer by plasma-enhanced chemical vapor deposition (PECVD); depositing a photoresist having an adhesion to the silicon dioxide greater than a respective adhesion of the photoresist to the upper superconductor layer; patterning the photoresist; etching through the silicon dioxide layer and the upper superconductor layer to expose the insulating layer; anodizing exposed portions of the insulating layer and a portion of the lower superconductor layer, to thereby increase a layer thickness of the anodized insulating layer and the portion of the lower superconductor layer, with respect to the insulating layer and the portion of the lower superconductor layer, to create a continuous anodized portion of the lower superconductor layer which surrounds and extends vertically along sidewalls of the lower superconductor layer, the insulating layer, and the upper superconductor layer, and which interrupts the anodized insulating layer; and dry etching the anodized insulating layer and the portion of the lower superconductor layer, to produce a Josephson junction device.

11. The Josephson junction circuit according to claim 10, further comprising removing the photoresist.

12. The Josephson junction circuit according to claim 10, wherein the dry etching comprises ion-milling with a neutral beam of argon (Ar) atoms.

13. The Josephson junction circuit according to claim 10, wherein the dry etching comprises plasma etching with a chlorine-based plasma and then a fluorine-based plasma.

14. The Josephson junction circuit according to claim 13, wherein the dry etching comprises reactive ion etching.

15. The Josephson junction circuit according to claim 13, wherein the dry etching comprises an inductively coupled plasma etching.

16. The Josephson junction circuit according to claim 10, wherein the lower superconductor layer comprises niobium, the insulating layer comprises oxidized aluminum, and the upper superconductor layer comprises niobium.

17. The Josephson junction circuit according to claim 10, wherein the silicon dioxide layer is formed by chemical vapor deposition with a layer thickness of between about 5-300 nm.

18. A method of forming a Josephson junction integrated circuit, comprising: depositing a Josephson junction trilayer comprising a lower superconductor layer, an insulating layer, and an upper superconductor layer, on a substrate; depositing a silicon dioxide layer directly on top of the upper superconductor layer by plasma-enhanced chemical vapor deposition (PECVD); depositing a photoresist having an adhesion to the silicon dioxide greater than a respective adhesion of the photoresist to the upper superconductor layer; patterning the photoresist; etching through the silicon dioxide layer and the upper superconductor layer to expose the insulating layer; anodizing exposed portions of the insulating layer and a portion of the lower superconductor layer, creating a continuous anodized portion of the lower superconductor layer surrounding and extending vertically along sidewalls of the lower superconductor layer, the insulating layer, and the upper superconductor layer of a defined junction and causing a discontinuity of the anodized insulating layer between the insulating layer and the anodized insulating layer; and dry etching the anodized insulating layer and the portion of the lower superconductor layer, to produce a Josephson junction device.

19. The method according to claim 18, wherein the integrated circuit is patterned to define a plurality of interconnected Josephson junctions formed, further comprising operating the plurality of Josephson junctions at a clock rate of at least 100 GHz.

20. The method according to claim 18, wherein the lower superconductor layer comprises niobium, the insulating layer comprises oxidized aluminum, and the upper superconductor layer comprises niobium; wherein the silicon dioxide layer is formed by chemical vapor deposition with a layer thickness of between about 5-300 nm; and wherein the dry etching comprises at least one of: ion-milling with a neutral beam of argon (Ar) atoms; inductively coupled plasma etching with a chlorine-based plasma and then a fluorine-based plasma; and reactive ion etching.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 shows a cross section of a wafer having Nb/Al/AlO.sub.x/Nb layers as used in the fabrication of superconducting devices such as a Josephson junction.

(2) FIG. 2 shows a modification of the prior art process whereby dielectric layer of SiO.sub.2 is deposited to act as an adhesion layer between the Nb and the photoresist layer deposited during the next process step.

(3) FIG. 3 shows application of a photoresist layer on top of the silicon dioxide layer in accordance with one aspect of the invention.

(4) FIG. 4 shows the photoresist area that defines the junction area after exposure and development of the photoresist.

(5) FIG. 5 shows the etching of the SiO.sub.2 adhesion layer and Nb counter-electrode down to the AlO.sub.x/Al barrier layer.

(6) FIG. 6A shows the results of a selective anodization step whereby all the exposed Al and part of the underlying Nb are converted to insulating oxides.

(7) FIG. 6B shows a magnified view of the region inside the small dashed box in FIG. 6A.

(8) FIG. 7 shows the removal of the photoresist layer.

(9) FIG. 8 shows the result of coating and patterning of another photoresist layer designed to produce a protective anodization ring around the junction area.

(10) FIG. 9 shows the etching (by Ar ion milling or dry reactive ion etching) of the anodized oxide (both AlO.sub.x and NbO.sub.x layers) except in the anodization ring (under the photoresist mask)

(11) FIG. 10 shows the removal of the photoresist defining the anodization ring.

(12) FIG. 11 shows the deposition of an SiO.sub.2 insulating layer, designed to isolate the junction from subsequent wiring layers.

(13) FIG. 12 shows the coating and patterning of a third photoresist layer, designed to produce a contact via to the Nb junction from a Nb wiring layer.

(14) FIG. 13 shows the selective etching of the SiO.sub.2 up to the Nb counter-electrode.

(15) FIG. 14 shows the removal of the photoresist. Now the structure is ready for deposition of a Nb wiring layer

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

(16) A new fabrication method is proposed for increasing the yield and quality of superconducting junctions and more particularly Josephson junctions and Josephson-based digital and analog circuits in superconducting electronics. The method is based on using a double-layer mask for partial anodization of the junction side-walls and base-electrode around the junction. The top layer of this mask is a photoresist or electron-beam resist, and the bottom layer is a dielectric (e.g., SiO.sub.2) that is insoluble in either aqueous or organic solvents. A more detailed description will now be given.

(17) The existing fabrication scheme for making Nb-based Josephson tunnel junctions for superconducting electronics is comprised of the following fabrication steps:

(18) 1. As shown in FIG. 1, a Nb/Al/AlO.sub.x/Nb trilayer is deposited in-situ on a wafer that includes or will include several other patterned layers of metal and dielectric. A tunnel barrier is formed by in-situ thermal oxidation of the Al layer in oxygen or an oxygen/argon mixture at a defined pressure, to form a thin (1-2 nm) layer of AlO.sub.x. Both the oxidation time and the pressure determine the properties of the tunnel barrier such as the Josephson critical current density J.sub.c. The bottom Nb layer is called the base electrode, and the top Nb layer is called the counter-electrode of the tunnel Josephson junctions.

(19) 2. FIG. 2 shows a step that differs from prior art fabrication techniques and will be discussed in more detail hereinafter.

(20) 3. The wafer is coated with either positive or negative resist (FIG. 3), and the resist etch mask is formed by optical or e-beam lithography (FIG. 4). The counter-electrode area is then defined by etching (FIG. 5), using e.g. plasma etching, reactive-ion etching, or high-density plasma etching. The AlO.sub.x/Al layer acts as an etch stop. (Notethe prior art method does not include the thin SiO.sub.2 layer shown in FIGS. 3, 4 and 5.)

(21) 4. After etching and without removing the resist, the wafer is immersed in an anodization solution, and all the surfaces that are not protected by the resist mask formed in step 5 are anodized. That is, the same resist etch mask is also used as an anodization mask. Anodization creates a bilayer of anodized Al (AlO.sub.x) and anodized Nb (NbO.sub.x) on the surface of the base electrode (FIG. 6). A layer of anodized Nb is also formed on all sidewalls of the junction's counter-electrode. This anodization step is very important because it encapsulates the junction's tunnel barrier with an anodized NbO.sub.x layer, and this, protects it from reacting with water, oxygen, and other processing chemicals during all further wafer processing steps. This step also allows for opening a contact hole to the counter-electrode that is larger in size than the junction itself. The thickness of the anodized layer is controlled by the anodization voltage, usually in the range of 15-50 V. The initial anodization current density is in the range from 0.5-5 mA/cm.sup.2.

(22) 5. After anodization, the resist is stripped (FIG. 7), and the wafer proceeds to the next fabrication steps that are intended to pattern the base electrode of the junction by lithography and etching. This may also require removing the anodization layer in some parts of the circuit. It remains around the junction (the anodization ring of FIGS. 8-10).

(23) 6. After base electrode patterning, the Josephson junction is completely formed. All other fabrication steps are necessary in order to interconnect junctions in the circuits (such as the SiO.sub.2 insulating layer in FIGS. 11-14), and to create resistors for biasing and shunting the junctions. These steps may vary depending on the details the fabrication process.

(24) One of the main sources of defects and loss of yield in this fabrication scheme is poor adhesion of the resist mask in step 3. Although this fact has not been recognized in the prior art. This may be due in part to the volume expansion of Nb and Al layers during anodization, which places significant local stresses on the photoresist mask. As a result, some parts of the resist mask may peel off during anodization, or anodization solutions may leach under the resist mask. This is especially a problem with many negative resists such as UVN-30 (Shipley Company, Marlborough Mass.). Some photoresists may also be incompatible with (partially soluble in) the common anodization solutions. In these cases, some junctions may be degraded, or the counter-electrode of some junctions may be partially anodized, thus preventing a good (superconducting) electrical contact to be made to the junctions during the following fabrication steps.

(25) One improvement of the invention is to use a double-layer anodization mask with the lower layer being an inorganic dielectric layer (such as SiO.sub.2) that is insoluble in water, solvents, and components of the anodization solution, and the upper layer is the photoresist (or e-beam resist) layer. SiO.sub.2 is especially suitable since it has already been optimized as an insulating layer in the prior-art Nb integrated circuit process, and is also fully compatible with standard Si-based resist processing. This double-layer mask is formed in the following simple way:

(26) a. After the Josephson junction trilayer (Nb/Al/AlO.sub.x/Nb) is formed as in step 1 above, a pinhole-free layer of SiO.sub.2 is deposited by any appropriate method (e.g., rf magnetron sputtering, or plasma-enhanced chemical vapor depositionPECVD) on top of the trilayer (see FIG. 2). The layer thickness may be anywhere from 5 to 300 nm, and is not critical, as long as it is free from pinholes. Thicker layers require long etch times, making them impractical.

(27) b. A resist mask is formed in the same way as in step 4 above.

(28) c. Then etching is done, using reactive ion etching (RIE) or inductively coupled plasma (ICP) with fluorine-based chemistry (e.g., SF.sub.6, NF.sub.3, or CF.sub.4+O.sub.2) such that both the SiO.sub.2 overlayer and the Nb counter-electrode are etched in the same process. This may be a one-step process when the same etch parameters are used for both layers, or a two-step process when different etch recipes are used for etching first the SiO.sub.2 and then the Nb counter-electrode. After completing the etch down to the AlO.sub.x/Al layer in the trilayer structure (FIG. 5), the top of the Josephson junction will have a double-layer structure (SiO.sub.2+resist) that serves as the double-layer anodization mask.

(29) d. Etching is immediately followed by the anodization step 3, without removing the resist mask (FIG. 6). Now there is a layer of SiO.sub.2 under the resist mask for extra protection.

(30) The advantages of the proposed method are as follows. The SiO.sub.2 layer improves the adhesion of the resist, and does not allow the anodization solution to leach underneath. Since the adhesion of sputtered or PECVD-deposited SiO.sub.2 to Nb has already been optimized, and is stronger than the adhesion of the resist to Nb, the double-layer also protects the junction counter-electrode from being anodized even in the unlikely event that a part of the resist mask pops off, or if the anodization solution does leach under the resist. In the rare case that the SiO.sub.2 layer has a pinhole or other defect, the presence of the resist on top still provides protection during the anodization. The probability that both layers of the double-layer anodization mask fail in the same location is much smaller than the probability of a failure of a single-layer resist mask. As a result, a dramatic increase in the yield and junction quality is achieved.

(31) Another improvement over the prior art is described in reference to FIGS. 8 and 9, in defining the anodization ring around the Josephson junction. In the prior art, the AlO.sub.x layer was first removed by a wet etch process, followed by reactive ion etching (RIE) for removing the NbO.sub.x layer. However, a wet etch process can cause problems, that should preferably be avoided in high-reliability VLSI processing, particularly if sub-micron resolution is required. In the process of the present invention, this wet etch step is discarded, and two new approaches have been successfully demonstrated. In approach A, ion-milling with a neutral beam of argon (Ar) atoms is used to remove both the AlO.sub.x and the NbO.sub.x layers. In approach B, plasma etching (RIE or ICP) is used in a two-step process. First, a chlorine-based plasma is used to remove AlO.sub.x, and then a fluorine-based plasma is used to remove the NbO.sub.x. Either approach provides for increased yield and uniformity.

(32) While various embodiments of the present invention have been illustrated herein in detail, it should be apparent that modifications and adaptations to those embodiments may occur to those skilled in the art without departing from the scope of the present invention as set forth in the following claims.