TRANSCEIVER FOR ASYNCHRONOUS DATA TRANSMISSION OVER A NOISY CHANNEL

Abstract

A method of asynchronous transmission over a noisy channel includes the following steps: providing a data frame having at least one start bit, payload data and at least one stop bit, the data frame having a predetermined number of bits; forming a signaling preamble having a predetermined length by using at least said start and stop bit periods of the data frame; building a processed data frame by attaching the signaling preamble to the payload data, the processed data frame having the same predetermined number of bits; and modulating the processed data with a signaling modulation scheme and transmitting the modulated processed data over the noisy channel. The method can be advantageously implemented for data transmission over DC and/or AC power lines, for instance in vehicles or cars. Despite the noise on the data channel the data transmission is robust and there is no need for further error correction codes.

Claims

1-15. (canceled)

16. A method of asynchronous transmission of data over a noisy channel, the method comprising: providing a data frame having at least one start bit, payload data and at least one stop bit, the data frame having a predetermined number of bits; forming a signaling preamble having a predetermined length by using at least the start and stop bit periods of the data frame; building a processed data frame by attaching the signaling preamble to the payload data, the processed data frame having the predetermined number of bits; and modulating the processed data by using a signaling modulation scheme and transmitting the modulated processed data over the noisy channel.

17. The method according to claim 16, wherein the signaling preamble corresponds to a signaling synchronization sequence of the data frame, the synchronization sequence having a predetermined bit length of at least a number of the start and stop bits.

18. The method according to claim 16, wherein the signaling preamble is formed on a basis of the payload data within the data frame.

19. The method according to claim 16, wherein the signaling modulation scheme is a phase shift key modulation scheme.

20. The method according to claim 16, wherein the forming step comprises shifting the stop bit to a position adjacent the start bit of the data frame.

21. The method according to claim 16, which further comprises receiving the processed data at a receiver.

22. The method according to claim 21, which further comprises demodulating the signaling data frame received at the receiver by sampling the data and entering sampled data into a shift register.

23. The method according to claim 22, which further comprises comparing the sampled data with reference signaling data patterns stored in a register on a receiver side, and determining whether a valid signaling preamble was received.

24. The method according to claim 23, which further comprises, upon detecting a valid signaling preamble, building the original data frame.

25. The method according to claim 16, wherein the data frame is a data type selected from the group consisting of universal asynchronous receiver/transmitter interface data type, RS232, RS485, LIN, CAN, SPI, and MIL-Std-1553 data type.

26. A transceiver for asynchronous sending and/or receiving of data over a noisy channel, the transceiver comprising: a register for storing a data frame with a predetermined data length; a processor connected to said register and configured for processing the data frame by forming a signaling preamble sequence, said processor including a module for generating the signaling preamble sequence based on data bits of the data frame, a processed data frame having the predetermined data length; a modulator for modulating the processed data frame to form modulated signaling data; and a transmitter configured for transmitting the modulated signaling data over the noisy channel.

27. The transceiver according to claim 26, further comprising: a receiver configured to receive the modulated signaling data; a demodulator configured to demodulate the modulated signaling data received by said receiver; a comparator configured to compare the signaling preamble sequence with at least one valid signaling preamble sequence stored in a valid sequence register; and a module for reconstructing the original data frame.

28. The transceiver according to claim 26, wherein said modulator is a phase shift key modulator.

29. The transceiver according to claim 26, wherein the noisy channel is a power line.

30. The transceiver according to claim 29, wherein the noisy channel is a DC and/or AC power line connection.

31. A transceiver for asynchronous sending and/or receiving of data over a noisy channel, the transceiver comprising a central processing unit configured and programmed to execute the method according to claim 16.

Description

SHORT DESCRIPTION OF THE FIGURES

[0026] The invention is explained in further detail, by way of example and with reference to the accompanying drawings wherein:

[0027] FIG. 1 shows the UART encoding scheme;

[0028] FIG. 2 shows an operational sequence of the method (operational diagram) according to the present invention;

[0029] FIG. 3 depicts the signaling principle according to the present invention on the basis of an UART encoding scheme;

[0030] FIG. 4 schematically shows the transmission path according to the present invention;

[0031] FIG. 5 schematically shows the corresponding receiving path of the present invention; and

[0032] FIG. 6 discloses one embodiment of a transceiver according to the present invention.

DETAILED DESCRIPTION

[0033] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. In this regard, directional terminology, such as top, bottom, front, back, etc., is used with reference to the orientation of the figure(s) being described. Because components of embodiments of the present invention can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.

[0034] FIG. 1 shows a usual UART encoding scheme. The UART provides a means of sending and receiving bytes serially over a transmission channel, like for instance a wire or AC and/or DC power line at a specific data rate, namely baud rate. A data stream 10 is shown comprising a number of bytes 11, and the UART encoded data stream 16 is shown below. At the sending end each data byte 16 is enhanced with a start bit 18, stop bit 19 and may also be configured with a parity bit or checksum bit for instance which are not shown below. Each bit is transmitted serially at the pace of the baud rate clock. At the receiving site, the transition between the start bit 18 and stop bit 19 synchronizes the baud rate clock and the received data bits are sampled with the baud rate clock upon reception. The start bit 18, stop bit 19 and any parity bits (not shown) are removed by a processor and the data byte 16 may be placed in a dynamic register or buffer.

[0035] This processing of the data bytes is usually embedded in a UART port hardware in a transceiver or the like. The UART interface allows a simple transmission of payload data wherein no coding or decoding is needed. Over noisy channels like for instance AC and/or DC power lines the start bit and stop bit of the data frame may not be detected properly leading to synchronization problems on the receiver for instance. Therefore for detect data errors a message payload checksum mechanism may be provided so that a message check sum is added to each message. This checksum is then validated at the receiving end to check the message integrity. A checksum result different from the expected will cause a message to be rejected. However synchronization problems are not able to be detected by error detection and/or correction codes.

[0036] FIG. 2 shows an operational sequence of the method according to the present invention. In a first step S200 the operational sequence may start by providing a data frame including at least one start bit 18, payload data and at least one stop bit 19, said data frame 16 having a predetermined number of bits N. Such a data frame structure is shown with reference to FIG. 1, wherein one start bit and one stop bit are used. After the data frame 16, which for example may be a UART data frame but also other data format able to be used for an asynchronous data transmission are conceivable to be processed according to the method of the present invention, was provided a signaling preamble may be formed in step S210. The forming step S210 forms the signaling preamble by using the bit periods of the start and stop bit therefore keeping the whole data length N unchanged. After the signaling preamble was formed in step S210, building of a processed data frame S220 will be performed, wherein again the data length of the processed data frame will be identical with the original length of the provided data frame above in step S200. Thus the method can be used in already implemented data transmission systems where the used data lengths were already fixed.

[0037] After a processed data frame was provided modulating of said processed data follows according to a modulating step S230. The modulation scheme used may correspond to the technique disclosed in EP 1292060 B1 of the applicant, which is herewith incorporated by reference. The modulated signal is thereafter transmitted S240 over a channel, i.e. a noisy DC and/or AC power line wire for instance in an automobile to a receiver Rx which is in turn connected to the power line system for instance. The method on the transmitter site Tx of the present invention may be restarted if a next original data frame will be provided.

[0038] FIG. 2 shows on the right side the operational sequence on the receiver site according to a possible embodiment of the present invention. During a receiving step S250 a processed data stream, which was generated on the transmitter Tx site according to the present invention, may be further processed. The received data stream belongs to a serial data stream, which has to be encoded on the receiver site. Next demodulating of the received data in step S260 may be performed. Therein the modulated radio frequency signal is demodulated, whereby the base band signal is extracted.

[0039] According to the present invention a comparing step S270 is executed wherein the received signaling data frame is compared with reference signaling data patterns stored in a register at the receiver for instance. If a valid signal was detected the CPU in the receiver for instance may rebuild S280 the sent original data and the received data may further be processed. During a decisional step S290 it may be identified if valid data is present and in case of a positive identification the receiving method may stop. If false data was received the receiving method may further be executed in a recursive manner whereby a new modulated data frame may be processed until valid data was encoded.

[0040] FIG. 3 schematically shows the principle of the present invention. By the way of example a UART data frame was used comprising one start bit, one stop bit and eight bit of payload data, that is the data lengths is ten bits. According to the present invention a signaling data preamble is generated by keeping the data frame length unchanged, that is according to this embodiment ten bits. It should be understood that different data frame lengths are implementable within the scope of the present invention.

[0041] In order to be able to synchronize a single byte of data, a synchronization sequence, herein preamble sequence is required at the beginning of the byte. Said preamble distinguishes between ordinary noise that exist over the power line and the start of the byte. A longer preamble sequence ensures better detection of the unique preamble sequence within the noise occurred in the transmission channel, i.e. DC and/or AC power line. The overall length of the byte cannot be changed because the number of bytes in a message can be infinite. Therefore, the synchronization preamble length determines the byte robustness to noise and interference.

[0042] The method according to the present invention suggest to use both the start and stop bits periods of the asynchronous byte as the preamble period, followed by the modulated data bits, keeping the entire byte duration unchanged, which is schematically shown with reference to FIG. 3. On the DC line for instance, the processed data frame 33 is shown comprising a signaling preamble 35 having a length of two bits corresponding to the minimum amount of start and stop bits in the UART frame. With reference 31 the modulated preamble sequence 35 is shown wherein a PSK modulation technique with phase changes was implemented.

[0043] For the robust transmission of the data over the noisy channel a PSK modulation scheme may be implemented. At the bottom of FIG. 3 the modulated preamble is schematically shown. It should be noted that the remaining bits of the processed data frame will also be modulated prior the transmission over the noisy channel. For the sake of simplicity only the modulated preamble is shown.

[0044] Furthermore, if more than these two bits period may be required for the preamble, it is conceivable to generate two different preamble sequences. The receiver will try to detect both sequences within the noisy channel. If the first sequence is detected, the first data bit will be considered as 1. If the second sequence is detected, the first data bit will be considered as 0. Furthermore, if longer preamble period may be needed, four different preamble sequences can be used for the first two bits of data and so on. Thus the method according to the present invention can be adapted on the basis of the channel transmission quality. That is, the better the channel transmission is the fewer bits for the signaling preamble are needed.

[0045] According to a further embodiment the entire byte period of the UART data frame may be divided into two sub periods, where the first sub period is used as preamble and the second sub period is used to transfer the entire data bits. The determination of the necessary length of these sub periods is a balance that depends on the demodulation receiver performance in the expected noisy channel and the required bit rate.

[0046] The method is applicable to many existing data types such as RS232, RS485, LIN, CAN, SPI, MIL-Std-1553 or the like.

[0047] With reference to FIG. 4 the transmitter according to the present invention is schematically shown. The transmitting side receives the UART data byte. Upon detection of the start bit 18, the digital processing unit or CPU 630 starts to transmit the preamble sequence 35. During this period, the data bits are entered into the digital processing unit 630 and signaling patterns for the payload data are generated according to the entered bits (0 or 1). The signaling patterns are converted into an analog signal form by means of a digital to analog converter. The converted data will be in turn transmitted over the DC power line 604 according to one embodiment. It should be noted the communication channel 604 may also be a AC power line connection or the like.

[0048] FIG. 5 shows schematically a receiver according to the present invention that detects sequence of two possible expected sequences (0 or 1). Same solution can be used for only one preamble sequence or more sequences. Furthermore, similar circuit can be used to detect also the data pattern bits. The received modulated signal 51, pass through band pass filter 510 and is sampled at high speed by an analog to digital converter 50. The sampled data enter into a shift register 620 where each sampled data is compared with an expected sequence (one or more) that is stored in a memory 62a. If the result of the entire compared shift register values are gathered by the digital processing unit 630. If the calculated values are close enough to the value of the expected sequence, (one or more) the digital processing unit 630 start to detect the rest of the expected data bytes and output the decoded data in the original UART byte format as entered on the transmitting side.

[0049] FIG. 6 shows a possible embodiment of the transceiver 600 according to the present invention. Referring to FIG. 6, a transmitter 601 for transmitting data over a power supply line 604 and a receiver 606 for receiving data transmitted over the power supply line 604 according to embodiments of the present invention are illustrated. According to one exemplary embodiment the transmitter 601 and the receiver 606 are implemented as one device or apparatus as a transceiver 600, but also two functional blocks or separated apparatuses for transmitting and receiving are conceivable.

[0050] The transmitter 601 and the receiver 606 are functionally connected, e.g. the transmitter and receiver are apparatuses that complement each other and may work together. For example, the transmitter and receiver may be combined into a modem for data communication.

[0051] The transmitter 601 comprises a signal interface or port 602 for receiving a serial bit stream. For example, the serial bit stream may correspond to the processed data frame as explained with reference to FIG. 2, wherein the method according to an embodiment of the present invention is disclosed. The transceiver operating on the basis of the inventive method may provide a robust hardware and software solution for data exchange between different components in vehicles for instance.

[0052] The transmitter 601 also comprises a power line interface or port 603 for sending a signal over a power supply line 604, especially a DC power line or wire. The signal interface 602 may be implemented to receive a serial bit stream in form of a processed data frame according to the present invention. The power line connection interface 603 may be adapted for transmitting a signal over a power supply line 604 of the vehicle.

[0053] The transmitter 601 further comprises a modulator 605 for generating the modulated signal on the basis of the processed data. The modulator 605 is adapted to encode the processed serial bit stream, e.g. the serial bit stream received via the local signal port 602 and processed according to the method of the present invention described with reference to FIG. 2, into an original signal. The modulation technique may be a phase shift key modulation as disclosed in EP 1292060 B1 of the applicant.

[0054] The modulator 605 may implement different modulation techniques such as: amplitude modulation (AM), frequency modulation (FM) or phase modulation (PM) or the like. However, the modulator 605 may also implement digital modulation techniques, such as amplitude shift keying (ASK), frequency shift keying (FSK), minimum shift keying (MSK), or more complex techniques like quadrature phase shift keying (QPSK), or quadrature amplitude modulation (QAM) or the like.

[0055] According to an embodiment the modulator 605 is implemented to function according to the modulation technique as disclosed in EP 1292060 B1 of the applicant leading to a robust transmission of short data over noisy channels, especially over the DC power line 604 according to one embodiment.

[0056] The receiver 606 within the transceiver 600 may comprise two interfaces 608 and 607 which are interconnected in an analogous manner with reference to the transmitter 601 as shown in FIG. 6.

[0057] Further the transceiver 600 comprises a central processing unit 630 or a CPU which is adapted to control the operation of the included modules. The CPU 630 is connected with a register device 620 which may be implemented as a static or dynamic register for instance, but other storage techniques are conceivable. Within the register 620 a valid data register 620a (not shown) may be implemented containing for instance a list of valid signaling preambles which are used for encoding of valid data which was received via the communication channel 604.

[0058] The transceiver 600 according to the present invention comprises a module for generating 640 a signaling preamble sequence on the basis of data bits of said data frame, wherein the processed data frame comprises an unchanged number of bits N. The generating module 640 may be implemented as software code running on the CPU 630 but other implementation techniques are conceivable.

[0059] For receiving and encoding the data a comparator module or unit 660 may be implemented which compares the received signaling preamble with predetermined valid signaling preambles within a register 620a (not shown) within the transceiver 600. If the comparison step identifies a match valid data was received which can be processed further.

[0060] The modem device 650 with reference to FIG. 6 may be implemented to modulate and/or demodulate date which has to be sent and received over the power line 604. The functionality of the modem 650 is not explained in detail herein and should be clear for a person skilled in the art of data communication.

[0061] For the sake of simplicity not all connections within the transceiver 600 are depicted, but it should be clear that all units might be interconnected by means of the CPU 630 for instance. According to a further embodiment the transceiver may be implemented on a FPGA for instance wherein suitable firmware code is embodied to operate according to the method of the present invention.

[0062] It is to be noticed that the term comprising, used in the claims, should not be interpreted as being restricted to the means listed thereafter; it does not exclude other elements or steps. It is thus to be interpreted as specifying the presence of the stated features, integers, steps or components as referred to, but does not preclude the presence or addition of one or more other features.

[0063] Thus, the scope of the expression a device comprising means A and B should not be limited to devices or modules consisting only of components A and B. It means that with respect to the present invention, the only relevant components of the device are A and B.

[0064] Reference throughout this specification to one embodiment or an embodiment means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, appearances of the phrases in one embodiment or in an embodiment in various places throughout this specification are not necessarily all referring to the same embodiment, but may. Furthermore, the particular features, structures or characteristics may be combined in any suitable manner, as would be apparent to one of ordinary skill in the art from this disclosure, in one or more embodiments.

[0065] Similarly it should be appreciated that in the description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various inventive aspects. This method of disclosure, however, is not to be interpreted as reflecting an intention that the claimed invention requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this invention.

[0066] Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific embodiments illustrated and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that this invention be limited only by the claims and the equivalents thereof.