P-Type chalcogenide and n-type silicon heterojunction infared photodiodes and method of manufacturing thereof

Abstract

A photodetector comprising a region of a p-type phase-change chalcogenide material forming a heterojunction with a region of n-type Silicon; wherein the p-type phase-change chalcogenide material comprises one of GeTe and SbTe.

Claims

1. A method of manufacturing a photodetector, the method comprising: providing a region of n-type Silicon having top and bottom surfaces; forming one of a layer of crystalline p-type phase-change chalcogenide material and a layer of polycrystalline p-type phase-change chalcogenide material on the top surface of the region of n-type Silicon; wherein the p-type phase-change chalcogenide material comprises one of GeTe and SbTe.

2. The method of claim 1, wherein said forming one of a layer of crystalline p-type phase-change chalcogenide material and a layer of polycrystalline p-type phase-change chalcogenide material on the top surface of the region of n-type Silicon comprises: sputtering at room temperature a layer of an amorphous p-type phase-change chalcogenide material on the top surface of the region of n-type Silicon; and increasing the temperature until structural phase transition transforms the layer of amorphous p-type phase-change chalcogenide material into one of a layer of crystalline p-type phase-change chalcogenide material and a layer of polycrystalline p-type phase-change chalcogenide material.

3. The method of claim 1, wherein said providing a region of n-type Silicon having top and bottom surfaces comprises: providing a first substrate having a work surface; and forming said region of n-type Silicon on said work surface of the first substrate, wherein the top surface of said region of n-type Silicon is in contact with the work surface of the substrate and the bottom surface of said region of n-type Silicon is exposed; forming an integrated circuit in the bottom surface of said region of n-type Silicon; said integrated circuit being electrically coupled to a first electrode of said photodetector; forming a dielectric layer on the bottom surface of said region of n-type Silicon; attaching a second substrate to the dielectric layer; and removing the first substrate to expose the top surface of said region of n-type Silicon.

4. The method of claim 3, wherein said dielectric layer comprises at least one conductor electrically connected to said integrated circuit.

5. The method of claim 3, further comprising forming an insulated via between said integrated circuit and a top surface of the p-type phase-change chalcogenide material; and forming on the top surface of the p-type phase-change chalcogenide material a second electrode of said photodetector in contact with the via.

6. The method of claim 1, further comprising covering the layer of p-type phase-change chalcogenide material with an anti-reflection material.

7. The method of claim 6, wherein the anti-reflection coating comprises Ge or ZnSe.

8. A method of manufacturing a photodetector, the method comprising: providing a region of n-type Silicon having top and bottom surfaces; forming one of a layer of crystalline p-type phase-change chalcogenide material and a layer of polycrystalline p-type phase-change chalcogenide material on the top surface and in direct contact with of the region of n-type Silicon.

9. The method of claim 8, wherein said forming one of a layer of crystalline p-type phase-change chalcogenide material and a layer of polycrystalline p-type phase-change chalcogenide material on the top surface of the region of n-type Silicon comprises: sputtering at room temperature a layer of an amorphous p-type phase-change chalcogenide material on the top surface of the region of n-type Silicon; and increasing the temperature until structural phase transition transforms the layer of amorphous p-type phase-change chalcogenide material into one of a layer of crystalline p-type phase-change chalcogenide material and a layer of polycrystalline p-type phase-change chalcogenide material.

10. The method of claim 8, wherein the p-type phase-change chalcogenide material comprises one of GeTe and SbTe.

11. The method of claim 8, wherein said providing a region of n-type Silicon having top and bottom surfaces comprises: providing a first substrate having a work surface; and forming said region of n-type Silicon on said work surface of the first substrate, wherein the top surface of said region of n-type Silicon is in contact with the work surface of the substrate and the bottom surface of said region of n-type Silicon is exposed; forming an integrated circuit in the bottom surface of said region of n-type Silicon; said integrated circuit being electrically coupled to a first electrode of said photodetector; forming a dielectric layer on the bottom surface of said region of n-type Silicon; attaching a second substrate to the dielectric layer; and removing the first substrate to expose the top surface of said region of n-type Silicon.

12. The method of claim 10, wherein said dielectric layer comprises at least one conductor electrically connected to said integrated circuit.

13. The method of claim 10, further comprising forming an insulated via between said integrated circuit and a top surface of the p-type phase-change chalcogenide material; and forming on the top surface of the p-type phase-change chalcogenide material a second electrode of said photodetector in contact with the via.

14. The method of claim 8, further comprising covering the layer of p-type phase-change chalcogenide material with an anti-reflection material.

15. The method of claim 13, wherein the anti-reflection coating comprises Ge or ZnSe.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) For a more complete understanding of this presentation and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which like reference numerals represent like parts:

(2) FIG. 1 illustrates a known Bismuth-Tellurium on Silicon photodiode.

(3) FIG. 2 illustrates a photodetector according to an embodiment of this presentation.

(4) FIG. 3 illustrates the I/V characteristic of a photodetector according to an embodiment of this presentation.

(5) FIG. 4 illustrates the electrical resistance/temperature characteristic of a region of a p-type phase-change chalcogenide material according to an embodiment of this presentation.

(6) FIG. 5 illustrates X-ray diffraction data showing the change in crystallinity of a region of a p-type phase-change chalcogenide material according to an embodiment of this presentation with phase-transition.

(7) FIG. 6 illustrates the sheet resistance of a wafer of a p-type phase-change chalcogenide material according to an embodiment of this presentation.

(8) FIG. 7 illustrates schematically a photodetector according to an embodiment of this presentation.

(9) FIGS. 8A to 8F illustrates a method of manufacturing of the photodetector of FIG. 7.

DETAILED DESCRIPTION

(10) It should be understood at the outset that, although example embodiments are illustrated below, the present technology may be implemented using any number of techniques, whether currently known or not. The present technology should in no way be limited to the example implementations, drawings, and techniques illustrated below. Additionally, the drawings are not necessarily drawn to scale.

(11) A chalcogenide is a compound containing selenium (Se), Tellurium (Te), or Sulfur (S), which has been used in various photonic applications including photovoltaic solar cells. Currently, thin film solar cells made of Copper-Indium-Gallium-Selenium (Cu(In,Ga)Se2), or Cadmium-Tellurium-Cadmium Sulphide (CdTe/CdS) compounds are made. The principal of phase change materials (PCMs) was known in the 1960s, particularly for their application in rewritable optical DVDs having been developed using Germanium-Antimony-Tellurium (Ge.sub.2Sb.sub.2Te.sub.5) or Silver-Indium-Antimony-Tellurium ((Ag, In)Sb.sub.2Te). Lately, PCMs have been developed for non-volatile memory as a future replacement for flash memory in the Integrated Circuit (IC) industry by companies such as Micron, Samsung, IBM, STMicroelectronics, and Intel.

(12) FIG. 2 illustrates a cross-section of a photodetector 10 according to an embodiment of this presentation, comprising a region 12 of a p-type phase-change chalcogenide material, arranged in contact with a region 14 of n-type Silicon so as to form a heterojunction 16 with region 14. According to an embodiment, the n-type Silicon has electrons as a major carrier and can be formed with extrinsic doping with Group V elements such as phosphorus, arsenic, and antimony (for example with a density of 10.sup.19 per cm.sup.3). The p-type phase-change chalcogenide material has holes as a major carrier and the p-type is intrinsically formed by Ge-site vacancies in general. According to an embodiment of this presentation, the p-type phase-change chalcogenide material of region 12 comprises one of GeTe (for example Ge0.5Te0.5) and SbTe (for example Sb2Te3). According to an embodiment of this presentation, the p-type phase-change chalcogenide material of region 12 is crystalline or polycrystalline. According to an embodiment of this presentation, photodetector 10 operates in the near-IR and short-wave IR spectral ranges. According to an embodiment of this presentation, the region 12 has a thickness comprised between 0.2 m and 1 m; for example a thickness of 0.6 or 1 micrometer. According to an embodiment of this presentation, the material of region 14 can comprise Si. According to an embodiment of this presentation, region 12 comprises a bottom surface that is in contact with a top surface of the region 14; a portion of a bottom surface of the region 14 is in contact with a first electrode 18; and a portion of a top surface of region 12 is in contact with a second electrode 20. According to an embodiment of this presentation, region 12 comprises lateral sides that are surrounded by a dielectric material region 22; for example SiO2. According to an embodiment of this presentation, second electrode 20 is in contact with a portion of a top surface of said dielectric material region 22. Electrode 20 can be made of an optically transparent conductive material, including graphene or a network of silver nanowires.

(13) According to an embodiment of this presentation, dielectric material region 22 can comprise SiO2 or silicon nitride (SiNx) and can be formed as a blanket dielectric layer over a Silicon substrate comprising region 14. The blanket dielectric layer can then be etched away from a predetermined region above region 14, thus forming a recess surrounded by dielectric layer 22, before forming region 12 in said recess and forming electrode 20 above at least a portion of region 12. According to an embodiment of this presentation, at least the portion of the top surface of region 12 that is not in contact with the second electrode 20 is covered by an anti-reflection coating 24. According to an embodiment of this presentation, anti-reflection coating 24 can comprise Ge or ZnSe coating as an example.

(14) According to an embodiment of this presentation, region 12 can be formed directly on top of region 14 by: sputtering at room temperature a layer of an amorphous p-type phase-change chalcogenide material e.g. (GeTe, such as Ge0.5Te0.5; or Sb2Te3) on the top surface of region 14; then increasing the temperature until structural phase transition transforms the layer of amorphous p-type phase-change chalcogenide material into region 14, which comprises either a layer of crystalline p-type phase-change chalcogenide material or a layer of polycrystalline p-type phase-change chalcogenide material. According to an embodiment of this presentation, the phase transition temperature of the p-type phase-change chalcogenide material is low enough that increasing the temperature until structural phase transition takes place and forms region 14 does for example not damage an integrated circuit such as a CMOS circuit previously formed on a surface of region 14. The circuit can for example be a Readout Integrated Circuit (ROIC). Thus, and as detailed hereafter, a photodetector according to an embodiment of this presentation can be integrated directly to a CMOS circuit without requiring any hybridization process (as required for known crystalline semiconductors IR photodetectors). Thus, an embodiment of this presentation provides for fabricating chalcogenide photodiodes directly on CMOS wafers without requiring a hybridization process, which allows reducing the cost of imagers, and allows obtaining larger wafer-size scaling.

(15) FIG. 3 illustrates measured current-voltage characteristics of a 7373 square micrometer p-GeTe/n-Si heterojunction photodetectors (using a GeTe thickness of 2000A) at room temperature after the GeTe was phase-transitioned to a poly-crystalline state by annealing at 200 C. It can be seen from FIG. 3 that the photocurrent of the photodiode/photodetector increases as the IR illumination intensity increases from 13 nW to 33 nW. It is noted that GeTe has a large band gap of 0.8 eV (amorphous) and 0.7 eV (crystalline) at room temperature

(16) FIG. 4 maps measured resistance versus temperature characteristics for a GeTe layer formed on a Si wafer/region according to an embodiment of this presentation (various colors represent different doping concentrations). As illustrated the phase transition, from an amorphous state to a polycrystalline state, occurs when the chalcogenide is annealed at around 200 C. (in a range comprised between 190 and 230 degree Celsius). As illustrated in FIG. 4, a crystallized region of p-type phase-change chalcogenide material, according to embodiments of this presentation, is formed by annealing an amorphous region of the material at the phase transition temperature. FIG. 4 shows a resistance greater than 10.sup.5 Ohms per square units (such as sq meter or sq cm) for amorphous material and 10 ohms per square for poly-crystalline material. Further, a crystallized region of p-type phase-change chalcogenide material according to embodiments of this presentation had an excellent DC conductivity of around 3000 Siemens/cm. Further a crystallized region of p-type phase-change chalcogenide material according to embodiments of this presentation shows, for some doping concentrations, a p-type carrier mobility as high as 1400 cm.sup.2/Volt-second.

(17) FIG. 5 illustrates a measured intensity of X-Ray Diffraction as a function of an incidence angle of the X-ray on a phase-change chalcogenide material region GeTe according to an embodiment of this presentation.

(18) FIG. 6 illustrates measured resistivity contours on an Antimony-Tellurium (Sb.sub.2Te.sub.3) region formed according to an embodiment of this presentation on a 3-inch Silicon wafer by raising the temperature of a room-temperature-sputtered amorphous layer to a phase transition temperature of about 160 degree C. As illustrated in FIG. 6, the sheet resistance of the illustrated Antimony-Tellurium (Sb.sub.2Te.sub.3) region is around 161 /square meter, and it has a carrier mobility of about 272 cm.sup.2/V-Sec. As illustrated in FIG. 6, a p-doped Antimony-Tellurium (Sb.sub.2Te.sub.3) is also a suitable chalcogenide on the n-doped Silicon region forming a heterojunction suitable for a photodiode.

(19) FIG. 7 illustrates an embodiment of a phase-change chalcogenide photodiode device/photodetector 10, which comprises all the elements described in relation with the photodiode 10 in FIG. 2. Further, photodetector 10 comprises an integrated circuit 30 formed at least in part in a portion of the bottom surface of the region 14 of n-type Silicon, circuit 30 being connected to first electrode 18. According to an embodiment of this presentation, integrated circuit 30 can be a CMOS circuit, for example a ROIC circuit. A CMOS inverter comprising a PMOS transistor and a NMOS transistor, respectfully in an n-well and a p-well formed each in the bottom surface of region 14, is illustrated in FIG. 7. As illustrated in FIG. 7, the bottom surface of region 14 can be covered by a dielectric layer 32 and said dielectric layer can comprise conductor strips 34 forming electrical connections of integrated circuit 30. The conductor strips 34 can be connected together using vias 36 formed in dielectric layer 32. Circuit 30 can be connected to pads 38 formed on a bottom surface (illustrated) or a lateral surface (not shown) of dielectric layer 32.

(20) According to an embodiment of this presentation, electrode 20 can be electrically connected to integrated circuity by a via 40. Via 40 can be formed through dielectric region 22 so as to be isolated from region 12, and can be formed through a dielectric region 42 traversing region 14 so as to be isolated from region 14. According to an embodiment of this presentation, integrated circuit 30 can comprise a capacitor 44 formed of two conductor strips 34 separated by a thin dielectric layer. According to an embodiment of this presentation (illustrated hereafter) a bottom surface of dielectric layer 32 can be attached to a carrier wafer. FIG. 7 also illustrates schematically the naked electrical photodiode formed by the heterojunction between regions 12 and 14. It is noted that the term region as used here can be equated to the term layer where appropriate.

(21) FIGS. 8A to 8B illustrate a method, according to an embodiment of this presentation, of manufacturing a photodetector such as illustrated in FIG. 7.

(22) As illustrated in FIG. 8A, the method comprises providing a first substrate 50 having a work surface 52; and forming on work surface 52 the region 14 of n-type Silicon. The work surface 52 of substrate 50 can comprise an insulator region 54 and region 14 can be a layer of Silicon-on-insulator. It is noted that, at this stage of manufacturing, the final top surface of region 14 is in contact with the work surface of the substrate and the final bottom surface of region 14 is exposed. According to an embodiment of this presentation, the method then comprises forming integrated circuit 30 in the exposed surface of region 14; said integrated circuit being electrically coupled to a first electrode of said photodetector. It is noted that circuit 30 can be formed using known CMOS manufacturing processes. As outlined above, a layer 32 of dielectric can be formed above the exposed layer of region 14 and can comprise conductive strips 34 and/or vias 36 connected to or forming part of integrated circuit 30.

(23) As illustrated in FIG. 8B, the method then comprises attaching a attaching a second substrate 60 to the top of region 14 (or on top of dielectric layer 32 when dielectric layer 32 is formed, as illustrated). According to an embodiment of this presentation, substrate 60 can be attached permanently (to manufacture a more rigid final product) or removably (to manufacture a less rigid final product).

(24) As illustrated in FIGS. 8C and 8D, the method then comprises removing the first substrate 50, for example by etching and polishing. Removing substrate 50 exposes a surface of region 14 that is the final top surface of region 14. In the illustrated embodiment, where substrate 50 comprised an insulator 54, the carrier part of substrate 50 is first removed in FIG. 8C and then the insulator 54 is removed in FIG. 8D. As also illustrated in FIG. 8C, a plurality of regions 14 can be formed out of a single original region 14, for example by forming dielectric separator wells 42. Separator wells 42 can be formed at this stage or they can be formed earlier at the time of manufacturing integrated circuit 30.

(25) As illustrated in FIG. 8E, the method then comprises forming a layer 62 of an amorphous p-type phase-change chalcogenide material on the top surface of region 14. According to an embodiment of this presentation, layer 62 is formed at room temperature, for example by sputtering. The method further comprises annealing at 200 degrees C. until a structural phase transition of layer 62 transforms the layer 62 of amorphous p-type phase-change chalcogenide material into one of a layer of crystalline p-type phase-change chalcogenide material and a layer of polycrystalline p-type phase-change chalcogenide material. According to an embodiment of this presentation, the material of region 12 is chosen such that its structural phase transition temperature does not damage the rest of the circuit, in particular integrated circuit 30. As illustrated in FIG. 8E, layer 62 can then be etched to form regions 12 above corresponding regions 14, for example opening a space above the dielectric separator wells 42.

(26) As illustrated in FIG. 8F, dielectric regions 22 can then be formed in the space above the dielectric separator wells 42 and a via 40 can be formed through dielectric regions 22 and dielectric separator wells 42 to contact a conductor 34 of integrated circuit 30. According to an embodiment of this presentation, electrodes 20 can be formed, for example to contact via 40 to the top surface of region 14 of p-type phase-change chalcogenide material. According to an embodiment of this presentation, an anti-reflection material, for example Ge or ZnSe, can then be formed on the top surface of the photodetector. Substrate 60 can then be kept (as illustrated) to make photodetector 10 more rigid, or can be removed (as shown in FIG. 7) to make photodetector 10 less rigid.

(27) As detailed above, alternatively to what is shown in FIG. 8D, a dielectric layer can be formed on the top surface of region 14 before region 12 is formed. The dielectric layer is then etched to form the dielectric regions 22 around a recess, and region 12 is formed in the recess.

(28) As demonstrated with the measured performance data in the figures presented above, the various embodiments presented herein offer low-cost high performance IR photodetectors suitable for many applications for use as sensors and cameras operating in NIR or SWIR spectral range. Although GeTe and SbTe are demonstrated as preferred chalcogenides, other chalcogenides can be used as well in a similar fashion.

(29) As detailed above, the disclosed phase-change chalcogenide/n-Si heterojunction photodiodes can be integrated with conventional silicon CMOS or SOI process, potentially enabling low-cost NIR and SWIR detectors.

(30) In particular configurations, it may be desirable to have p-GeTe on n-Si as the preferred hetero-junction. In other applications, p-SbTe on n-Si may be the preferred heterojunction for the photodiode.

(31) Modifications, additions, or omissions may be made to the systems, apparatuses, and methods described herein without departing from the scope of the inventive concepts. The components of the systems and apparatuses may be integrated or separated. Moreover, the operations of the systems and apparatuses may be performed by more, fewer, or other components. The methods may include more, fewer, or other steps. Additionally, steps may be performed in any suitable order. As used in this document, each refers to each member of a set or each member of a subset of a set.

(32) To aid the Patent Office, and any readers of any patent issued on this application in interpreting the claims appended hereto, applicants wish to note that they do not intend any of the appended claims or claim elements to invoke paragraph 6 of 35 U.S.C. Section 112 as it exists on the date of filing hereof unless the words means for or step for are explicitly used in the particular claim.