SEMICONDUCTOR TRANSISTOR STRUCTURE WITH REDUCED CONTACT RESISTANCE AND FABRICATION METHOD THEREOF

Abstract

A semiconductor transistor structure with reduced contact resistance includes a substrate, a channel layer on the substrate, a barrier layer on the channel layer, a two-dimensional electron gas (2DEG) layer at an interface between the barrier layer and the channel layer, and a recess in a contact region. The recess penetrates through the barrier layer and extends into the channel layer. An Ohmic contact metal is disposed in the recess. The Ohmic contact metal is in direct contact with a vertical side surface of the barrier layer in the recess and in direct contact with an inclined side surface of the 2DEG layer and the channel layer in the recess.

Claims

1. A semiconductor transistor structure with reduced contact resistance, comprising: a substrate; a channel layer on the substrate; a barrier layer on the channel layer; a two-dimensional electron gas (2DEG) layer at an interface between the barrier layer and the channel layer; a recess in a contact region, wherein the recess penetrates through the barrier layer and extends into the channel layer; and an Ohmic contact metal disposed in the recess, wherein the Ohmic contact metal is in direct contact with a vertical side surface of the barrier layer in the recess and in direct contact with an inclined side surface of the 2DEG layer and the channel layer in the recess.

2. The semiconductor transistor structure with reduced contact resistance according to claim 1, wherein the inclined side surface is inclined at an angle ranging between 60-80 degrees with a horizontal plane.

3. The semiconductor transistor structure with reduced contact resistance according to claim 1, wherein the channel layer comprises a GaN layer.

4. The semiconductor transistor structure with reduced contact resistance according to claim 1, wherein the barrier layer comprises an AlGaN layer.

5. The semiconductor transistor structure with reduced contact resistance according to claim 4, wherein the barrier layer further comprises an AlN layer.

6. The semiconductor transistor structure with reduced contact resistance according to claim 1 further comprising: a passivation layer on the barrier layer.

7. The semiconductor transistor structure with reduced contact resistance according to claim 1, wherein a depth of the recess is about 10 nm below a bottom surface of the barrier layer.

8. The semiconductor transistor structure with reduced contact resistance according to claim 1, wherein the Ohmic contact metal comprises Ti and Al.

9. A semiconductor transistor structure with reduced contact resistance, comprising: a substrate; a channel layer on the substrate; a barrier layer on the channel layer; a two-dimensional electron gas (2DEG) layer at an interface between the barrier layer and the channel layer; a recess in a contact region, wherein the recess penetrates through the barrier layer and extends into the channel layer; and an Ohmic contact metal disposed in the recess, wherein the Ohmic contact metal is in direct contact with a vertical side surface of the barrier layer and the 2DEG layer in the recess and in direct contact with an inclined side surface of the channel layer in the recess.

10. The semiconductor transistor structure with reduced contact resistance according to claim 9, wherein the inclined side surface is inclined at an angle ranging between 60-80 degrees with a horizontal plane.

11. The semiconductor transistor structure with reduced contact resistance according to claim 9, wherein the channel layer comprises a GaN layer.

12. The semiconductor transistor structure with reduced contact resistance according to claim 9, wherein the barrier layer comprises an AlGaN layer.

13. The semiconductor transistor structure with reduced contact resistance according to claim 12, wherein the barrier layer further comprises an AlN layer.

14. The semiconductor transistor structure with reduced contact resistance according to claim 9 further comprising: a passivation layer on the barrier layer.

15. The semiconductor transistor structure with reduced contact resistance according to claim 9, wherein a depth of the recess is about 10 nm below a bottom surface of the barrier layer.

16. The semiconductor transistor structure with reduced contact resistance according to claim 9, wherein the Ohmic contact metal comprises Ti and Al.

17. A method of forming a semiconductor transistor structure with reduced contact resistance, comprising: providing a substrate; forming a channel layer on the substrate; forming a barrier layer on the channel layer, thereby forming a two-dimensional electron gas (2DEG) layer at an interface between the barrier layer and the channel layer; forming a recess in a contact region, wherein the recess penetrates through the barrier layer and extends into the channel layer, wherein the recess has a vertical sidewall profile in the barrier layer and an angled sidewall profile in the channel layer; and forming an Ohmic contact metal in the recess, wherein the Ohmic contact metal is in direct contact with the barrier layer, the 2DEG layer and the channel layer in the recess.

18. The method according to claim 17, wherein the angled sidewall profile in the channel layer comprises an inclined side surface that is inclined at an angle ranging between 60-80 degrees with a horizontal plane.

19. The method according to claim 17, wherein the angled sidewall profile is also formed in the 2DEG layer.

20. The method according to claim 17, wherein the vertical sidewall profile is also formed in the 2DEG layer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0027] FIG. 1 to FIG. 4 are schematic diagrams of a method for forming a semiconductor transistor structure with reduced contact resistance according to an embodiment of the present invention.

[0028] FIG. 5 shows a semiconductor structure according to another embodiment of the invention.

[0029] FIG. 6 illustrates that angled sidewall profile is also formed in the two-dimensional electron gas layer.

[0030] FIG. 7 illustrates that the vertical sidewall profile is also formed in the two-dimensional electron gas layer.

DETAILED DESCRIPTION

[0031] In the following detailed description of the disclosure, reference is made to the accompanying drawings, which form a part hereof, and in which is shown, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention.

[0032] Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention. Therefore, the following detailed description is not to be considered as limiting, but the embodiments included herein are defined by the scope of the accompanying claims.

[0033] Please refer to FIG. 1 to FIG. 4, which are schematic diagrams of a method for forming a semiconductor transistor structure 1 with a reduced contact resistance according to an embodiment of the present invention. First, as shown in FIG. 1, a substrate 100 is provided, for example, a sapphire, silicon carbide (SiC), gallium nitride (GaN) or silicon (Si) substrate, but it is not limited thereto. A channel layer 110 is then formed on the substrate 100 in an epitaxial manner. For example, the channel layer 110 may include a gallium nitride (GaN) layer, but is not limited thereto. A barrier layer 120, such as an aluminum gallium nitride (AlGaN) layer, is then formed on the channel layer 110 in an epitaxial manner, thereby forming two dimensional electron gas layer 2DEG at an interface between the barrier layer 120 and the channel layer 110. A passivation layer 130 may be formed on the barrier layer 120. The passivation layer 130 may comprise silicon nitride or silicon oxide, but it is not limited thereto. The substrate 100 comprises a contact region 200 for forming a contact electrode.

[0034] The present invention is not limited to the above-mentioned stacked structure. For example, according to other embodiments of the present invention, as shown in FIG. 5, the barrier layer 120 may further include an aluminum nitride (AlN) layer 122 directly on the channel layer 110.

[0035] As shown in FIG. 2, a photoresist pattern PR is formed on the passivation layer 130 by using a lithography process. The photoresist pattern PR has an opening POP that exposes the contact region 200. An anisotropic dry etching process is then performed to etch the passivation layer 130 and the barrier layer 120 through the opening POP, thereby forming a first opening OP1 in the passivation layer 130 and the barrier layer 120 within the contact region 200. The first opening OP1 penetrates through the barrier layer 120, but the above etching process is controlled to stop at the surface of the channel layer 110. At this point, the first opening OP1 exposes the vertical side surface 120s of the barrier layer 120.

[0036] As shown in FIG. 3, another etching process is then performed to etch the channel layer 110 downwardly through the first opening OP1 to a predetermined depth h below the bottom surface 120b of the barrier layer 120. For example, the predetermined depth h may be about 10 nm, but not limited thereto. A tapered second opening OP2 is formed in this way. The first opening OP1 and the tapered second opening OP2 form a recess R. The recess R penetrates through the barrier layer 120 and extends into the channel layer 110. In the recess R, the vertical side surface 120s of the barrier layer 120 constitutes a vertical sidewall profile S1 and the inclined side surface 110s of the channel layer 110 constitutes an angled sidewall profile S2.

[0037] According to an embodiment of the present invention, for example, the inclined side surface 110s of the channel layer 110 is inclined at an angle θ ranging from 60 degrees to 80 degrees, preferably, at an angle θ ranging from 65 degrees to 75 degrees, to a horizontal plane HL. Forming the inclined side surface 110s of the channel layer 110 at the angle θ between 60 degrees and 80 degrees can ensure the smallest dangling bond density.

[0038] As shown in FIG. 4, an Ohmic contact metal 150 is formed in the recess R, wherein the Ohmic contact metal 150 is in direct contact with the barrier layer 120, the two-dimensional electron gas layer 2DEG and the channel layer 110 in the recess R. According to an embodiment of the present invention, the Ohmic contact metal 150 may include titanium and aluminum. According to an embodiment of the present invention, the Ohmic contact metal 150 may include titanium or aluminum, but is not limited thereto.

[0039] As shown in FIG. 6, according to an embodiment of the present invention, the angled sidewall profile S2 is also formed in the two-dimensional electron gas layer 2DEG.

[0040] As shown in FIG. 7, according to another embodiment of the present invention, the vertical sidewall profile S1 is also formed in the two-dimensional electron gas layer 2DEG In this example, the Ohmic contact metal 150 is in direct contact with the vertical side surface 120s of the barrier layer 120 and the two-dimensional electron gas layer 2DEG in the recess R, and is in direct contact with the inclined side surface 110s of the channel layer 110 in the recess R.

[0041] Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.