POWER MANAGEMENT CIRCUIT SUPPORTING PHASE CORRECTION IN AN ANALOG SIGNAL

Abstract

A power management circuit supporting phase correction in an analog signal is disclosed. The power management circuit includes a power amplifier circuit configured to amplify an analog signal having a time-variant power envelope based on a modulated voltage. The power management circuit also includes an envelope tracking (ET) integrated circuit (ETIC) configured to generate the modulated voltage and a modulated phase correction voltage to thereby cause a phase change in the analog signal. In embodiments disclosed herein, a correlation between the time-variant power envelope, the modulated voltage, and the modulated phase correction voltage is explored to thereby allow the ETIC to generate the modulated voltage and the modulated phase correction voltage based on the time-variant power envelope. As a result, it is possible to enable good time and phase alignment between the modulated voltage and the time-variant power envelope to thereby improve efficiency and linearity of the power amplifier circuit.

Claims

1. A power management circuit comprising: a power amplifier circuit configured to amplify an analog signal based on a modulated voltage; and an envelope tracking (ET) integrated circuit (ETIC) comprising: a voltage modulation circuit configured to: receive an envelope indication signal corresponding to a time-variant power envelope of the analog signal; and generate the modulated voltage based on the envelope indication signal; and a phase correction circuit configured to generate a modulated phase correction voltage based on the envelope indication signal to thereby cause a phase change in the analog signal.

2. The power management circuit of claim 1, wherein the power amplifier circuit comprises a phase shifter circuit configured to: determine a phase shift corresponding to the modulated phase correction voltage; and phase-shift the analog signal based on the determined phase shift.

3. The power management circuit of claim 2, wherein the power amplifier circuit further comprises a power amplifier configured to amplify the phase-shifted analog signal based on the modulated voltage.

4. The power management circuit of claim 2, wherein the phase shifter circuit is further configured to adjust an amplitude of the analog signal.

5. The power management circuit of claim 1, further comprising a transceiver circuit configured to generate the envelope indication signal.

6. The power management circuit of claim 5, wherein the transceiver circuit comprises: a signal processing circuit configured to generate the analog signal having the time-variant power envelope; and a target voltage circuit configured to: generate a target voltage that tracks the time-variant power envelope of the analog signal; generate the envelope indication signal that indicates the target voltage; and provide the envelope indication signal to the ETIC.

7. The power management circuit of claim 6, wherein the target voltage circuit is further configured to generate the target voltage based on an isogain lookup table (LUT) that correlates a time-variant amplitude of the time-variant power envelope with the target voltage.

8. The power management circuit of claim 6, wherein the phase correction circuit comprises an isophase lookup table (LUT) configured to correlate the target voltage with the modulated phase correction voltage.

9. The power management circuit of claim 6, wherein the ETIC further comprises a voltage equalizer configured to equalize the target voltage.

10. The power management circuit of claim 6, wherein the phase correction circuit comprises a frequency equalizer configured to equalize the target voltage.

11. The power management circuit of claim 6, wherein the phase correction circuit comprises a frequency equalizer configured to equalize the modulated phase correction voltage.

12. The power management circuit of claim 5, wherein the transceiver circuit comprises a signal processing circuit configured to: generate the analog signal having the time-variant power envelope; generate the envelope indication signal that indicates a time-variant amplitude of the time-variant power envelope; and provide the envelope indication signal to the ETIC.

13. The power management circuit of claim 12, wherein: the ETIC further comprises a target voltage circuit configured to generate a target voltage based on an isogain lookup table (LUT) that correlates the time-variant amplitude of the time-variant power envelope with the target voltage; and the voltage modulation circuit is further configured to generate the modulated voltage based on the target voltage.

14. The power management circuit of claim 12, wherein the phase correction circuit comprises an isophase lookup table (LUT) configured to correlate the time-variant amplitude of the time-variant power envelope with the modulated phase correction voltage.

15. A power management circuit comprising: a power amplifier circuit configured to amplify an analog signal based on a modulated voltage; an envelope tracking (ET) integrated circuit (ETIC) configured to generate the modulated voltage; and a transceiver circuit configured to: generate the analog signal having a time-variant power envelope; generate a modulated phase correction voltage based on the time-variant power envelope of the analog signal; generate an envelope indication signal that indicates the modulated phase correction voltage; and provide the envelope indication signal to the ETIC to thereby cause a phase change in the analog signal at the power amplifier circuit.

16. The power management circuit of claim 15, wherein the transceiver circuit comprises: a signal processing circuit configured to generate the analog signal having the time-variant power envelope; and an isophase lookup table (LUT) configured to: generate the modulated phase correction voltage based on a time-variant amplitude of the time-variant power envelope; generate the envelope indication signal that indicates the modulated phase correction voltage; and provide the envelope indication signal to the ETIC.

17. The power management circuit of claim 16, wherein the ETIC comprises: a target voltage circuit configured to generate a target voltage based on an isogain lookup table (LUT) that correlates the modulated phase correction voltage with the target voltage; and a voltage modulation circuit configured to generate the modulated voltage based on the target voltage.

18. The power management circuit of claim 17, wherein the power amplifier circuit comprises a phase shifter circuit configured to: determine a phase shift corresponding to the modulated phase correction voltage; and phase-shift the analog signal to the determined phase shift.

19. The power management circuit of claim 18, wherein the phase shifter circuit is further configured to adjust an amplitude of the analog signal.

20. The power management circuit of claim 18, wherein the power amplifier circuit further comprises a power amplifier configured to amplify the phase-shifted analog signal based on the modulated voltage.

Description

BRIEF DESCRIPTION OF THE DRAWING FIGURES

[0010] The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.

[0011] FIG. 1 is a schematic diagram of an exemplary power amplifier circuit that can be adapted according to various embodiments of the present disclosure to support phase correction in an analog signal;

[0012] FIG. 2 is a schematic diagram providing an exemplary illustration of the power amplifier circuit of FIG. 1 configured according to one embodiment of the present disclosure;

[0013] FIG. 3 is a schematic diagram providing an exemplary illustration of the power amplifier circuit of FIG. 1 configured according to another embodiment of the present disclosure; and

[0014] FIG. 4 is a schematic diagram of an exemplary power amplifier circuit configured according to an alternative embodiment of the present disclosure.

DETAILED DESCRIPTION

[0015] The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

[0016] It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

[0017] It will be understood that when an element such as a layer, region, or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being “over” or extending “over” another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly over” or extending “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.

[0018] Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.

[0019] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and/or “including” when used herein specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

[0020] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0021] Embodiments are described herein with reference to a power management circuit supporting phase correction in an analog signal. The power management circuit includes a power amplifier circuit configured to amplify an analog signal having a time-variant power envelope based on a modulated voltage. The power management circuit also includes an envelope tracking (ET) integrated circuit (ETIC) configured to generate the modulated voltage and a modulated phase correction voltage to thereby cause a phase change in the analog signal. In embodiments disclosed herein, a correlation between the time-variant power envelope, the modulated voltage, and the modulated phase correction voltage is explored to thereby allow the ETIC to generate the modulated voltage and the modulated phase correction voltage based on the time-variant power envelope of the analog signal. As a result, it is possible to enable good time and phase alignment between the modulated voltage and the time-variant power envelope to thereby improve efficiency and linearity of the power amplifier circuit.

[0022] FIG. 1 is a schematic diagram of an exemplary power amplifier circuit 10 that can be adapted according to various embodiments of the present disclosure to support phase correction in an analog signal 12. The power management circuit 10 includes a power amplifier circuit 14 and an ETIC 16. The power amplifier circuit 14 is configured to amplify the analog signal 12 based on a modulated voltage V.sub.CC, which can be an ET modulated voltage or an average power tracking (APT) modulated voltage. The ETIC 16 is configured to generate the modulated voltage V.sub.CC, which tracks a time-variant power envelope P.sub.POWER(t) of the analog signal 12, and a modulated phase correction voltage V.sub.PHASE to thereby cause a phase change in the analog signal 12. In embodiments disclosed herein, a correlation between the time-variant power envelope P.sub.POWER(t), the modulated voltage V.sub.CC, and the modulated phase correction voltage V.sub.PHASE is explored to thereby allow the ETIC 16 to generate the modulated voltage V.sub.CC and the modulated phase correction voltage V.sub.PHASE based on the time-variant power envelope P.sub.POWER(t) of the analog signal 12. As a result, it is possible to enable good time and phase alignment between the modulated voltage V.sub.CC and the time-variant power envelope P.sub.POWER(t) to thereby improve efficiency and linearity of the power amplifier circuit 14.

[0023] The ETIC 16 includes a voltage modulation circuit 18 and a phase correction circuit 20. The voltage modulation circuit 18 receives an envelope indication signal 22. In various embodiments further discussed in FIGS. 2-4, the envelope indication signal 22 can be adapted to indicate the time-variant power envelope P.sub.POWER(t) in a number of ways. Accordingly, the voltage modulation circuit 18 can be configured to generate the modulated voltage V.sub.CC and the phase correction circuit 20 can be configured to generate the modulated phase correction voltage V.sub.PHASE all based on the envelope indication signal 22.

[0024] In an embodiment, the power management circuit 10 can include or be coupled to a transceiver circuit 24. The transceiver circuit 24 can be configured to generate and provide the analog signal 12 to the power amplifier circuit 14. In addition, the transceiver circuit 24 is also configured to generate and provide the envelope indication signal 22 to the ETIC 16. Given that the transceiver circuit 24 generates the analog signal 12 associated with the time-variant power envelope P.sub.POWER(t), the transceiver circuit 24 is able to provide an indication of the time-variant power envelope P.sub.POWER(t) via the envelope indication signal 22.

[0025] The power amplifier circuit 14 can be configured to include a phase shifter circuit 26 and a power amplifier 28. The phase shifter circuit 26 is coupled to the phase correction circuit 20 to receive the modulated phase correction voltage V.sub.PHASE. The phase shifter circuit 26 may include internal storage (not shown), such as registers for example, to store a correlation between various levels of the modulated phase correction voltage V.sub.PHASE and various degrees of phase shift. For example, storing a correlation between the modulated phase correction voltage V.sub.PHASE of 0 V, 1 V, and 2 V and a phase shift of 0°, 1°, and 2°, respectively. Accordingly, the phase shifter circuit 26 can determine a phase shift based on the modulated phase correction voltage V.sub.PHASE and phase-shift the analog signal 12 based on the determined phase shift.

[0026] In one embodiment, the phase shifter circuit 26 can operate as a passive phase shift to only cause the phase change in the analog signal 12. As such, the modulated phase correction voltage V.sub.PHASE does not need to convey power to the phase shifter circuit 26. In another embodiment, the phase shifter circuit 26 can operate as an active phase shift to not only cause the phase change in the analog signal 12, but also amplify the analog signal 12. As such, the modulated phase correction voltage V.sub.PHASE needs to convey power to the phase shifter circuit 26.

[0027] The power amplifier 28 can be any type of power amplifier, including but not limited to a Doherty power amplifier, differential power amplifier, multi-stage power amplifier, single-stage power amplifier, etc. The power amplifier 28 is coupled to the phase shifter circuit 26 to amplify the analog signal 12, which may have been phase-shifted and/or amplitude-adjusted by the phase shifter circuit 26.

[0028] The various embodiments of the power management circuit 10 are now discussed in detail with reference to FIGS. 2-4.

[0029] FIG. 2 is a schematic diagram providing an exemplary illustration of the power management circuit 10 of FIG. 1 configured according to one embodiment of the present disclosure. Common elements between FIGS. 1 and 2 are shown therein with common element numbers and will not be re-described herein.

[0030] Herein, the transceiver circuit 24 is configured to include a signal processing circuit 30 and a target voltage circuit 32. The signal processing circuit 30 is configured to generate the analog signal 12 and, accordingly, the time-variant power envelope P.sub.POWER(t). In a non-limiting example, the signal processing circuit 30 can include a digital baseband circuit (not shown) that generates a digital version of the analog signal 12 and a digital-to-analog converter (not shown) to convert the digital version of the analog signal 12 into the analog signal 12. In an embodiment, the digital version of the analog signal 12 can be so generated to include an in-phase (I) component and a quadrature (Q) component. Accordingly, the signal processing circuit 30 can sample the time-variant power envelope P.sub.POWER(t) to thereby determine a time-variant amplitude (expressed as √{square root over (I.sup.2+Q.sup.2)}) of the time-variant power envelope P.sub.POWER(t).

[0031] In an embodiment, the target voltage circuit 32 can be configured to include an isogain lookup table (LUT) preconfigured to correlate the time-variant amplitude (√{square root over (I.sup.2+Q.sup.2)}) of the time-variant power envelope P.sub.POWER(t) with a target voltage V.sub.TGT. Herein, the term “isogain” refers to a constant gain relative to the time-variant amplitude (√{square root over (I.sup.2+Q.sup.2)}) of the time-variant power envelope P.sub.POWER(t).

[0032] As such, the target voltage circuit 32 can generate the target voltage V.sub.TGT having a time-variant target voltage envelope ENV.sub.TGT(t) that tracks the time-variant amplitude (√{square root over (I.sup.2+Q.sup.2)}) of the time-variant power envelope P.sub.POWER(t) based on the isogain LUT. Accordingly, the target voltage circuit 32 can generate the envelope indication signal 22 to indicate the target voltage V.sub.TGT in association with the time-variant target voltage envelope ENV.sub.TGT(t) and provide the envelope indication signal 22 to the ETIC 16.

[0033] The ETIC 16 is configured to explore a correlation between the time-variant power envelope P.sub.POWER(t), the modulated voltage V.sub.CC, and the modulated phase correction voltage V.sub.PHASE such that the modulated voltage V.sub.CC and the modulated phase correction voltage V.sub.PHASE can both be generated based on the time-variant target voltage envelope ENV.sub.TGT(t) of the target voltage V.sub.TGT. As mentioned earlier, the time-variant amplitude (√{square root over (I.sup.2+Q.sup.2)}) is sampled from the time-variant power envelope P.sub.POWER(t) and the target voltage V.sub.TGT is generated based on the time-variant amplitude (√{square root over (I.sup.2+Q.sup.2)}). In this regard, the target voltage V.sub.TGT is a function F.sub.V( ) of the time-variant power envelope P.sub.POWER(t), as expressed in equation (Eq. 1) below.

V.sub.TGT=F.sub.V(P.sub.POWER(t))  (Eq. 1)

[0034] The modulated phase correction voltage V.sub.PHASE can be a function F.sub.ϕ( ) of the time-variant power envelope P.sub.POWER(t), as expressed in equation (Eq. 2) below. In a non-limiting example, the function F.sub.ϕ( ) an be established by an isophase LUT 34 in the phase correction circuit 20.

V.sub.PHASE=F.sub.ϕ(P.sub.POWER(t))  (Eq. 2)

[0035] From equation (Eq. 1), the time-variant power envelope P.sub.POWER(t) can be expressed as a function of the target voltage V.sub.TGT, as shown in equation (Eq. 3) below.

P.sub.POWER(t)=F.sub.V.sup.−1(V.sub.TGT)  (Eq. 3)

[0036] By substituting the time-variant power envelope P.sub.POWER(t) in equation (Eq. 2) with the time-variant power envelope P.sub.POWER(t) in equation (Eq. 3), the modulated phase correction voltage V.sub.PHASE becomes a function of the target voltage V.sub.TGT, as expressed in equation (Eq. 4) below.

V.sub.PHASE=F.sub.ϕ(F.sub.V.sup.−1(V.sub.TGT))  (Eq. 4)

[0037] As shown in the equation (Eq. 4), it is possible to generate the modulated phase correction voltage V.sub.PHASE from the target voltage V.sub.TGT based on the function F.sub.ϕ(F.sub.V.sup.−1( )). In a non-limiting example, the function F.sub.ϕ(F.sub.V.sup.−1( )), which correlates the target voltage V.sub.TGT with the modulated phase correction voltage V.sub.PHASE, can be established by an isophase LUT 34 in the phase correction circuit 20. As a result, the ETIC 16 can be configured to generate both the modulated voltage V.sub.CC and the modulated phase correction voltage V.sub.PHASE based on the target voltage V.sub.TGT, as indicated by the envelope indication signal 22.

[0038] Accordingly, the voltage modulation circuit 18 can be configured to generate the modulated voltage V.sub.CC as an ET modulated voltage based on the target voltage V.sub.TGT. The voltage modulation circuit 18 is configured to provide the modulated voltage V.sub.CC to the power amplifier 28 in the power amplifier circuit 14 for amplifying the analog signal 12.

[0039] The ETIC 16 may include a voltage equalizer 36 to equalize the target voltage V.sub.TGT. In a non-limiting example, the voltage equalizer 36 can implement a second-order complex-zero and a real-zero transfer function to help reduce ripples (a.k.a. voltage disturbance) in the modulated voltage V.sub.CC, which may be caused by, for example, trace inductance between the ETIC 16 and the power amplifier 28.

[0040] In an alternative embodiment, the voltage modulation circuit 18 can also generate the modulated voltage V.sub.CC as an APT modulated voltage. In this regard, the target voltage V.sub.TGT may instead be associated with a time-invariant target voltage envelope (not shown). Nevertheless, the voltage modulation circuit 18 can still generate the modulated voltage V.sub.CC based on the target voltage V.sub.TGT indicated by the envelope indication signal 22.

[0041] The phase correction circuit 20 may include a frequency equalizer 38. In one embodiment, the frequency equalizer 38 may be provided before the isophase LUT 34 to equalize the target voltage V.sub.TGT. In another embodiment, the frequency equalizer 38 may be provided after the isophase LUT 34 to equalize the modulated phase correction voltage V.sub.PHASE. In a non-limiting example, the frequency equalizer 38 can implement a real-zero transfer function to help reduce frequency disturbance in the analog signal 12.

[0042] FIG. 3 is a schematic diagram providing an exemplary illustration of the power management circuit 10 of FIG. 1 configured according to another embodiment of the present disclosure. Common elements between FIGS. 2 and 3 are shown therein with common element numbers and will not be re-described herein.

[0043] Herein, the target voltage circuit 32 is moved from the transceiver circuit 24 in FIG. 2 into the ETIC 16. In this regard, the signal processing circuit 30 in the transceiver circuit 24 is instead configured to generate the envelope indication signal 22 that indicates the time-variant amplitude (√{square root over (I.sup.2+Q.sup.2)}) of the time-variant power envelope P.sub.POWER(t). The target voltage circuit 32 in the ETIC 16 is then configured to generate the target voltage V.sub.TGT based on the time-variant amplitude (√{square root over (I.sup.2+Q.sup.2)}) of the time-variant power envelope P.sub.POWER(t). The isophase LUT 34, one the other hand, is configured to correlate the time-variant amplitude (√{square root over (I.sup.2+Q.sup.2)}) of the time-variant power envelope P.sub.POWER(t) with the modulated phase correction voltage V.sub.PHASE.

[0044] FIG. 4 is a schematic diagram of an exemplary power amplifier circuit 40 configured according to an alternative embodiment of the present disclosure. Common elements between FIGS. 2, 3, and 4 are shown therein with common element numbers and will not be re-described herein.

[0045] Herein, the power management circuit 40 includes an ETIC 42. The ETIC 42 includes the voltage modulation circuit 18 configured to generate the modulated voltage V.sub.CC based on the target voltage V.sub.TGT. The power management circuit 40 also includes a transceiver circuit 44, which includes the signal processing circuit 30 and an isophase LUT 46. The isophase LUT 46 is configured to correlate the modulated phase correction voltage V.sub.PHASE with the time-variant amplitude (√{square root over (I.sup.2+Q.sup.2)}) of the time-variant power envelope P.sub.POWER(t). Accordingly, the transceiver circuit 44 can generate the modulated phase correction voltage V.sub.PHASE based on the isophase LUT 46 and generate the envelope indication signal 22 that indicates the modulated phase correction voltage V.sub.PHASE.

[0046] The ETIC 42 includes a target voltage circuit 48, which can implement an isogain LUT that correlates the modulated phase correction voltage V.sub.PHASE with the target voltage V.sub.TGT. Accordingly, the voltage modulation circuit 18 can generate the modulated voltage V.sub.CC based on the target voltage V.sub.TGT.

[0047] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.