MICROFABRICATED ION TRAP WITH IMPROVED THERMAL CHARACTERISTICS

Abstract

In an ion trap chip, an RF electrode for producing a radio-frequency ion-trapping electric field is formed in one of a plurality of metallization layers formed on a substrate and separated from each other by intermetal dielectric. At least two spans of the RF electrode are suspended between support pillars over a void defined within one or more layers of intermetal dielectric. For each span that is suspended between a first and a second support pillar, an area A.sub.Total and an area A.sub.Supported are defined. A.sub.Total is the total electrode area from an initial edge of the first support pillar to an initial edge of the second support pillar. A.sub.Supported is the electrode area directly underlain by the first support pillar. In each span that is suspended from a first support pillar to a second support pillar, A.sub.Supported is not more than one-half of A.sub.Total.

Claims

1. A method for forming an ion trap chip, the ion trap chip including an RF electrode including at least two spans, each of the at least two spans suspended from a first respective support pillar to a second respective support pillar, the method comprising the steps of: forming a first metal layer on a substrate; forming a first intermetal dielectric layer on the first metal layer; etching a first plurality of closed-loop etch-stop via openings through the first intermetal dielectric layer; filling the first plurality of closed-loop etch-stop via openings with sacrificial metal to thereby form a first plurality of vertical etch-stop vias and a first plurality of protected intermetal dielectric columns, each of the first plurality of protected intermetal dielectric columns surrounded by a corresponding one of the first plurality of vertical etch-stop vias; forming a second metal layer on the first intermetal dielectric layer; removing a portion of the second metal layer between adjacent ones of the first plurality of vertical etch-stop vias to form a first plurality of etch holes; forming a second intermetal dielectric layer on the second metal layer; etching a second plurality of closed-loop etch-stop via openings through the second intermetal dielectric layer; filling the second plurality of closed-loop etch-stop via openings with sacrificial metal to thereby form a second plurality of vertical etch-stop vias and a second plurality of protected intermetal dielectric columns, each of the second plurality of protected intermetal dielectric columns surrounded by a corresponding one of the second plurality of vertical etch-stop vias; forming a third metal layer on the second intermetal dielectric layer, the third metal layer including a second plurality of etch holes between the second plurality of vertical etch-stop vias; removing a portion of the third metal layer to form a second plurality of etch holes; simultaneously selectively etching the first intermetal dielectric layer between adjacent ones of the first plurality of vertical etch-stop vias using the first plurality of etch holes, and the second intermetal dielectric layer between adjacent ones of the second plurality of vertical etch-stop vias using the second plurality of etch holes; and subsequently simultaneously selectively removing the first plurality of vertical etch-stop vias and the second plurality of vertical etch-stop vias to thereby form the support pillars from which the at least two spans are suspended, each support pillar including a corresponding one of the first plurality of protected intermetal dielectric columns and a corresponding one of the second plurality of protected intermetal dielectric columns.

2. The method of claim 1, wherein each of the first metal layer, the second metal layer, and the third metal layer includes aluminum.

3. The method of claim 1, wherein each of the first intermetal dielectric layer and the second intermetal dielectric layer includes at least one of silicon dioxide, aluminum nitride, silicon nitride, alumina, diamond, or silicon carbide.

4. The method of claim 1, wherein the sacrificial metal includes tungsten.

5. The method of claim 1, wherein the step of removing a portion of the third metal layer forms the RF electrode.

6. The method of claim 1, wherein the step of simultaneously selectively etching the first intermetal dielectric layer employs hydrofluoric acid.

7. The method of claim 1, wherein the step of simultaneously selectively removing the first plurality of vertical etch-stop vias employs hydrogen peroxide.

8. The method of claim 1, wherein: a shape and a size of each of the first plurality of vertical etch-stop vias is the same as a shape and a size of the second plurality of vertical etch-stop vias; and each of the second plurality of vertical etch-stop vias is directly underlain by a respective one of the first plurality of vertical etch-stop vias.

9. The method of claim 1, wherein a shape of each of the first plurality of vertical etch-stop vias is the same as a shape of the second plurality of vertical etch-stop vias; and a size of each of the first plurality of vertical etch-stop vias is different from a size of the second plurality of vertical etch-stop vias.

10. The method of claim 1, wherein a shape of each of the first plurality of vertical etch-stop vias and a shape of each of the second plurality of vertical etch-stop vias is one of a circle or a rectangle.

11. The method of claim 1, wherein a distance between adjacent ones of the support pillars is between 35 μm and 100 μm.

12. The method of claim 1, further comprising, after the step of filling the second plurality of etch-stop via openings, the steps of: forming a fourth metal layer on the second intermetal dielectric layer, the fourth metal layer including a third plurality of etch holes between the second plurality of vertical etch-stop vias; forming a third intermetal dielectric layer on the fourth metal layer, the fourth metal layer and the third intermetal dielectric layer thereby located between the second intermetal layer and the third metal layer; etching a third plurality of etch-stop via openings through the third intermetal dielectric layer; and filling the third plurality of etch-stop via openings with sacrificial metal to thereby form a third plurality of vertical etch-stop vias; wherein: the step of simultaneously selectively etching the first intermetal dielectric layer further includes simultaneously selectively etching the third intermetal dielectric layer between adjacent ones of the third plurality of vertical etch-stop vias using the third plurality of etch holes; and the step of simultaneously selectively removing the first plurality of vertical etch-stop vias further includes simultaneously selectively removing the third plurality of vertical etch-stop vias.

13. A method for forming intermetal dielectric columns, the method comprising the steps of: forming a first metal layer on a substrate; forming an intermetal dielectric layer on the first metal layer; etching a plurality of closed-loop etch-stop via openings through the intermetal dielectric layer; filling the plurality of closed-loop etch-stop via openings with sacrificial metal to thereby form a plurality of vertical etch-stop vias and a plurality of protected intermetal dielectric columns, each of the plurality of protected intermetal dielectric columns surrounded by a corresponding one of the plurality of vertical etch-stop vias; forming a second metal layer on the first intermetal dielectric layer; removing a portion of the second metal layer between adjacent ones of the plurality of vertical etch-stop vias to form a plurality of etch holes; selectively etching the intermetal dielectric layer between adjacent ones of the plurality of vertical etch-stop vias using the plurality of etch holes; and subsequently selectively removing the plurality of vertical etch-stop vias to thereby form the intermetal dielectric columns.

14. The method of claim 13, wherein each of the first metal layer and the second metal layer includes aluminum.

15. The method of claim 13, wherein the intermetal dielectric layer includes at least one of silicon dioxide, aluminum nitride, silicon nitride, alumina, diamond, or silicon carbide.

16. The method of claim 13, wherein the sacrificial metal includes tungsten.

17. The method of claim 13, wherein the step of selectively etching the intermetal dielectric layer employs hydrofluoric acid.

18. The method of claim 13, wherein the step of selectively removing the plurality of vertical etch-stop vias employs hydrogen peroxide.

19. The method of claim 13, wherein a shape of each of the plurality of vertical etch-stop vias is one of a circle or a rectangle.

20. The method of claim 13, wherein a distance between adjacent ones of the intermetal dielectric columns is between 35 μm and 100 μm.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0055] FIG. 1 is a cross-sectional cartoon view of an example ion trap that uses two metallization layers.

[0056] FIG. 2 is an overhead view of the ion trap of FIG. 1.

[0057] FIG. 3 is an overhead view of a fabricated prototype similar to the ion trap of FIGS. 1 and 2. The loading hole and part of the electrode layout are visible in the figure.

[0058] FIG. 4 is a detail of the prototype of FIG. 3, shown in perspective view. Visible features in the figure include portions of the loading hole, the two inner dc electrodes bracketing the loading hole, and the RF electrode.

[0059] FIG. 5 is a notional cartoon view, in cross-section, of an example ion trap that uses four metallization layers. The figure is highly simplified and its scale is grossly distorted for clarity of presentation.

[0060] FIGS. 6A and 6B provide a cross-sectional view, approximately to scale, of the slotted quantum region of an ion trap fabricated in four metallization layers. FIG. 6B is a detail of FIG. 6A.

[0061] FIG. 7 is a plan view of a complete ion trap chip, in an illustrative example.

[0062] FIG. 8 is a cutaway perspective view of a portion of a suspended RF electrode, including a capacitively coupled RF amplitude sensor.

[0063] FIG. 9 is an elevational sectional view of the RI amplitude sensor of FIG. 8.

[0064] FIG. 10 is a cartoon drawing, in cross-section, of part of an example ion-trap chip. The chip has six metallization levels; the top three levels are included in the figure. The portion shown is taken from a region that includes part of the RF electrode.

[0065] FIGS. 11A, 11B, and 12 show a portion of an RF electrode in an example implementation. FIG. 11A is a perspective view of one pillar together with the overlying portion of the RF electrode. FIG. 11B is a perspective view of two pillars together with the overlying span of the RF electrode. FIG. 12 is a view of a pillar in cross-section. The figures are notional only, and they are not drawn to scale.

DETAILED DESCRIPTION

[0066] FIGS. 1 and 2 provide schematic views of an example ion trap of the kind reported in D. Stick et al., arXiv:1008.0990v2, cited above. The ion trap described here is offered solely for illustrative purposes and is not meant to be limiting.

[0067] FIG. 1 is a cross-sectional view of the ion trap, and FIG. 2 is an overhead view. FIG. 3 is an overhead view of a fabricated prototype, showing the loading hole and part of the electrode layout. FIG. 4 is a detail in perspective view, showing portions of the loading hole, the two inner dc electrodes bracketing the loading hole, and the RF electrode.

[0068] The device is fabricated on an SOI wafer 100 using known photolithographic techniques and other techniques of CMOS and MEMS processing. It includes two metal layers 102, 104 (M1 and M2) separated by an insulating layer 106 of silicon dioxide. Geometrically, the trap has a symmetric six-rail design with a 100-μm-wide slot 108 (the “loading hole”) etched through the substrate to allow for backside ion loading and optical access.

[0069] It should be noted in this regard that although silicon dioxide is a typical dielectric material to interpose between metallization levels, alternative materials are feasible and are not excluded from the scope of the present invention. Some possible alternatives include, without limitation, aluminum nitride, silicon nitride, alumina, diamond, and silicon carbide. Several of these alternatives, such as diamond, offer the benefit of high coefficients of thermal conductivity, which is helpful for thermal management in the ion trap. Although some of these materials have undesirably high dielectric constants, that disadvantage may in some cases be offset by the advantage of high thermal conductivity. In this and further illustrative embodiments described below, the interlevel dielectric is silicon dioxide, also referred to as “oxide”. However, this is by way of example only, and it should not be understood as excluding other material choices.

[0070] Likewise, although a silicon or SOI wafer constitutes a typical substrate, other insulating or semiconducting materials may be suitable substrate materials and are not excluded from the scope of the present invention. Some possible alternative materials include, without limitation, silicon dioxide, alumina, silicon carbide, diamond, and gallium arsenide and other III-V semiconductors.

[0071] Adjacent to the slot, as best seen in FIG. 3, are split central control electrodes 110, 112, two electrodes 114, 116 with RF voltages applied, and forty outer segmented control electrodes 118, 120. The control electrodes (also referred to as “dc electrodes”) have quasistatic voltages applied to them.

[0072] As best seen in FIG. 1, the oxide layer 106, 14 μtm thick, separates the top metal layer from the bottom metal layer. Each metal layer is aluminum, 2.4 μm thick.

[0073] Turning back to FIG. 3, the two RF rails 114, 116 are each 60 μm thick and are separated by 140 μm. The combined capacitance of the RF rails is about 7 pF to RF ground.

[0074] The equilibrium trapping position is about 80 μm above the trap surface.

[0075] Turning again to FIG. 1, the oxide insulating layer 106 is controllably etched back to expose the RF ground plane 102 in M1 directly beneath the electrodes, and to recess the oxide support walls for the electrodes in M2. Because of this recess 130, the electrode metal overhangs the oxide, thus reducing the amount of insulator exposed to a line-of-sight from the trapping region. One benefit of this overhang is that it enables a metal of choice to be evaporated onto the top electrodes without causing short circuits.

[0076] The electrical connections 132 between metallization layers, as seen in FIG. 1, are made by 2.7-μm via technology.

[0077] Optionally, the exposed silicon surfaces can be evaporatively coated with a ground layer, for example a 500-nm layer of gold.

[0078] The implementation shown in FIGS. 1 and 2 is readily modified by adding additional metallization layers, using conventional CMOS fabrication techniques. In particular, it may be advantageous for at least some applications to add a ground plane on a new M1 layer beneath the top metal layer (i.e., beneath the layer shown in FIGS. 1 and 2 and labeled as the M1 layer in the illustrated implementation).

[0079] For example, FIG. 5 provides a notional cross-sectional view of a more recent fabrication technology for ion traps that uses four metallization layers 501, 502, 503, 504, i.e., M1-M4. The respective layers are separated by oxide pillars. Connections are made among the layers with tungsten via interconnects. FIG. 5 is not drawn to scale, and various simplifications have been made for clarity of presentation.

[0080] The electrodes in the top metal (M4) overhang their supporting oxide walls 506, as described above. These overhangs are beneficial for, among other things, shielding the trapped ions from stray charges on the dielectric surfaces.

[0081] The DC and RF trap electrodes 508, 510 are fed by buried metal lines on M2. Microwave signals for controlling state transitions may be delivered by buried transmission lines on M3 and shielded by a surface ground plane 512 on M4.

[0082] FIGS. 6A and 6B provide a more realistic drawing, approximately to scale, of the slotted quantum region of an ion trap fabricated in four metallization layers. FIG. 6B is a detail of FIG. 6A. The metallization layer M1A is a diffusion barrier of titanium nitride. The other metallization layers (i.e., M1B, M2, M3, and M4) are composed of aluminum alloyed with 0.5% copper. The non-limiting example that is illustrated has a 60-μm-wide slot 600 in the quantum region. In sequence from the center of the slot, the electrodes shown in the drawing are: DC control electrodes 602 in M3, RF electrodes 604 in M4, DC control electrodes 606 in M4, and a ground plane 608 in M3. Each inner DC electrode 602 is seen to be connected by tungsten vias 610 to the M1 level, and each outer DC electrode 606 is seen to be connected by tungsten vias 612 to the M2 level. Typical thicknesses are indicated on the drawing, including the height of the trapped ion 614 above the M4 level. The metallization levels and the exposed dielectric surfaces are overcoated with gold.

[0083] A still more recent advance in fabrication technology for ion traps uses six metallization layers. The additional metal layers provide more routing space to connect electrodes, which may be densely distributed, to the bond pads situated near the edges of the trap chip. By adding more metal layers, we can also increase the dielectric thickness between the RF electrodes and the ground planes. This has the benefit of reducing the overall capacitance of the RF electrode without sacrificing chip area that might be needed for the lithographic definition of structural features such as silicon dioxide support pillars for the electrodes.

[0084] In a non-limiting example of the six-level technology, electrodes are provided on the top metal (M6) layer, shielding is provided by ground planes on the next two layers (M5 and M4), signal routing is provided by traces on the next two layers (M3 and M2), and a ground plane is provided on the bottom layer (M1).

[0085] The RF electrode as shown in the preceding figures extends to bond pads at the periphery of the trap chip.

[0086] FIG. 7 is an illustrative example of a complete ion trap chip having a linear trap, shown in plan view. Features shown in the figure include the loading region 700 and the quantum region 702 of the chip, the RF electrode 703, a capacitive sensor 704 for measuring the RF voltage amplitude, and a bank 706 of onboard RF shunt capacitors that are integrated directly on the chip. Wirebond blocks 708 for input and output are also shown. Also indicated on the figure is a possible location 710 for thermoresistive temperature-sensing wires and resistive heating wires (not shown explicitly in the drawing). In the figure, the RF electrode is seen to terminate at bond pads at each of the two opposing ends of the chip.

[0087] As mentioned above, we have found that it is advantageous to suspend the RF electrode in order to reduce its capacitance and related dissipative effects that cause unwanted heating. FIG. 8 is a cutaway perspective view of a portion of a suspended RF electrode 801. The portion visible in the figure is shown supported by four pillars of silicon dioxide, the rest of the underlying intermetal dielectric having been removed by etching. The figure also shows a capacitively coupled sensor 800 used for measuring the voltage amplitude of the RF signal, and ground plane 802.

[0088] The RF electrode of FIGS. 7 and 8 is fabricated in the top metal layer of the chip. Although such top-level RF electrodes are a subject of current study, other designs are also possible, in which the RF electrode occupies a lower metallization level and in which the RE electrode may even be overlain by metal in a higher level. Hence, designs in which the RF electrode is formed in a metallization level below the top level are not excluded from the scope of the present invention.

[0089] In the example of FIG. 8, the top metal layer is the layer M4. For amplitude measurement, a capacitively coupled sensor plate is fabricated in the M3 804 and M2 803 metal layers. The sensor signal is passed vertically through vias from M3 804 to M2 803 and extracted on a lead fabricated in M2 803.

[0090] FIG. 9 is an elevational sectional view showing a detail of the sensor 900. It will be seen that the sensor is constituted as a capacitive voltage divider, with an upper capacitance 903 between the RF electrode 901 and the sensor plate 906, and a lower capacitance 908 between the sensor plate and a ground plane 902 in M1.

[0091] The signal from the sensor plate is routed out of the device on a trace on M2 that passes through a ground channel between ground planes. The pertinent ground planes in the example of FIGS. 8 and 9 are formed in M1 and M3. The lower capacitance is realized by the sensor routing trace and its surrounding ground planes.

[0092] An RF electrode in another example is shown in FIG. 10. FIG. 10 is a cartoon drawing of a partial cross-section of an ion-trap chip in a region that includes part of the RF electrode. The view, which is notional only and not to scale, shows the top five metallization levels (i.e., M2-M6) of a six-level chip. It should be understood, however, that this drawing is intended solely as an illustrative example and is not meant to be limiting in any respect.

[0093] With further reference to the figure, it will be seen that the RF electrode 1000 is formed in the top metal layer, i.e., the M6 metal layer, and that the longitudinal axis of the RF electrode runs across the figure view from left to right. It will be seen that each of the support pillars 1002 is constituted by a sequence of intermetal dielectric (e.g., silicon dioxide) layers 1004 formed between M2 and M3, M3 and M4, M4 and M5, and M5 and M6, respectively.

[0094] The selective etching process that forms the pillars will be described below. As will be explained, the oxide that will constitute each of the pillars is encased in an etch stop (of tungsten, for example) to protect it from the etchant that removes the surrounding oxide. The figure shows these etch stops 1006 in place before they are removed by a selective etchant.

[0095] The metallization 1008 at each intermediate position within each pillar (i.e., the metallization at levels M3, M4, and M5 in the example of FIG. 10) forms an annulus that wraps all the way around the oxide portion of its pillar. Each of these annuli extends beyond the outer boundary of the pillar oxide to form a metal overlap 1010 that extends into the void between pillars. Each annulus provides a land onto which the next higher tungsten etch stop is deposited. The RF electrode also extends beyond the outer boundaries of its supporting pillars, thus forming an overlap that extends perpendicular to the plane of the figure.

[0096] The annular lands are grounded through vias to a ground plane.

PROCESS DESCRIPTION

[0097] An example device can be made using techniques of deposition, patterning, and etching that are known from back-end-of-line (BEOL) CMOS fabrication technology. A useful reference in this regard is R. Jacob Baker, CMOS Circuit Design, Layout, and Simulation, Revised Third Edition, John Wiley & Sons (2008), Volume 1, Chapter 7, “CMOS Fabrication by Jeff Jessing,” pp. 161-212, particularly at pages 206-211.

[0098] Another useful reference is U.S. Pat. No. 6,893,578, issued to P.J. Clews et al. on May 17, 2005 under the title, “Selective Etchant for Oxide Sacrificial Material in Semiconductor Device Fabrication,” which is commonly owned herewith, and which is hereby incorporated herein in its entirety.

[0099] U.S. Pat. No. 6,893,578 describes a method of wet etching for semiconductor device fabrication that is useful in the present context. As described there, oxide sacrificial material is removed using an etching solution comprising a mixture of hydrofluoric acid (HF) and sulfuric acid (H2504). The hydrofluoric acid concentration according to the above-cited patent is generally in the range of 40-50% by weight HF, and the sulfuric acid concentration is generally at least 90% by weight H.sub.2SO.sub.4.

[0100] The hydrofluoric acid and sulfuric acid in the etching solution can be provided in a ratio HF:HSO that ranges from 1:3 to 3:1 or more, and preferably in the range of 1:1 to 3:1. These ratios in the range of 1:3 to 3:1 provide an etch selectivity greater than 100 for the oxide sacrificial material relative to a metal layer that comprises aluminum, such as an aluminum-5% copper metal layer. Etching can be performed with the etching solution at a temperature anywhere in the range of 5° -70° C.

[0101] The principle of selective etching to create dielectric support pillars is described, for example, in D. Stick (2010), which was cited above.

[0102] In an example implementation, the intermetallic dielectric layers are grown on a silicon wafer in multiple stages of plasma-enhanced chemical vapor deposition (PECVD) of silicon dioxide. The six metallization layers M1-M6 are vapor-deposited aluminum-5% copper. Electrical vias are formed by conventional vapor deposition of tungsten.

[0103] The pillars that support the RF electrode are defined by depositing vertical etch-stop layers of tungsten, as mentioned above. We refer to these etch stops as etch-stop “vias” because they can be deposited concurrently with electrical vias using the same process.

[0104] Each level of intermetal dielectric is polished flat by CMP prior to the tungsten deposition, and then subjected to a tungsten CMP after the vias (including etch-stop vias) are deposited.

[0105] After forming the RF electrode and other metal features on M6, the HF etch is performed to remove all of the sacrificial oxide in a single step. Etch holes formed through the RF electrode facilitate the entry of the HF etchant.

[0106] The tungsten etch stops are then removed using a conventional hydrogen peroxide wet etch.

EXAMPLE

[0107] FIGS. 11A, 11B, and 12 show a portion of an RF electrode in an example implementation. FIG. 11A is a perspective view of one pillar 1100 together with the overlying portion 1102 of the RF electrode. FIG. 11B is a perspective view of two pillars 1104, 1106 together with the overlying span 1108 of the RF electrode. FIG. 12 is a view of a pillar in cross-section. The figures are notional only, and they are not drawn to scale.

[0108] We performed mathematical modeling on the RF electrode of FIGS. 11 and 12 in order to find favorable design parameters with respect to capacitance, heating, and mechanical vibration.

[0109] In our design study, we assumed a thickness of 2 μm for the intermetal oxide dielectric 1200 between M5 and M6, and a total oxide thickness of 8.4 μm between M4 and M6. We also assumed a basic unit of 0.7 μm for the overlap distance. We let the RF electrode 1202 overlap the M5-M6 oxide by two units (i.e., a horizontal distance of 1.4 μm), and we let the oxide overlap the M5 metal by one unit (i.e., a horizontal distance of 0.7 μm). Accordingly, the 2-μm-thick layer of dielectric between the RF electrode and the M5 metal consisted of an oxide portion 0.7 μm wide and a vacuum portion 1204 1.4 μm wide.

[0110] In the design study, the support ratio, i.e., the ratio of RF electrode area supported by oxide to total RF electrode area, was maintained at 1:3. According to our estimate, that ratio (assuming a silicon dioxide dielectric) would minimize the steady-state operating temperature of the RF electrode. A smaller ratio would lead to a temperature increase due to reduced heat sinking, whereas a larger ratio would lead to a temperature increase due to increased capacitance.

[0111] Our design study was limited by particular choices of materials and layer thicknesses. Given a greater variety of design choices, a range of support ratios could be effective. As a general rule, however, it will be desirable for at least 50% of the total RF electrode area to be unsupported. In other words, the RF electrode will generally have a support ratio (supported area:total area) of 1:2 or less. Although even smaller ratios may be achievable, a ratio of 1:100 is believed to approach the limit of what is mechanically feasible.

[0112] The design parameters that we varied were the pitch of the support pillars and the length of the pillars in the longitudinal direction of the RF electrode. We also examined how changing the metal thickness of the RF electrode would affect deflection and mechanical resonance.

[0113] The range of pitches considered in our design study was 35 μm -100 μm. This range encompasses typical values for the length of an RF electrode span, given the particular materials and layer thicknesses chosen for our design study. However, these values should be understood as exemplary only, and as non-limiting.

[0114] The performance measures we examined were capacitance, steady-state operating temperature, electrostatic deflection, and mechanical resonant frequency. The capacitance is presented here as a relative quantity compared to a hypothetical baseline device having a continuous dielectric support structure under the RF electrode.

[0115] The baseline device is not described here in detail. However, it should be noted that in fabrication efforts, we have built up thick layers of oxide in successive depositions of oxide layers that are, e.g., 2 μm thick. To achieve acceptable results, we have found it desirable to include some metal between each pair of these layers, thus leading to metallization at M2, M3, etc. Hence, a practical realization of our hypothetical baseline device would contain metallization within the continuous dielectric support structure, and that metallization is predicted to increase the capacitance by 33%.

[0116] We modeled capacitance (as a fraction of the hypothetical baseline device capacitance) as a function of the pitch of the support pillars, taking as a representative design an RF electrode width (perpendicular to the longitudinal direction) of 100 μm and a pillar width (also perpendicular to the longitudinal direction) of 79 μm. We found that the capacitance decreased monotonically with pitch, and that it showed a stronger dependence below about 100 μm and a weaker dependence above that value. We also modeled the capacitance as a function of the pillar width. We found a near-linear increase in the capacitance as the pillar width increased.

[0117] According to a simple estimate, the steady-state operating temperature of the RF electrode is proportional to the square of the capacitance, divided by the pillar area. From that estimate, we predicted that the temperature would fall with increasing pillar length (in the longitudinal direction) up to about 40 μm, after which it would level off or rise gradually.

[0118] We modeled the steady-state operating temperature of the RF electrode, assuming an input voltage of 100V at a frequency of 100 MHz.

[0119] Our modeling of capacitance and temperature led to the values listed in Table 1 for selected combinations of design parameters. The capacitance fraction is expressed as a percentage of the capacitance of the baseline device. The column of the table labeled “Heat unit cell” lists the predicted electric power that is dissipated as heat, per unit cell of the structure. A unit cell may be defined, e.g., as the portion extending toward the right, from the left-hand edge of one pillar to the left-hand edge of the next pillar. The maximum temperature differential (Max AT) is the modeled maximum temperature difference between the RF electrode and an underlying silicon dioxide dielectric. It would be desirable to make Max ΔT as small as possible.

TABLE-US-00001 TABLE 1 Pillar Capacitance Heat unit Pitch Length fraction cell Max ΔT 35 10 μm 96% 32.2 μW 0.46K 70 30 μm 93% 60.5 μW 0.31K 50 15 μm 88% 38.7 μW 0.37K 80 30 μm 87% 60.5 μW 0.31K 70 20 μm 80% 44.8 μW 0.34K 100 30 μm 76% 57.8 μW 0.30K

[0120] We modeled the average downward force on the RF electrode due to an RF voltage of 300V. Table 2 lists the force on a single span of the RF electrode between pillars, and it also lists the maximum deflection of that span due to the electrical force for various combinations of design parameters. An electrode thickness of 1.2 μm is assumed.

TABLE-US-00002 TABLE 2 Pillar Capacitance Force on unit Max Pitch length fraction cell (300 V) amplitude 35 10 μm 96% 0.64 mN  84 nm 70 30 μm 93% 1.24 mN 231 nm 50 15 μm 88% 0.84 mN 151 nm 80 30 μm 87% 1.32 mN 414 nm 70 20 μm 80% 1.06 mN 384 nm 100 30 μm 76% 1.44 mN 1116 nm 

[0121] Excessive deflection is undesirable because it can change the equilibrium height of the trapped ion. Our studies showed, however, that deflections of 151 nm or less (and possibly also somewhat greater deflections) would be acceptable. In that regard, we found that a design having a pitch of 50 μm and a pillar length of 15 μm would yield a predicted deflection of 151 nm and a relatively low capacitance fraction of 88%. Because it offered such a favorable combination of performance measures, we chose that design for further study.

[0122] We also modeled the mechanical resonances of the RF electrode. The minimum resonance frequency that we predicted for each of various combinations of design parameters is listed in Table 3. In the event that mechanical resonances are exhibited in operation of the ion trap, it is desirable that the resonant frequencies be well separated from the secular frequencies of the trapped ion. In the study reported here, we hoped to find that the resonant frequencies would be higher than the secular frequencies of interest. (The first row of Table 3 relates to the hypothetical baseline device in a practical realization that includes intermediate metallization, which raises the capacitance. The second row of the table relates to the idealized baseline device that contains no intermediate metallization.

TABLE-US-00003 TABLE 3 Pillar Capacitance Max Min resonance Pitch length fraction Max ΔT deflection freq ∞ 133%  0.15K  36 nm ≈9 MHz Phoenix 100%  ≈9 MHz 35 10 μm 96% 0.46K  84 nm 7.1 MHz 70 30 μm 93% 0.31K 231 nm 3.3 MHz 50 15 μm 88% 0.37K 151 nm 4.0 MHz 80 30 μm 87% 0.31K 414 nm 2.3 MHz 70 20 μm 80% 0.34K 384 nm 2.3 MHz 100  30 μm 76% 0.30K 1116 nm  1.3 MHz

[0123] Typical secular frequencies are in the range 1-20 MHz, which roughly coincides with the minimum frequencies predicted by our modeling study. However, our modeling studies also showed that all of the predicted resonances are substantially damped out that if the material of the RF electrode has an internal damping coefficient (i.e., the imaginary part of the stiffness coefficient) that is at least 2×10.sup.−7. For an aluminum RF electrode, the internal damping coefficient is expected to be roughly 2×10.sup.−5. This gives us confidence that the ion trap can be operated with no significant interference from mechanical resonance.

[0124] Taking as a baseline the design with a pitch of 50 μm and a pillar length of 15 μm, we modeled some effects of doubling the RF electrode metal thickness from 1.2 μm to 2.4 μm, and the effect of perforating the RF electrode with holes for the introduction of the etchant that would suspend the RF electrode by removing oxide material. We have, in fact, considered fabricating a design using an RF electrode that is 2.4 μm or 2.5 μm thick, and even greater thicknesses are possible. The etch holes are a desirable feature for facilitating the introduction of the oxide etchant.

[0125] Table 4 shows the results of that study. As seen, doubling the metal thickness did not significantly affect the capacitance, but it reduced the maximum deflection by sixfold, and it almost doubled the minimum resonant frequency. We observed no effect from the etch holes on the deflection or on the resonant frequency.

TABLE-US-00004 TABLE 4 Min Pillar Capacitance Metal Max resonance length fraction thickness deflection frequency Comment 15 μm 88% 1.2 μm 151 nm  4.0 MHz 15 μm 88% 2.4 μm 25 nm 7.5 MHz 15 μm 88% 2.4 μm 25 nm 7.5 MHz Etch holes