HIGH-SPEED LOW-DISTORTION ENVELOPE DETECTOR AND METHOD THEREOF

Abstract

A method of envelope detection operates by receiving a RF (radio frequency) signal having a first voltage at a first node and a second voltage at a second node; using a common-mode source-follower (CMSF) having a first source follower and a second source follower connected in parallel and configured to receive the first voltage and the second voltage, respectively, and jointly output a first current to a third node in accordance with a sum of a second current and a third current received via a fourth node; establishing a first negative feedback control loop by converting the first current into the third current using a current-controlled current source (CCCS); and establishing a second negative feedback control loop by converting a drain voltage at the third node into the second current using a voltage-controlled current source (VCCS).

Claims

1. An envelope detector comprising: a common-mode source follower (CMSF) comprising a first source follower and a second source follower connected in parallel and configured to receive a RF (radio frequency) signal comprising a first voltage at a first node and a second voltage at a second node, respectively, and output a first current to a third node in accordance with a sum of a second current and a third current received via a fourth node; a current-controlled current source (CCCS) configured to receive the first current and output the third current; and a voltage-controlled current source (VCCS) configured to output the second current in accordance with a bias voltage and a drain voltage at the third node.

2. The envelope detector of claim 1, wherein the CCCS comprises a first PMOSFET (p-channel metal-oxide semiconductor field-effect transistor) configured in a diode-connect topology to convert the first current into the drain voltage and a second PMOSFET configured to output the third current to the fourth node in accordance with the drain voltage, a source of the first PMOSFET and a source of the second PMOSFET being connected to a power supply node.

3. The envelope detector of claim 2, wherein a gate of the first PMOSFET connects to a fifth node that is DC (direct-current) coupled to the third node via a resistor.

4. The envelope detector of claim 3, wherein the CCCS further comprises a capacitor configured to couple the fifth node to the power supply node.

5. The envelope detector of claim 1, wherein the VCCS comprises a NMOSFET (n-channel metal-oxide semiconductor field-effect transistor) configured to output the second current to the fourth node in accordance with a gate voltage at a gate node that is DC (direct current) coupled to the bias voltage via a gate resistor and AC (alternate current) coupled to the drain voltage via a coupling capacitor.

6. The envelope detector of claim 1 further comprising an AC (alternate current) coupling network configured to couple an incoming signal into the RF signal and set a DC (direct current) level of the RF signal to be equal to a common-mode voltage, the incoming signal comprising a third voltage and a fourth voltage.

7. The envelope detector of claim 6, wherein the AC coupling network comprises two capacitors configured to couple the third voltage and the fourth voltage to the first voltage and the second voltage, respectively, and two resistors configured to couple the common-mode voltage to the first voltage and the second voltage, respectively.

8. The envelope detector of claim 6 further comprising a bias generation network configured to receive a reference voltage and output the common-mode voltage in a manner such that a DC level of an output voltage at the fourth node is approximately equal to the reference voltage.

9. The envelope detector of claim 8, wherein the bias generation network comprises an additional CMSF that is a replica of the CMSF, an additional CCCS that is a replica of the CCCS, an additional VCCS that is a replica of the VCCS, and an operational amplifier.

10. The envelope detector of claim 9, wherein the operational amplifier outputs the common-mode voltage in accordance with a difference between a source voltage of the additional CMSF and the reference voltage.

11. A method of envelope detection comprising: receiving a RF (radio frequency) signal comprising a first voltage at a first node and a second voltage at a second node; using a common-mode source-follower (CMSF) comprising a first source follower and a second source follower connected in parallel and configured to receive the first voltage and the second voltage, respectively, and jointly output a first current to a third node in accordance with a sum of a second current and a third current received via a fourth node; establishing a first negative feedback control loop by converting the first current into the third current using a current-controlled current source (CCCS); and establishing a second negative feedback control loop by converting a drain voltage at the third node into the second current using a voltage controlled current source (VCCS).

12. The method of envelope detection of claim 11, wherein the CCCS comprises a first PMOSFET (p-channel metal-oxide semiconductor field-effect transistor) configured in a diode-connect topology to convert the first current into the drain voltage and a second PMOSFET configured to output the third current to the fourth node in accordance with the drain voltage, a source of the first PMOSFET and a source of the second PMOSFET being connected to a power supply node.

13. The method of envelope detection of claim 12, wherein a gate of the first PMOSFET connects to a fifth node that is DC (direct-current) coupled to the third node via a resistor.

14. The method of envelope detection of claim 13, wherein the CCCS further comprises a capacitor configured to couple the fifth node to the power supply node.

15. The method of envelope detection of claim 11, wherein the VCCS comprises a NMOSFET (p-channel metal-oxide semiconductor field-effect transistor) configured to output the second current to the fourth node in accordance with a gate voltage at a gate node that is DC (direct current) coupled to a bias voltage via a gate resistor and AC (alternate current) coupled to the drain voltage via a coupling capacitor.

16. The method of envelope detection of claim 11 further comprising using an AC (alternate current) coupling network to couple an incoming signal into the RF signal and set a DC (direct current) level of the RF signal to be equal to a common-mode voltage, the incoming signal comprising a third voltage and a fourth voltage.

17. The method of envelope detection of claim 16, wherein the AC coupling network comprises two capacitors configured to couple the third voltage and the fourth voltage to the first voltage and the second voltage, respectively, and two resistors configured to couple the common-mode voltage to the first voltage and the second voltage, respectively.

18. The method of envelope detection of claim 16 further comprising using a bias generation network to receive a reference voltage and output the common-mode voltage in a manner such that a DC level of an output voltage at the fourth node is approximately equal to the reference voltage.

19. The method of envelope detection of claim 18, wherein the bias generation network comprises an additional CMSF that is a replica of the CMSF, an additional CCCS that is a replica of the CCCS, an additional VCCS that is a replica of the VCCS, and an operational amplifier.

20. The method of envelope detection of claim 19, wherein the operational amplifier outputs the common-mode voltage in accordance with a difference between a source voltage of the additional CMSF and the reference voltage.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] FIG. 1 shows a schematic diagram of a prior art envelope detector.

[0011] FIG. 2 shows a schematic diagram of an envelope detector in accordance with an embodiment of the present disclosure.

[0012] FIG. 3 shows a schematic diagram of a bias generation network in accordance with an embodiment of the present disclosure.

[0013] FIG. 4 shows a flow diagram of envelope detection in accordance with an embodiment of the present disclosure.

DETAILED DESCRIPTION OF THIS DISCLOSURE

[0014] The present disclosure is directed to envelope detection. While the specification describes several example embodiments of the disclosure considered favorable modes of practicing the invention, it should be understood that the invention can be implemented in many ways and is not limited to the particular examples described below or to the particular manner in which any features of such examples are implemented. In other instances, well-known details are not shown or described to avoid obscuring aspects of the disclosure.

[0015] Persons of ordinary skill in the art understand terms and basic concepts related to microelectronics that are used in this disclosure, such as voltage, current, circuit node, signal, power supply, ground, bias voltage, DC (direct current), AC (alternate current), NMOSFET (n-channel metal oxide semiconductor field effect transistor), PMOSFET (p-channel metal oxide semiconductor field effect transistor), current source, operational amplifier, voltage-controlled current source, current-controlled current source, and source follower. Terms like these are used in a context of microelectronics, and the associated concepts are apparent to those of ordinary skills in the art and thus will not be explained in detail in this disclosure.

[0016] Those of ordinary skill in the art can recognize a resistor symbol, a capacitor symbol, and a MOSFET (metal-oxide semiconductor field effect transistor) symbol, for both PMOSFET and NMOSFET, and can identify a source terminal, a gate terminal, and a drain terminal of a MOSFET. Those of ordinary skills in the art can read schematics of a circuit comprising resistors, capacitors, NMOSFET, and PMOSFET, and do not need a verbose description about how one transistor, resistor, or capacitor connects with another in the schematics.

[0017] This present disclosure is disclosed in terms of an engineering sense. For instance, regarding two variables X and Y, when it is said that X is equal to Y, it means that X is approximately equal to Y, i.e., a difference between X and Y is smaller than a specified engineering tolerance. When it is said that X is zero, it means that X is approximately zero, i.e., X is smaller than a specified engineering tolerance. When it is said that X is substantially smaller than Y, it means that X is negligible with respect to Y, i.e., a ratio between X and Y is smaller than an engineering tolerance and therefore X is negligible when compared to Y.

[0018] Throughout this disclosure, V.sub.DD denotes a power supply node, and V.sub.SS denotes a ground node. Note that a ground node is a node at which a voltage level is substantially zero, and a power supply node is a node at which a voltage level is substantially stationary and higher than zero.

[0019] A circuit is a collection of a transistor, a capacitor, a resistor, and/or other electronic devices inter-connected in a certain manner to embody a certain function.

[0020] A network is a circuit or a collection of circuits configured to embody a certain function.

[0021] In this present disclosure, a circuit node is simply referred to as a node for short, as the meaning is clear from a context of microelectronics won't cause confusion.

[0022] In this present disclosure, a signal is a voltage of a variable level that can vary with time. A (voltage) level of a signal at a moment represents a state of the signal at that moment. A differential signal, or a signal in a differential embodiment, comprises a first voltage and a second voltage, and a difference in level between the first voltage and the second voltage represents a state of the differential signal.

[0023] A schematic diagram of an envelope detector 200 in accordance with an embodiment of the present disclosure is shown in FIG. 2. Envelope detector 200 receives a RF (radio frequency) signal that in a differential signal embodiment comprises two voltages V.sub.i+ and V.sub.i?, and outputs an output voltage V.sub.o, which is a detected envelope signal of the RF signal. Envelope detector 200 comprises: a common-mode source follower (CMSF) 210 configured to receive V.sub.i+ and V.sub.i? at a first node 201 and a second node 202, respectively, and outputs a first current I.sub.1 to a third node 203 in accordance with a sum of a second current I.sub.2 and a third current I.sub.3 received via a fourth node 204; a current-controlled current source (CCCS) 220 configured to receive the first current I.sub.1 from the third node 203 and output the third current I.sub.3 to the fourth node 204; and a voltage-controlled current source (VCCS) 240 configured to output the second current I.sub.2 in accordance with a bias voltage V.sub.b and a drain voltage V.sub.d of the CMSF 210 at the third node 203.

[0024] V.sub.i+ and V.sub.i? jointly embody a RF signal. In an embodiment, V.sub.i+ and V.sub.i? are complementary, i.e., when V.sub.i+ rises/falls by an amount, V.sub.i? will fall/rise by the same account. When V.sub.i+ reaches a peak, V.sub.i? will reach a valley, and vice versa. An envelope of the RF signal is defined by a peak of V.sub.i+ or a peak of V.sub.i?, whichever is higher, and detected and represented by V.sub.o, which is a voltage at the fourth node 204.

[0025] CMSF 210 comprises NMOSFET 211 and NMOSFET 212 connected in parallel and configured to receive V.sub.i+ and V.sub.i?, respectively, and jointly output I.sub.1 in accordance with a sum of I.sub.2 and I.sub.3. NMOSFET 211 and NMOSFET 212 both function as a source follower, wherein a source voltage follows a gate voltage. Since NMOSFET 211 and NMOSFET 212 share the same source voltage (which is V.sub.o) at the fourth node 204, whichever receives a higher gate voltage will dominate a voltage level of V.sub.o. As a result, V.sub.o will follow a higher voltage between V.sub.i+ and V.sub.i?, and a function of envelope detection is thus fulfilled.

[0026] A current-controlled current source (CCCS) is a circuit that converts an input current into an output current that is approximately proportional to the input current. CCCS 220 receives I.sub.1 (which is an output of CMSF 210) and outputs I.sub.3 (which is a part of a biasing current of CMSF 210 that is received via the fourth node 204) in an inverting manner, such that an increase (decrease) of I.sub.1 leads to a decrease (increase) of I.sub.3, thus causing a decrease (increase) of I.sub.1. A first negative feedback control loop is thus formed; the first negative feedback control loop can suppress a distortion of V.sub.o, thus allowing the envelope detector 200 to have low distortion.

[0027] As shown in FIG. 2, CCCS 220 comprises PMOSFET 221 and PMOSFET 222. PMOSFET 221 is configured in a diode-connect topology, wherein a drain is connected to a gate, to convert I.sub.1 into V.sub.d, which is a drain voltage of CMSF 210 at the third node 203. Due to the diode-connect topology, V.sub.d is also a gate voltage of PMOSFET 221. PMOSFET 222 and PMOSFET 211 have the same gate voltage V.sub.d and the same source voltage V.sub.DD and thus the same gate-to-source voltage, and a current-mirroring function is established, so that I.sub.3 is approximately proportional to I.sub.1 but of opposite sign. A current-controlled current source function is thus fulfilled. In an optional embodiment, a gate resistor 223 is inserted between the third node 203 and a fifth node 205, which connects to the gate of PMOSFET 221. Gate resistor 223 can cause the PMOSFET 221 to behave as an active inductor, compensating a parasitic capacitor at the third node 203 and speeding up CCCS 220. In a further optional embodiment, CCCS 220 further comprises a capacitor 224 inserted between the fifth node 205 and the power supply node V.sub.DD. Capacitor 224 can further enhance the active inductor behavior and speed up CCCS 220. That a diode-connected MOST with a gate resistor and a gate-to-source capacitor can form an active inductor is well known in the prior art and thus not further explained in detail.

[0028] A voltage controlled current source (VCCS) is a voltage-to-current conversion circuit configured to output an output current in accordance with a control voltage. VCCS 240 comprises NMOSFET 241, resistor 242, and capacitor 243. NMOSFET 241 outputs I.sub.2 in accordance with a control voltage V.sub.206 at a sixth node 206. The control voltage V.sub.206 comprises a static component received from V.sub.b via resistor 242 and a dynamic component received from V.sub.d via capacitor 243. A DC (direct-current) component of I.sub.2 is determined by V.sub.b, while an AC (alternate current) component of I.sub.2 is determined by V.sub.d. When V.sub.d rises (falls), V.sub.206 rises (falls), and consequently 12 and I.sub.1 decrease (increase), causing V.sub.d to fall (rise). A second negative feedback control loop is thus formed, further alleviating a distortion of V.sub.o.

[0029] In a further embodiment, the envelope detector 200 further comprises an AC (alternate current) coupling network 230 configured to couple two voltages V.sub.i+ and V.sub.i? into V.sub.i+ and V.sub.i?, respectively, wherein V.sub.i+ and V.sub.i? jointly embody an incoming signal in a differential embodiment. AC coupling network 230 comprising two capacitors 231 and 232 configured to provide AC (alternate current) coupling from V.sub.i+ and V.sub.i? to V.sub.i+ and V.sub.i?, respectively, and two resistors 233 and 234 configured to provide DC (direct current) coupling from a common-mode voltage V.sub.cm to V.sub.i+ and V.sub.i?, respectively. In an embodiment, a capacitance of capacitors 231 and 232 is substantially greater than a parasitic capacitance (not shown in figure but the concept is well understood by those of ordinary skill in the art) at nodes 201 and 202; this way, the AC coupling function of capacitors 231 and 232 can be effective. In an embodiment, a resistance of resistors 233 and 234 is substantially larger than an impedance of capacitors 231 and 232 at a frequency of the incoming signal; this way, resistors 233 and 234 can make a DC value of V.sub.i+ and V.sub.i? be equal to V.sub.cm without introducing an appreciable AC signal loss of the incoming signal, and consequently an amplitude of V.sub.i+ can be approximately equal to an amplitude of V.sub.i+, while an amplitude of V.sub.i? can be approximately equal to an amplitude of V.sub.i?.

[0030] In a further embodiment, a bias generation network 300 is used to generate the common-mode voltage V.sub.cm. As shown in FIG. 3, bias generation network 300 comprises CMSF 310 (comprising NMOSFET 311 and NMOSFET 312), CCCS 320 (comprising PMOSFET 321 configured in a diode-connect topology and PMOSFET 322), VCCS 340 (comprising NMOSFET 341), and an operational amplifier 330. In terms of circuit topology, CMSF 310 is the same as CMSF 210, CCCS 320 is the same as CCCS 220 (except that resistor 223 and capacitor 224 are removed, i.e., are replaced by a short circuit and an open circuit, respectively), VCCS 340 is the same as VCCS 240 (except that capacitor 243 and resistor 242 are removed, i.e., are replaced by an open circuit and a short circuit, respectively). Operational amplifier 330 outputs V.sub.cm in accordance with a difference between a reference voltage V.sub.ref and a source voltage Vs of CMSF 310. Operational amplifier 330 and CMSF 310 form a third negative feedback control loop to make Vs approximately equal to V.sub.ref. In an embodiment, CMSF 310, CCCS 320, and VCCS 340 are a replica of CMSF 210, CCCS 220, and VCCS 240 (except the removal of resistors and capacitors). In this case, a DC level of V.sub.o is approximately equal to Vs and thus approximately equal to V.sub.ref in the absence of incoming signal embodied by V.sub.i+ and V.sub.i?. This way, the DC level of V.sub.o can be controlled. Operational amplifiers are well known in the prior art and thus not described in detail. Operational amplifier 330 can be implemented using a variety of suitable circuits known in the prior art at a discretion of a circuit designer.

[0031] Envelope detector 200 offers certain advantages over the prior art envelope detector 100. First, it is highly insensitive to temperature and manufacturing process. When temperature and manufacturing process vary, characteristics of CMSF 210, CCCS 220, and VCCS 240 may vary. However, the first negative feedback control loop formed by CCCS 220 and the second negative feedback control loop formed by VCCS 240 can both help to improve an accuracy of envelope detection, provided their loop gains remain sufficiently high over temperature and manufacturing process variation. If a loop gain of a negative feedback control loop is, for instance, 40 dB, an error of an output of the loop gain may be typically approximately 1%. If the loop gain varies between 34 dB to 46 dB, for instance, due to temperature and manufacturing process variation, the error typically may vary approximately between 0.5% and 2%, which is still small. In other words, the negative feedback control loop can still ensure high accuracy and low distortion of V.sub.o despite temperature and manufacturing process variation. Second, crossover distortion can be eliminated, since at least one of V.sub.i+ and V.sub.i? can cause CMSF 210 to remain in an on-state, and a cross-over between an on-state and an off-state is avoided. Third, a high-speed envelope detection can be fulfilled. This is because CMSF 210 is a very high-speed circuit, wherein a delay is merely between a gate and a source of NMOSFET 211 and NMOSFET 212. The second negative feedback control loop formed by VCCS 240 is fast, because it only involves a gate-to-drain delay of NMOSFET 241. The first negative feedback control loop formed by CCCS 220 is not as fast, because it involves a current to voltage conversion of PMOSFET 221 and a gate-to-drain delay of PMOSFET 222. However, the optional resistor 223 and the optional capacitor 224 can speed up the current-to-voltage conversion of PMOSFET 221, thus speeding up the first negative feedback control loop.

[0032] As illustrated by a flow diagram shown in FIG. 4, a method of envelope detection in accordance with an embodiment of the present disclosure comprises: (step 410) receiving a RF (radio frequency) signal comprising a first voltage at a first node and a second voltage at a second node; (step 420) using a common-mode source-follower (CMSF) comprising a first source follower and a second source follower connected in parallel and configured to receive the first voltage and the second voltage, respectively, and jointly output a first current to a third node in accordance with a sum of a second current and a third current received via a fourth node; (step 430) establishing a first negative feedback control loop by converting the first current into the third current using a current-controlled current source (CCCS); and (step 440) establishing a second negative feedback control loop by converting a drain voltage at the third node into the second current using a voltage-controlled current source (VCCS).

[0033] Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the disclosure. Accordingly, the above disclosure should not be construed as limited only by the metes and bounds of the appended claims.