Millimeter-wave scalable PLL-coupled array for phased-array applications

Abstract

Techniques, systems and architectures for generating desired phase shifts in a phased array to control the directions of radiation in a wide range of angles are disclosed. Particularly, phased array architectures based on novel PLL-coupled phase shifting techniques for implementation in millimeter-wave (mm-wave) and sub-terahertz (sub-THz) operations range are described. In one aspect, a phased array including an array of unit cells is disclosed. In some embodiments, each unit cell in the array of unit cells includes a dual-nested PLL that is configured to effectuate phase locking and frequency locking to a reference signal from an adjacent unit cell. Moreover, each PLL includes control circuitry that can generate a wide range of phase shifts between adjacent unit cells to facilitate phased-array operations. Note that using the dual-nested PLL to generate a desired phase shift between adjacent radiating elements eliminates the use of conventional lossy phase shifters in the phased array.

Claims

1. A phased array using a phase-locked loop (PLL)-coupled structure, comprising: an array of unit cells, wherein each unit cell in the array of unit cells includes a radiating element; wherein each unit cell in the array of unit cells includes a PLL having a dual-nested structure that is configured to effectuate phase locking and frequency locking to a reference signal from an adjacent unit cell in the array; wherein each PLL includes a local voltage-controlled oscillator (VCO) that is phase locked and frequency locked with an adjacent VCO in an adjacent PLL in an adjacent unit cell in the array of unit cells; and wherein each PLL includes control circuitry that controls a phase shift between the local VCO and the adjacent VCO to facilitate phased-array operations.

2. The phased array of claim 1, wherein the dual-nested structure in each PLL in each unit cell includes: a fast loop that provides frequency locking between the local VCO and the adjacent VCO: and a slow loop that provides phase locking between the local VCO and the adjacent VCO.

3. The phased array of claim 2, wherein the slow loop includes adjustable delay circuitry that generates the phase shift between the local VCO and the adjacent VCO based on a control voltage.

4. The phased array of claim 3, wherein using the adjustable delay circuitry in the dual-nested PLL to generate the phase shift eliminates using a conventional phase shifter in the unit cell.

5. The phased array of claim 2, wherein the slow loop includes a mixer which is coupled between the local VCO and the adjacent VCO, and functions as a phase/frequency detector that measures a phase difference between the local VCO and the adjacent VCO.

6. The phased array of claim 5, wherein the mixer is configured with a symmetrical topology for receiving differential signals from both the local VCO and the adjacent VCO, thereby avoiding long signal routings to the mixer at high operating frequencies.

7. The phased array of claim 1, further comprising a reference VCO coupled to the array of unit cells to provide a frequency reference for all unit cells in the array of unit cells based on an external DC control signal that controls the reference VCO.

8. The phased array of claim 1, wherein the array of unit cells comprises a two-dimensional array of unit cells.

9. The phased array of claim 8, wherein the two-dimensional array of unit cells includes a first row of unit cells arranged along an X-direction; and wherein each unit cell in the first row of unit cells receives a first control voltage that controls a first phase shift between a first VCO of a first PLL and a second VCO of a second PLL within a pair of adjacent unit cells in the first row of unit cells, and wherein the first phase shift determines a first radiation angel for the radiating elements in the first row of unit cells in the X-direction.

10. The phased array of claim 9, wherein the first control voltage is applied to the adjustable delay circuitry within each of the first row of unit cells.

11. The phased array of claim 9, wherein the two-dimensional array of unit cells additionally includes a second row of unit cells arranged along the X-direction; and wherein the first row of unit cells and the second row of unit cells are coupled through a coupling unit cell located at an end of the second row of unit cells.

12. The phased array of claim 11, wherein each unit cell in the first row of unit cells and a corresponding unit cell in the second row of unit cells are aligned along a Y-direction perpendicular to the X-direction; and wherein the coupling unit cell receives a second control voltage which controls a second phase shift between the first row of unit cells and the second row of unit cells, and wherein the second phase shift determines a second radiation angel for the radiating elements in both the first and second rows of unit cells in the Y-direction.

13. The phased array of claim 12, wherein the second control voltage is applied to the adjustable delay circuitry within the coupling unit cell.

14. The phased array of claim 12, wherein each unit cell other than the coupling unit cell in the second row of unit cells receives the first control voltage which determines the first radiation angel for the second row of unit cells in the X-direction.

15. The phased array of claim 1, wherein unit cells in the array of unit cells are continuously coupled to each other through the PLL of each unit cell in the array of unit cells, and wherein the continuously-coupled PLLs in the array of unit cells form a PLL-coupled structure.

Description

DESCRIPTION OF THE FIGURES

(1) FIG. 1 shows a conventional phase array which employs phase shifters to achieve the desired phase shift between adjacent radiating elements.

(2) FIG. 2 shows a block diagram of a coupled-phase-locked loop (PLL) array which can be used for phase shifting and beam steering in a phased array.

(3) FIG. 3 shows the block diagram of a proposed dual-nested PLL 300 for use in a PLL-coupled array in accordance with some embodiments.

(4) FIG. 4 shows a block diagram of a PLL-coupled-array architecture 400 which employs the proposed dual-nested PLL 300 in accordance with some embodiments.

(5) FIG. 5 presents a proposed scalable phased array implemented with the proposed PLL-coupled phase shifter in accordance with some embodiments.

(6) FIG. 6 shows the schematic of a pulse width modulation (PWM) circuit as an exemplary implementation of the proposed PWM module in the proposed dual-nested PLL for controlling the phase shift within the proposed phased array in accordance with some embodiments.

(7) FIG. 7 shows a detailed circuit diagram of the disclosed dual-nested PLL using the proposed PWM circuit for phased array applications in accordance with some embodiments.

(8) FIG. 8 shows a detailed circuit diagram of the disclosed dual-nested PLL implemented in a two-element PLL-coupled system for mm-wave phased-array application in accordance with some embodiments.

(9) FIG. 9 shows a linear model of the proposed dual-nested PLL and PLL-coupled array for analyzing the operation and stability of the control loop in accordance with some embodiments.

(10) FIG. 10 shows the noise sources used to perform the noise analysis of the disclosed dual-nested PLL in accordance with some embodiments.

(11) FIG. 11 shows the circuit topology of an exemplary voltage-controlled oscillator (VCO) which is used in the disclosed PLL-coupled array system at 117 GHz in accordance with some embodiments.

(12) FIG. 12A shows the measured and simulated tuning range of the stand-alone VCO of FIG. 10 at the fundamental frequency in accordance with some embodiments.

(13) FIG. 12B shows the measured down-converted output spectrum of the reference VCO in accordance with some embodiments.

(14) FIG. 13 shows schematic of an exemplary implementation of the differential mixer used in the disclosed dual-nested PLL as a phase/frequency detector in accordance with some embodiments.

(15) FIG. 14 shows the simulated output voltage of the mixer as a function of phase difference between the reference and slave VCOs with the slope of K.sub.PD in accordance with some embodiments.

(16) FIG. 15 shows the schematic of an exemplary implementation of the differential delay cell in accordance with some embodiments.

(17) FIG. 16 shows a die micrograph of the 117-GHz PLL-coupled array system in accordance with some embodiments.

DETAILED DESCRIPTION

(18) The following description is presented to enable any person skilled in the art to make and use the disclosed embodiments, and is provided in the context of one or more particular applications and their requirements. Various modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the scope of those that are disclosed. Thus, the present invention or inventions are not intended to be limited to the embodiments shown, but rather are to be accorded the widest scope consistent with the disclosure.

(19) This disclosure provides various techniques, systems and architectures for generating desired phase shifts in a phased array to control the directions of radiation in a wide range of angles. Particularly, phased array architectures based on novel phase-locked-loop-coupled (PLL-coupled) phase shifting techniques for implementation in millimeter-wave (mm-wave) and sub-terahertz (sub-THz) operations range are disclosed. In some embodiments, a proposed phased array is configured to use the proposed dual-nested PLLs to generate a wide range of phase shifts between adjacent radiator elements, thereby eliminating the use of conventional lossy phase shifters in the proposed phased array.

(20) The proposed dual-nested PLL architecture includes the two nested loops which operate coherently and concurrently to both lock the frequency and the phase, and create the required phase shift between a local voltage-controlled oscillator (VCO) and a reference VCO. More specifically, the two nested loops include both a fast loop configured to enable frequency locking between two VCOs of the two adjacent radiator elements; and a slow loop configured to effectuate phase locking between the two VCOs of the two adjacent radiator elements. Moreover, the fast loop and the slow loop work together to create a type-II PLL which can provide the required phase shift between the two VCOs,

(21) By eliminating the phase shifters from the phased array architecture entirely, the power loss and power consumption in the proposed phased array can be significantly reduced. As a result, the proposed phased array architecture can be used to create phased arrays of desirable sizes by simply adding more unit cells, i.e., the radiating elements in each dimension of the architecture. This up-scaling of a phased array would not be possible when conventional phase shifters are used because the power consumption would significantly limit the achievable power gain. In addition, in PLL-coupled array architecture, the required phase shift can be generated by changing only an analog control voltage. Furthermore, implementation of the disclosed dual-nested PLL employs symmetrical mixer topology and differential VCOs signaling to avoid long signal routings at high-frequencies, thereby making the system scalable for mm-wave and sub-THz phased arrays with a large number of elements.

(22) As mentioned in the background section, conventional phased-array designs using phase shifters for beam-steering/scanning suffer from power losses and high power consumptions issues. Injection-locked or coupled oscillators techniques for phased array designs offered phase shift solutions without using phase shifters, but nonetheless suffer from issues such as narrow locking range and phase fluctuation that lead to beam-steering errors. To mitigate the problems of phase fluctuation and error, a phase-shift technique referred to as coupled phase-locked loop (PLL) has been proposed.

(23) FIG. 2 shows a block diagram of a coupled-PLL array 200 that can be used for phase shifting and beam steering in a phased array. In the architecture of FIG. 2, voltage-controlled oscillators (VCOs) are locked to a reference VCO (VCO.sub.ref) and a control voltage, V.sub.ctrl is used to generate an equal phase shift between the adjacent VCOs. This coupled PLL technique can achieve wider phase-shift-variation and locking ranges than the aforementioned injection-locked and coupled oscillator arrays and at the same time reduce the phase fluctuations and beam-steering errors. However, as can be observed from FIG. 2, the PLLs in coupled PLL array 200 use conventional phase detectors (PDs), which are intended to operate in low frequencies. Indeed, designing a wide-band PLL with its VCO, PD, and frequency-divider blocks all operating over a wide band at mm-wave/sub-THz frequencies can be extremely difficult. As such, the coupled PLL array 200 are not suitable for mm-wave/sub-THz frequency operations. Hence, there is a motivation to create a new PLL architecture which can be used in a coupled-PLL array for mm-wave/sub-THz frequency operations.

(24) FIG. 3 shows the block diagram of a proposed dual-nested PLL 300 for use in a PLL-coupled array in accordance with some embodiments. As can be seen in FIG. 3, PLL 300 includes a VCO 302, a mixer 304, a first low pass filter LPF1, a second low pass filter LPF2, and a proposed pulse width modulation (PWM) module 306, all of the above modules are coupled to each other in the manner shown. Note that in the architecture of the proposed PLL 300, PWM module 306 takes the place of either a conventional phase-frequency detector (PFD)/charge pump (CP) block or a conventional phase detector (PD)/charge pump (CP) block to generate VCO control signals. As shown in FIG. 3, the proposed PWM module 306 further includes a phase delay module (PDL) 308, a phase-frequency detector (PFD) 310, and a charge pump (CP) 312, which are coupled and functioning in the sequence as shown. As will be described in more detail below, by using the proposed PWM module 306 to generate desired phase shift in place of traditional PFD/CP or PD/CP blocks, the proposed dual-nested PLL 300 can be used in a PLL-coupled array in place of conventional PLLs to enable mm-wave/sub-THz frequency operations.

(25) Note that dual-nested PLL 300 receives a reference input signal V.sub.ref(f.sub.0) from the bottom right and outputs a stable voltage signal V.sub.PLL (f.sub.0) from VCO 302. In some embodiments, the proposed dual-nested PLL 300 operates to lock both the frequency and phase of VCO 302 output V.sub.PLL(f.sub.0) to the frequency and phase of reference input V.sub.ref(f.sub.0). Moreover, the proposed dual-nested PLL 300 is also configured to generate a predetermined amount of phase shift between V.sub.PLL (f.sub.0) and V.sub.ref (f.sub.0). When dual-nested PLL 300 is used to construct a PLL-coupled structure and/or the proposed phased-array structures as described below, reference input V.sub.ref(f.sub.0) is typically the output voltage from a reference VCO adjacent to VCO 302, wherein VCO 302 and the reference VCO reside respectively within two adjacent unit cells in a proposed phased array. In these applications, VCO 302 is referred to as the slave VCO with respect to the reference VCO, and VCO 302 and reference VCO are identical VCOs. Note that the proposed dual-nested PLL 300 can be used in applications other than the phased arrays. When used in other applications, input signal V.sub.ref(f.sub.0) can be received from other types of VCOs and other types of PLLs different from dual-nested PLL 300 and VCO 302.

(26) Note that input signal V.sub.ref(f.sub.0) is first received by mixer 304, which simultaneously receives output V.sub.PLL(f.sub.0) of VCO 302. Note that mixer 304 functions as a phase detector and measures the phase difference between reference signal V.sub.ref(f.sub.0) and V.sub.PLL(f.sub.0). In some embodiments, both signals V.sub.ref(f.sub.0) and V.sub.PLL(f.sub.0) are differential signals. Mixer 304 outputs a voltage signal V.sub.O,MIX which is a function of both the phase difference between V.sub.ref(f.sub.0) and V.sub.PLL(f.sub.0), and a sensitivity of mixer 304. Design of mixer 304 is described below in more detail.

(27) Note that the proposed dual-nested PLL 300 includes two distinct loops, namely, a fast loop 320 and a slow loop 322, wherein the fast loop 320 in “nested” inside slow loop 322. For this reason, the proposed PLL 300 is referred to as a dual-nested PLL. A unique feature of dual-nested PLL 300 is that fast loop 320 and slow loop 322 work collectively to lock the frequency and phase of V.sub.PLL(f.sub.0) to the reference signal V.sub.ref(f.sub.0).

(28) More specifically, fast loop 320 operates to quickly lock the frequency of V.sub.PLL(f.sub.0) to the frequency f.sub.0 of reference signal f.sub.0. In some embodiments, fast loop 320 is composed of VCO 302 and mixer 304. As mentioned above, mixer 304 functions as a phase detector and measures the phase difference between V.sub.PLL(f.sub.0) and V.sub.ref(f.sub.0). In some embodiments, mixer 304 can include an internal LPF which is used to filter AC signals to some extent. Note that fast loop 320 also includes a capacitor C.sub.p that is coupled between an output of mixer 304 and the control input to VCO 302. Capacitor C.sub.p can be configured to block the DC component in the mixer's output V.sub.O,MIX while allowing the high-frequency component in the mixer's output V.sub.O,MIX to pass through. The value of C.sub.p can be selected based on the operation frequency of PLL 300. In some embodiments, a higher C.sub.p value can generally improve the overall PLL performance. While the specific embodiment of dual-nested PLL 300 uses capacitor C.sub.p to perform the high-pass filter (HPF) function, other embodiments of a HPF, e.g., an active HPF can be used in place of capacitor C.sub.p to perform the intended functionality in fast loop 320 and dual-nested PLL 300 without departing from the scope of the present disclosure.

(29) In fast loop 320, as the loop is locking, the phase change is rapid and therefore results in a high-frequency component from the mixer 304's output. This high-frequency component of the mixer's output signal V.sub.O,MIX, which results from the phase difference between V.sub.PLL(f.sub.0) and V.sub.ref(f.sub.0) is fed to and used to adjust the tuning voltage V.sub.C of VCO 302 through capacitor C.sub.p. As mentioned above, capacitor C.sub.p in the fast loop also blocks the slow moving/DC component V.sub.Φ in the mixer's output signal V.sub.O,MIX. Fast loop 320 behaves as a type-I PLL to achieve rapid frequency locking by coarse-tuning the tuning voltage V.sub.C. However, due to the limited loop gain of fast loop 320, a residual phase error between V.sub.PLL(f.sub.0) and V.sub.ref(f.sub.0) remains when the frequency locking is complete. At this point, slow loop 322 operates to bring the residual phase error to zero by fine-tuning the tuning voltage V.sub.C of VCO 302.

(30) As can be seen in FIG. 3, slow loop 322 comprises VCO 302, mixer 302, both low pass filters LPF1, LPF2, and PWM module 306, which further includes PDL 308, PFD 310, and CP 312. Mixer 304 output V.sub.O,MIX passes through LPF2, which eliminates high-frequency components in mixer's output V.sub.O,MIX. As a result, the DC component of V.sub.O,MIX is kept, which is shown as V.sub.Φ in FIG. 3. V.sub.Φ is directly coupled to PDL 308 to control an amount of phase delay generated by a group of delay cells inside PDL 308. Slow loop 322 begins to correct a phase error between two delay paths in PDL 308 by fine-tuning the tuning voltage V.sub.C of VCO 302. After a number of iterations, the residual phase error is corrected and forced to zero as a result of an inherent infinite DC loop gain of slow loop 322.

(31) As can be seen in FIG. 3, PWM module 306 in the proposed dual-nested PLL 300 is configured to receive a phase shift control signal Vps. Similarly to V.sub.Φ, V.sub.PS is directly coupled to PDL 308 to control an amount of phase delay generated by another group of delay cells inside PDL 308. As will be described in more detail below in conjunction with the proposed PLL-coupled array and the proposed phased array systems, V.sub.PS (which becomes V.sub.steer) in conjunction with V.sub.Φ can be used to change a phase shift between VCO 302 output V.sub.PLL and reference VCO input V.sub.ref. However, if a phase shift between V.sub.PLL and V.sub.ref is not required, V.sub.PS can be set to any voltage value and the proposed dual-nested PLL 300 can perform the conventional PLL function of locking V.sub.PLL to reference input V.sub.ref.

(32) In some embodiments, the proposed dual-nested PLL 300 additionally receives a control clock signal V.sub.DL (which is received by PDL 308 in PWM module 306) to control an optimal operating speed of slow loop 322 to lock the phase. Note that if slow loop 322 works too fast, the loop can become unstable and unable to lock the phase. On the other hand, if slow loop 322 works too slowly, it will take a long time for slow loop 322 to settle and lock the phase. Note that slow loop 322 by itself is generally not stable. However, the stability of slow loop 322 is achieved when slow loop 322 works in parallel with fast loop 320. When both loops operate concurrently, slow loop 322 becomes a type-II PLL which is capable of locking both phase and frequency. In conclusion, fast loop 320 rapidly locks the frequency of V.sub.PLL(f.sub.0) with V.sub.ref(f.sub.0), whereas slow loop 322 corrects the phase difference between the V.sub.PLL(f.sub.0) with V.sub.ref(f.sub.0).

(33) Note that the proposed dual-nested PLL 300 can be used in a PLL-coupled array inside a phased-array system to perform the phase shifting functionalities. FIG. 4 shows a block diagram of a PLL-coupled-array architecture 400 which employs the proposed dual-nested PLL 300 in accordance with some embodiments. As can be seen in FIG. 4, PLL-coupled array 400 includes a row of coupled PLLs, namely PLL 402-1, PLL 402-2, . . . , PLL 402-N. In particular, each of the N PLLs 402-i (i=1 to N) is implemented with the proposed dual-nested PLL 300 described in conjunction with FIG. 3, but without VCO 302. Instead, the VCO associated with each PLL 402-i is shown in PLL-coupled array 400 directly coupled to PLL 402-i and the adjacent PLL 402-(i+1). For example, VCO.sub.1, which is the local VCO for PLL 402-1, is coupled to both PLL 402-1 and PLL 402-2. Similarly, VCO.sub.2, which is the local VCO for PLL 402-2, is coupled to both PLL 402-2 and PLL 402-3, and so on. As such, each PLL 402-i and its associated VCO, form unit of the proposed dual-nested PLL 300, e.g., dual-nested PLL unit 404-1 and PLL unit 404-N encapsulated inside respective dashed-line boxes. Each of the dual-nested PLL unit 404-i (i=1 to N) further receives a reference input signal from the adjacent VCO.sub.i-1 inside the adjacent dual-nested PLL unit 404-(i−1), except for the first dual-nested PLL unit 404-1, which receives its reference input signal from an independent reference source VCO.sub.ref.

(34) Note that compared with coupled-PLL array 200, PLL-coupled-array architecture 400 replaces each PLL unit in coupled-PLL array 200 with the disclosed dual-nested PLL 300. Moreover, each dual-nested PLL unit 404-i in PLL-coupled-array architecture 400 receives a common phase shift control signal V.sub.ctrl_phase. This represents another distinction between PLL-coupled array 400 and PLL-coupled array 200, wherein the latter does not include a common control signal for all PLL units. Note that PLL-coupled-array architecture 400 can be used to implement a constant phase shift among an array of circuit elements, such as an array of radiator elements. We will now describe using the disclosed PLL-coupled-array architecture 400 and the disclosed dual-nested PLL 300 to implement various phased array designs suitable for mm-wave/sub-THz frequency operations. In these implementations, the common control signal V.sub.ctrl_phase becomes the common beam-angel control signals V.sub.steer,x and V.sub.steer,x.

(35) FIG. 5 presents a proposed scalable phased array 500 implemented with the proposed PLL-coupled phase shifter in accordance with some embodiments. As can be seen in FIG. 5, phased array 500 is composed of a network (e.g., 4×4) of independently radiating elements (also referred to as “unit cells,” or “cells” hereinafter). As shown in FIG. 5, a single radiating element/unit cell in the proposed scalable phased array 500 is further composed of a VCO 502, a mixer 504, a pulse width modulator (PWM) 506, and an antenna 508. For example, the radiating element at the bottom left of phased array 500 is composed of VCO 502-1, a mixer 504-1, PWM 506-1, and antenna 508-1, etc. Note that collectively VCO 502, mixer 504, and PWM 506 inside each radiating element/unit cell can be implemented with the proposed dual-nested PLL 300, which is referred to as PLL 510-1, PLL 510-2, PLL 510-3, etc. inside each dashed-line boxes in array 500. In the proposed phased array 500, an external control voltage V.sub.Cref, which is a DC signal, is used to set the frequency of reference VCO 512, and as such, determining the frequency for all other VCOs in phased array 500 and the overall operation frequency of phased array 500. Depending on the target application, reference VCO 512 of phased array 500 can be locked by a separate traditional PLL to reduce the variations in the operation frequency.

(36) Note that the proposed phased array 500 has implemented the proposed PLL-coupled-array architecture 400 described in conjunction with FIG. 4. More specifically, each VCO inside a given unit cell inside the proposed phased-array 500 is phase/frequency locked to the neighboring VCO inside the adjacent unit cell using the proposed PLL architecture of the given unit cell. In other words, each dual-nested PLL, e.g., PLL 510-2, inside a given unit cell independently generates the required phase for the neighboring VCO inside the adjacent unit cell/PLL, e.g., PLL 510-3. Note that this phase-shift generation technique in the proposed phased array 500 is in clear contrast to conventional phase-shifter-based phased arrays, which use a local phase shifter within a unit cell to generate the desired phase shift for the signal generated by the local VCO within the same unit cell.

(37) Note that the proposed phased array 500 is configured to steer/scan the radiation beam independently in the X- and Y-directions. As can be seen in FIG. 5, the 2-dimensional array of unit cells in phased array 500 is actually formed from a chain of unit cells configured in the proposed PLL-coupled architecture 400. To form the rows and columns in phased array 500, the chain of unit cells is arranged in multiple rows and columns (e.g., 4 rows and 4 columns in array 500), wherein two adjacent rows in array 500 are coupled through a unit cell (i.e., unit cells 520, 522, and 524), which connects the two adjacent rows. Unit cells 520, 522, and 524 are also referred to as Y-control unit cells because they are the only unit cells which receive Y-control signal V.sub.steer,y. For clarity, indicator arrows are used in FIG. 5 pointing to 4 rows, namely, R1, R2, R3, and R4 in array 500. It can be observed that all VCOs and antennas of the unit cells in a given row (R1-R4) in phased array 500 are arranged to have substantially the same Y-location/coordinate; wherein all VCOs and antennas of the unit cells in a given column in phased array 500 (e.g., in unit cells 520 and 524) are arranged to have substantially the same X-location/coordinate.

(38) More specifically, each unit cell/PLL in phased array 500 receives an X-control signal V.sub.steer,x through the corresponding PWM module, except for row-connecting unit cells, i.e., Y-control unit cells 520, 522, and 524. For example, all unit cells in the bottom row R1 in phased array 500 receive the X-control signal V.sub.steer,x. In some embodiments, by controlling X-control signal V.sub.steer,x, an equal amount of phase shift between adjacent VCOs/unit cells within each row in the X-direction is produced. In other words, a phase shift between each pair of unit cells in a given row in phased array 500 can be modified by adjusting V.sub.steer,x, resulting in the beam/radiation steering/scanning in the X direction.

(39) Note that each Y-control unit cell 520, 522, and 524 receives Y-control signal V.sub.steer,y through the corresponding PWM module. V.sub.steer,y is configured to create a constant phase shift between rows in phased array 500. In some embodiments, only one Y-control unit cell/PLL is needed to change the phase shift from one row (e.g., R1) to the adjacent row (e.g., R2) in the Y-direction. In other words, if two corresponding unit cells in two adjacent rows (e.g., the unit cell corresponding to PLL 510-4 in row R1 and corresponding unit cell 520 in row R2) have a given phase shift in the Y-direction with respect to each other, then the other corresponding pair of cells having the same X-coordinates in these two adjacent rows (e.g., the unit cell corresponding to PLL 510-3 in row R1 and corresponding unit cell 530 in row R2) will automatically have the same phase shift in the Y-direction as well. Hence, by controlling V.sub.steer,y on each Y-control unit cell, the Y-direction phase shift between two adjacent rows in phased array 500 can be modified, resulting in the beam/radiation steering/scanning in Y-direction. Consequently, wideband beam steering in two dimensions can be achieved in the proposed phased array 500 by programming V.sub.steer,x and V.sub.steer,y control signals. Although not explicitly shown in FIG. 5, each unit cell in phased array 500 additionally receives low-frequency control signal at frequency f.sub.DL (e.g., 88 MHz in some exemplary designs). We will discuss this low-frequency control signal in more detail below in conjunction with FIGS. 6 and 7.

(40) Note that while the exemplary phased array 500 has a 4×4 dimension, the topology of the proposed phased array 500 can be readily extended in both X and Y-dimensions, either independently or equally, to any desired size. Moreover, the numbers of unit cells in rows and columns in a proposed phased array can be different from each other. In other words, some embodiments of proposed phased array can have dimensions of M×N, wherein M≠N. However, in practice, the array size may be limited by the physical implementation challenges on the chip. For example, the supply voltage is typically provided to the circuit through bond wires, and different unit cells within a given phased array can have different wiring paths to the supply pads. Hence, and because of the sheet resistance, different unit cells may experience different supply voltages. This discrepancy in supply voltages can result in different self-resonance frequencies among different VCOs. In an extreme case, the above discrepancy and other possible mismatches can affect the locking strength of the phased array. One solution to the above problem is to design a highly symmetric layout for the phased-array circuit. Moreover, unwanted couplings between unit cells in an array, such as coupling through antennas and substrate, need to be minimized. In some embodiments, these unwanted couplings can be significantly reduced by using shielding antennas and other isolation techniques.

(41) FIG. 6 shows the schematic of a PWM circuit 600 as an exemplary implementation of the proposed PWM module in the proposed dual-nested PLL 300 for controlling the phase shift within the proposed phased array 500 in accordance with some embodiments. Note that because PWM circuit 600 operates inside the proposed dual-nested PLL 300, PWM circuit 600 should be understood in the scope of the proposed dual-nested PLL 300. Specifically, PWM circuit 600 includes a detailed implementation 608 of PDL (Phase Delay Module) 308 within PWM 306 in the proposed dual-nested PLL 300. As can be seen in FIG. 6, PDL 608 is composed of two parallel and identical delay paths, wherein each delay path of the two delay paths further includes two serial stages of delay cells. In some embodiments, the delay cells in each stage of the two-stage delay cells are implemented with voltage-controlled delay lines. Note that while the embodiment of PDL 608 includes two stages of delay cells, other embodiments of the PWM module in the proposed dual-nested PLL can be configured with a phase delay module (PDL) having fewer stages (e.g., a single stage) or more stages (e.g., three or four stages) of serially-coupled delay cells without departing from the present scope. In some embodiments, the number of stages of delay cells in a given PDL may be determined based on a range of phase shift required by a particular application.

(42) During a phased-array operation, PWM circuit 600 receives a reference clock signal referred to as V.sub.DL. In some embodiments, V.sub.DL is a low frequency clock having a frequency f.sub.DL. As shown in FIG. 6, V.sub.DL is fed to the first stage of the delay cells in PDL 608 and is used to control the speed of slow loop 322. As described above in conjunction with FIG. 3, f.sub.DL is chosen carefully so that slow loop 322 in the proposed dual-nested PLL 300 operates at optimal speed to lock the phase. If f.sub.DL is set too high, then slow loop 322 operates very fast and the loop becomes unstable and cannot lock the phase. On the other hand, if f.sub.DL is set too low, then slow loop 322 operates very slowly and it will take a long time for slow loop 322 to settle and lock the phase.

(43) As previously described in conjunction with FIG. 3, PWM circuit 600 receives a DC phase error signal V.sub.Φ from LPF2 in the slow loop, which is used as the first control input to the lower delay path of the two-stage PDL 608. As described in conjunction with FIG. 5, depending on the type of unit cells the PWM circuit 600 is used for, PWM circuit 600 also receives one of the two steering control signals V.sub.steer,x and V.sub.steer,y, which is collectively referred to as V.sub.steer in PWM circuit 600. As shown in FIG. 6, complementary to error signal V.sub.Φ, control signal V.sub.steer is used as the second control input to the upper delay path of the two-stage PDL 608. Hence, V.sub.Φ controls the delay of the lower delay cells in PDL 608, whereas V.sub.steer controls the delay of the upper delay cells in PDL 608.

(44) Note that if V.sub.Φ and V.sub.steer are different from each other, then the upper and lower delay paths in PDL 608 output two delayed V.sub.DL signals with different delays, as illustrated by the two exemplary signal waveforms having a phase difference of ΔV.sub.Φ1,2 between PDL 608 and PFD 610. In other words, the input signal V.sub.DL would reach PFD 610 with different delays. Phase difference ΔV.sub.Φ1,2 is then detected by PFD 610. As a result, charge pump CP 612 starts injecting or pulling current to or from LPF1 in the proposed dual-nested PLL 300. Consequently, the control voltage V.sub.C of VCO 302 changes to adjust the phase difference between VCO 302 output V.sub.PLL and reference VCO input V.sub.ref. In some embodiments, PFD 610 and CP 612 can be implemented with any phase-frequency detector and charge pump now known or later developed.

(45) Note that when the slow loop 322 eventually locks, a stable condition is reached and V.sub.Φ is forced to be equal to V.sub.steer to introduce the same delay to the two delay paths of signals fed to PFD 610. As a result, control signal V.sub.C becomes a fixed voltage and the output of VCO 302 is phase-locked to the reference VCO input. However, before the phase is locked, the PDL/PFD/CP block generates pulses whose duration is proportional to the phase difference ΔV.sub.Φ1,2 between the two delay paths of the reference input V.sub.DL. In other words, the PDL/PFD/CP block inside PWM circuit 600 performs pulse width modulation (PWM), as the name for the PWM module 306 indicates.

(46) Based on the above analysis, it becomes readily understood that a predetermined phase shift between PLL 300 output V.sub.PLL and PLL 300 reference input V.sub.ref in FIG. 3 can be achieved by simply changing the value of control input V.sub.steer. The loop dynamic of PLL 300 eventually forces V.sub.Φ to be equal to V.sub.steer. Hence, a different value of V.sub.steer means a different phase shift is generated between V.sub.PLL and V.sub.ref. Note that the phase shifting/locking operation of the disclosed dual-nested PLL is inherently wideband as long as the associated loop gain is constant. Consequently, the bandwidth of the phase shifting operation of the disclosed dual-nested PLL can be increased by keeping the loop gain constant over a wider range of frequencies. It should be noted that without the disclosed PDL 308/608, the proposed PWM 306 becomes a conventional phase detector where a conventional PFD is used for phase and frequency detection. However, without PDL 308, the proposed phase tracking and locking separated from the frequency locking would not be possible at the intended mm-wave/sub-THz operation range.

(47) FIG. 7 shows a detailed circuit diagram 700 of the disclosed dual-nested PLL 300 using PWM circuit 600 for phased array applications in accordance with some embodiments. As can be seen in FIG. 7, dual-nested PLL 700 includes two distinct/nested loops, namely, a fast loop 720 and a slow loop 722. The two loops work together to lock the slave VCO 702 of dual-nested PLL 700 to the reference VCO 750. Note that reference VCO 750 is not part of dual-nested PLL 700, but can be a local VCO of an adjacent dual-nested PLL in a PLL-coupled array, wherein the PLL-coupled array can be a phased array. As has been described above, mixer 704 is used a phase/frequency detector and captures the phase difference between slave VCO 702 and reference VCO 750. Note that FIG. 7 shows two arrows between each of the two VCOs and mixer 704, indicating both of the VCO signals feeding into mixer 704 are differential signals

(48) As has been described above, fast loop 720 which includes slave VCO 702 and mixer 704, works as a type-I PLL. Mixer 704 can further include a built-in low pass filter eliminate certain high-frequency components of the mixer output signal. The high-frequency component of the mixer's output signal which results from the phase difference between the two VCOs is fed to the control voltage V.sub.Cslave of slave VCO 702 through capacitor C.sub.p. Fast loop 720 as a type-I PLL can lock the frequency of slave VCO 702 to reference VCO 750, but cannot lock the phase of the slave VCO to the phase of the reference VCO. As a result, a residual phase error remains between two VCOs which is corrected by slow loop 722.

(49) As has been further described above, slow loop 722 contains mixer 704, delay cells 708, PFD 710, charge pump 712 and LPF1. The output of mixer 704 passes through the second LPF2, which obtains the DC component of the mixer's output V.sub.Φ. V.sub.Φ controls the delay of the lower delay cells 708 while V.sub.steer controls the delay of the upper delay cells 708. If V.sub.Φ and V.sub.steer are different, then the DL input signal 740 reaches PFD 710 with different delays following the upper path and the lower path of delay cells 708, which results in a ΔV.sub.Φ1,2 phase difference between the two paths. This phase difference is then detected by the PFD 710, which causes charge pump 712 to start injecting or pulling current to or from LPF1. As a result, the control voltage V.sub.Cslave of slave VCO 702 changes. In the stable condition, V.sub.Cslave is a fixed voltage and V.sub.Φ and V.sub.steer are equal to each other. Slow loop 722 operates as a type-II PLL that can lock both the frequency and the phase of slave VCO 702 to V.sub.Cref. Slow loop 722 is an unstable PLL by itself, but becomes a stable loop when works together with fast loop 720. Hence, fast loop 720 operates to quickly bring the frequencies of the two VCO together, while slow loop 722 corrects the residual phase difference between the two VCOs.

(50) FIG. 8 shows a detailed circuit diagram 800 of the disclosed dual-nested PLL 300 implemented in a two-element PLL-coupled system for mm-wave phased-array application in accordance with some embodiments. As can be seen in FIG. 8, the implemented two-element PLL-coupled system 800 contains a slave VCO 802 and an identical reference VCO 850, which provides frequency and phase references for the slave VCO 802. In some embodiments, reference VCO 850 has a center frequency of 117.23 GHz and a tuning range of 9.01 GHz. Slave VCO 802 is connected to the previously disclosed control loops and is phase and frequency locked to reference VCO 850. Moreover, a DC control voltage, V.sub.steer, is used to change the phase shift between the two VCOs. We will describe the loop behavior and operation principle of the two-element PLL-coupled system 800 in more detail below.

(51) The component values of LPF.sub.1 can be chosen to suppress the ripples and at the same time keep the loop stable. The output voltage of the mixer is at a higher level than what the control voltage of the delay cell can handle. The ratio of R is chosen to have a correct voltage divider at the output of the mixer and create a suitable voltage level for the delay cell. Note that when C.sub.p value is increased, the stability of the loop can be improved, but at the same time more chip area is consumed. In an exemplary design, C.sub.p=6 pF is chosen as a compromise between area and stability.

(52) Note that one of the advantages of the PLL-coupled architecture 800 is the removal of an injection-locked frequency divider (ILFD) at 117 GHz, which is conventionally used in an integer-N PLL. This exclusion leads to a higher locking range and lower power consumption. Moreover, the high frequency routings are limited to the ones between the two VCOs and the adjacent mixers and therefore can be significantly shortened. With no actual phase shifters used in this architecture and to achieve the phase shift by adjusting a control voltage, the disclosed PLL-coupled system 800 can accurately control the phase shift between VCOs 802 and 850, and enable beam steering (when used in a phased array) using the fast and the slow loops that work together. The disclosed PLL-coupled architecture becomes particularly useful for phased array systems at sub-THz frequencies when conventional phase shifters exhibit significant loss at this frequency range.

(53) FIG. 9 shows a linear model of the proposed dual-nested PLL and PLL-coupled array for analyzing the operation and stability of the control loop in accordance with some embodiments. Note that LPF1 can be simplified to just a capacitor C.sub.cp in this linear model, because C.sub.cp reactance at 88 MHz is much smaller than the magnitude of the R.sub.s=18 KΩ. C.sub.p is used to directly connect the mixer to Vc.sub.slave in AC mode. In the fast loop, as the loop is locking, the phase change is rapid and therefore the output of the mixer is fast moving compared to the output of the charge pump in the slow loop. Therefore, the output of the mixer and output of the charge pump can be regarded as AC and DC signals, respectively. As a result, C.sub.p in FIGS. 3, 7, and 8 can be modeled as an adder of these two signals, as shown in FIG. 9. The open-loop transfer function, G.sub.F(s), and closed-loop transfer function, H.sub.F(s) of the fast loop can be derived as:

(54) $\begin{array}{cc}{G}_F\left(s\right)=K_{\mathrm{PD}}.Math.\frac{K_{\mathrm{VCO}}}{s}.Math.\frac{1}{R_1{C}_{1}s+1}\mathrm{and}& \left(1\right)\\ H_F\left(s\right)=\frac{{\varphi }_{\mathrm{slave}}}{{\varphi }_{\mathrm{ref}}}\left(s\right)=\frac{K_{\mathrm{VCO}}{K}_{\mathrm{PD}}}{R_1{C}_1{s}^2+s+K_{\mathrm{VCO}}{K}_{\mathrm{PD}}},& \left(2\right)\end{array}$

(55) wherein R.sub.1 and C.sub.1 create a low-pass filter that is implemented at the output of the mixer (see FIG. 13 below) and K.sub.VCO and K.sub.PD are the gain of the VCOs and mixer respectively.

(56) As a type-I PLL, the fast loop in the disclosed dual-nested PLL has a DC gain that results in the residual phase error between the reference and slave VCOs. A simulation was performed for the case when the fast loop operates alone and the slow loop was removed from FIG. 9 to prove that the fast loop can lock the frequency. It should be noted that C.sub.p acts as a voltage divider together with the capacitance seen from the slave VCO, C.sub.slave. However, the dynamic of the fast loop remains unchanged, because the value of C.sub.p is much larger than C.sub.slave.

(57) To ensure zero phase error between the VCOs in FIG. 9, the combination of the fast and slow loops has to operate together as a type-II PLL. As shown in FIG. 9, the slow loop contains the delay cell, the PFD, the charge pump, the slave VCO, the mixer, and the low-pass filters. The open-loop transfer function, G.sub.S(s), and closed-loop transfer function, H.sub.S(s) of the slow loop can be derived as:

(58) $\begin{array}{cc}{G}_S\left(s\right)=K_{\mathrm{PD}}\frac{I_p{K}_{\mathrm{DL}}{f}_{\mathrm{DL}}}{C_{\mathrm{CP}}s}.Math.\frac{K_{\mathrm{VCO}}}{s}.Math.\frac{1}{1+R_1{C}_{1}s}.Math.\frac{1}{2+{\mathrm{RC}}_{2}s}\mathrm{and}& \left(3\right)\\ H_S\left(s\right)=\frac{{\varphi }_{\mathrm{slave}}}{{\varphi }_{\mathrm{ref}}}\left(s\right)=\frac{G_S\left(s\right)}{1+G_S\left(s\right)},& \left(4\right)\end{array}$

(59) where f.sub.DL is the frequency of the reference input signal applied to the delay cells and K.sub.DL is the gain of voltage-controlled delay cells. The open-loop transfer function of the slow loop, G.sub.S(s), exhibits a type-II PLL containing two poles at origin (i.e., two ideal integrators). This represents an oscillatory system and instability is expected. However, when the two loops (the fast loop and the slow loop) work concurrently, one zero is created, making the system stable. The open-loop transfer function of the complete PLL with both loops activated can be expressed as:

(60) $\begin{array}{cc}{G}_C\left(s\right)=G_F\left(s\right)+G_S\left(s\right)=\frac{K_{\mathrm{PD}}{K}_{\mathrm{VCO}}}{s\left(1+R_1{C}_{1}s\right)}\left[1+\frac{I_P{K}_{\mathrm{DL}}{f}_{\mathrm{DL}}}{C_{\mathrm{CP}}s\left(2+{\mathrm{RC}}_{2}s\right)}\right].& \left(5\right)\end{array}$
Note that Eq. (5) clearly indicates the presence of one zero within the closed-loop transfer function, and the loop is thus stabilized. In summary, control loop comprising of fast and slow loops represents a stable type-II PLL, which locks both the phase and frequency of the two VCOs. Moreover, with this unique PLL architecture, a designer now has the ability to accurately change the phase shift between the VCOs by changing a simple bias voltage V.sub.steer.

(61) FIG. 10 shows the noise sources used to perform the noise analysis of the disclosed dual-nested PLL in accordance with some embodiments. The noise of the slave VCO, reference VCO, mixer and charge pump are modeled as noise sources Φ.sub.N-slave, Φ.sub.N-ref, Φ.sub.N-mixer and Φ.sub.N-cp, respectively. The power spectral density of the output noise (at the output of the slave VCO) with respect to each one of the mentioned sources is calculated as a function of frequency. The simulation results showed that the magnitude of the transfer function of the output noise with respect to the noise of the reference VCO has a low pass behavior, which is to be expected from a type-II PLL. In contrast, the noise of the slave VCO has a high pass behavior to the output. Moreover, the power spectral density of the output phase with respect to the noise of the mixer has a low pass behavior, and with respect to the noise of the charge pump follows a band-pass response. The noise of the DL input (88 MHz reference) does not contribute much to the total noise at the output, because the jitter added from the DL input to the output of both delay cells is correlated. Simulation further shows that phase noise contribution of the reference VCO to the total in-band phase noise is much higher than the other components of the PLL. On the other hand, the out of band phase noise is dominated by the phase noise of the slave VCO. This means that if the reference VCO is locked to a low phase noise crystal, the in-band phase noise will be reduced significantly. As a result of suppressing phase noise from the reference VCO, the mixers' phase noise would have more effect on the in-band phase noise and would be accumulated in later stages.

(62) FIG. 11 shows the circuit topology of an exemplary VCO which is used in the disclosed PLL-coupled array system at 117 GHz in accordance with some embodiments. As can be seen in FIG. 11, the oscillator core of the VCO is composed of 4 stages. As a result, the dominant mode of oscillation has 180° phase shift per stage. This structure enables differential access to the VCO from left and right sides without creating any imbalance in the system. This is an important feature imposed by the proposed phased array of FIG. 5, as each mixer requires a differential signal from each associated VCO.

(63) Note that each stage of the oscillator further includes three transmission lines, i.e., L.sub.D,1, L.sub.D,2 and L.sub.G. L.sub.D,2 lines merge in the middle, which is a virtual ground. The transistors and the transmission lines are laid out similar to the circuit diagram in FIG. 11. This arrangement of the transmission lines boosts the 2nd harmonic current generated by the transistors. Therefore, a significant 2nd harmonic voltage at the drain is generated. Previous study has shown that this 2nd harmonic voltage can boost the swing at the fundamental f.sub.0. This present analysis further shows that that there is positive feedback that increases the amplitude of both fundamental and 2nd harmonic signals at the drain. If the drain loads at f.sub.0 and 2f.sub.0 are resistive, the voltage swing at both fundamental and 2nd harmonic is enhanced. The transmission line configuration at the drain of the transistors in the VCO design of FIG. 11 ensures a resonance near the 2nd harmonic frequency. With a high 2nd harmonic drain current, the 2nd harmonic voltage at the drain will be significant if the impedance at drain nodes of M.sub.1-M.sub.4 are high at 2f.sub.0.

(64) In some embodiments, all transmission lines of the VCO design of FIG. 11 can be implemented using the topmost aluminum layer for high characteristic impedance. This helps achieve higher drain impedance at 2f.sub.0. As stated above, the common node where all L.sub.D,2 lines meet in the middle is virtual ground for odd harmonics only. Therefore, L.sub.M and the following circuits have no impact on the oscillation frequency. Nevertheless, they have an impact on the drain impedance at 2f.sub.0. In order to maintain high drain impedance at 2f.sub.0, an open-stub at 2f.sub.0 can be deployed. This stub creates a short to ground at node P. The Length of L.sub.M is adjusted such that a high drain impedance can be achieved at 2f.sub.0 for M.sub.1-M.sub.4.

(65) The shorted line is also used to provide the supply voltage V.sub.DD and can be used to extract the 4th harmonic power if needed in a sub-THz phased array. Similarly, by a simple redesign of the common virtual ground node, the 2nd harmonic can be extracted if needed. Therefore, if the operation frequency of an application is higher than the f.sub.max of the transistors, this VCO can yield a boosted 2nd or 4th harmonic signal to cover the desired frequency range with more phase shift range. On the other hand, if the operation frequency of an application is lower than the f.sub.max of the transistors, the 2nd or 4th harmonic signal can be used to increase the phase shift range at the cost of a larger area and lower output power.

(66) High harmonic amplitudes at f.sub.0 and 2f.sub.0 create a pseudo half-sine waveform at the drain of each transistor, which is proved to improve phase noise. On the other hand, L.sub.D,1 works as a series peaking inductor and increases the swing at the drain. High swing at the drain pushes the transistor into deep triode region for high 2nd harmonic current generation. Studies have shown that operation in deep triode region is not necessarily harmful to phase noise, and can even improve it by depleting device noise from drain to ground as long as the drain-source oscillation waveform remains half-sine. FIG. 12A shows the measured and simulated tuning range of the stand-alone VCO of FIG. 10 at the fundamental frequency in accordance with some embodiments. This plot demonstrates the tuning range of 9.01 GHz at fundamental frequency ranging from 112.66 to 121.67 GHz. FIG. 12B shows the measured down-converted output spectrum of the reference VCO in accordance with some embodiments.

(67) FIG. 13 shows schematic of an exemplary implementation of the differential mixer used in the disclosed dual-nested PLL as a phase/frequency detector in accordance with some embodiments. Note that this topology of mixer design enables the differential signals to be routed symmetrically from the left and right sides of the mixer in the layout. As a result, there is no need for long and lossy interconnects from VCOs to the mixer, which makes the disclosed PLL architecture scalable. In the design of FIG. 13, transistors M.sub.5-M.sub.8 act as buffers between VCOs and mixer core (M.sub.1-M.sub.4). The T-network matching between the buffer and the core mixer is designed to maximize the oscillation amplitude applied to the mixer core. The transmission line T.sub.1 and C.sub.2 are designed to resonate and increase the impedance seen at f.sub.0 (e.g., at 117 GHz) from the source nodes, utilizing the square law characteristic for mixing performance. The supply of the buffers is connected to the 1-V V.sub.DD plane, whereas mixer transistors operate with 2.4 V supply voltage.

(68) Assuming the output voltage of the reference VCO and slave VCO can be expressed as:
V.sub.ref(t)=A sin(ω.sub.reft+ϕ.sub.ref),
V.sub.slave(t)=A sin(ω.sub.slavet+ϕ.sub.slave),  (6)
the buffers will amplify and apply these signals to the mixer. Because the source nodes in the mixer are designed to be high impedance at the fundamental frequency, the output of the mixer is the multiplication of the input signals. R.sub.1 and C.sub.1 at the output of the mixer create a low-pass filter. When the frequency of VCOs is locked, the output signal of the mixer can be expressed as:
V.sub.O,mix(t)=K.sub.PD(ϕ.sub.slave(t)−ϕ.sub.ref(t)).  (7)

(69) FIG. 14 shows the simulated output voltage of the mixer as a function of phase difference between the reference and slave VCOs with the slope of K.sub.PD in accordance with some embodiments. As can be seen in FIG. 14, the K.sub.PD decreases for the phase difference larger than 120° and lower than 40°, leading to a lower loop gain. As a result, frequency locking and phase steering of the PLL is limited by the mixer characteristic. This means the minimum and maximum phase shift that can be achieved between the VCOs at f.sub.0 (117 GHz) is 40° and 120°, respectively. In some embodiments, to further reach −200° to +120° phase shift in the proposed phased array in FIG. 5, the 4th harmonic from the VCOs can be extracted, which is then radiated using an on-chip antenna.

(70) As demonstrated in FIGS. 6-8, the low frequency part of the disclosed PWM module 600, dual-nested PLL 700, and the two-element coupled PLL array 800 all contain voltage-controlled delay line, PFD, CP and LPF.sub.1. Moreover, a square-shaped signal is applied to the disclosed two paths of the delay cells. The output of each delay cell is a delayed version of the reference signal V.sub.DL that can be controlled by V.sub.Φ and V.sub.steer. If V.sub.Φ and V.sub.steer are equal, the relative delay between the two paths will be zero. Therefore, in steady state and under locked condition V.sub.Φ will be equal to V.sub.steer and the output current of the charge pump will become zero.

(71) FIG. 15 shows the schematic of an exemplary implementation of the differential delay cell in accordance with some embodiments. Note that when M.sub.3 and M.sub.4 are turned on, their drain currents are equal to those of M.sub.7 and M.sub.8, respectively. The M.sub.1 and M.sub.2 combination ensures that V.sub.out− and V.sub.out+ are at voltages close to GND or V.sub.DD. The delay from input to output is a function of the drain current of M.sub.3 and M.sub.4, which are controlled by V.sub.ctrl and the total capacitance seen at output nodes. M.sub.5 and M.sub.6 are used to increase the total capacitance at the output nodes. An optimum K.sub.DL needs to be selected to provide sufficient loop gain and satisfy loop stability. As shown in Eq. (5), the total gain of the delay lines can also be manipulated by changing f.sub.DL. The steering phase can be altered, by externally changing V.sub.steer.

(72) The circuit of the disclosed PLL-coupled array system was fabricated in a 65nm CMOS process. FIG. 16 shows a die micrograph of the 117-GHz PLL-coupled array system in accordance with some embodiments. The supply voltage for V.sub.DD plane was 1 V. The mixer core and charge pump operate with 2.4 V supply to provide wider control voltage. The delay cell and PFD also operate with 1 V supply. We were able to monitor Vc.sub.slave in a steady state operation. This voltage closely follows the Vc.sub.ref, showing frequency locked operation over a wide frequency range of 113-121 GHz.

(73) The proposed PLL-coupled array architecture removes the need for phase shifters at high or low frequencies for phased array applications. By eliminating the phase shifters from the phased array design, the loss and power consumption have been reduced significantly. In addition, in the disclosed PLL-coupled array architecture, the required phase shift can be generated by simply changing an analog control voltage. To overcome the design challenges of a wide-band linear PLL at high frequencies, higher harmonics of the VCO can be used as the output signal which can increase the phase range significantly. Similarly, frequency dividers can be used before the phase detector to reduce the required operation frequency and bandwidth for the phase detector and effectively increase linearity.

(74) Novel phased array architectures based on novel PLL-based phase shifting techniques for the implementation in mm-wave/sub-THz range have been disclosed. The disclosed phased array architectures avoid using phase shifters, which are lossy at mm-wave frequencies. By utilizing a disclosed dual-nested loop PLL, a range of phase shift can be generated between a local VCO and a reference clock. The circuit implementation of the two-element PLL-coupled based on the disclosed dual-nested PLL employs symmetrical mixer topology and differential VCO signaling to avoid long signal routings at high-frequencies, thereby making the system scalable for mm-wave and sub-THz phased arrays with a large number of elements. In the disclosed PLL-coupled array, the fast loop and the slow loop work together to create a type-II PLL that can provide the required phase shift between the slave and reference oscillator. In some embodiments, a wide phase shift at 117 GHz was achieved with the two-element PLL-coupled array with a power consumption measured at 147 mW.

(75) The disclosed phased array architecture can be used in imaging and radar applications, such as FMCW (Frequency Modulated Continuous Wave) automotive radars, to provide accurate range and doppler velocity information used for collision avoidance and automatic cruise control. Moreover, the PLL-coupled array can be used in communication systems to generate the phase shift in LO path of a phased array communication transceiver. The disclosed PLL-based phased array architecture is inherently scalable and therefore is an attractive choice for implementing radiating structures at THz and mm-wave frequencies.

(76) An environment in which one or more embodiments described above are executed may incorporate a general-purpose computer or a special-purpose device such as a hand-held computer or communication device. Some details of such devices (e.g., processor, memory, data storage, display) may be omitted for the sake of clarity. A component such as a processor or memory to which one or more tasks or functions are attributed may be a general component temporarily configured to perform the specified task or function, or may be a specific component manufactured to perform the task or function. The term “processor” as used herein refers to one or more electronic circuits, devices, chips, processing cores and/or other components configured to process data and/or computer program code.

(77) Data structures and program code described in this detailed description are typically stored on a non-transitory computer-readable storage medium, which may be any device or medium that can store code and/or data for use by a computer system. Non-transitory computer-readable storage media include, but are not limited to, volatile memory; non-volatile memory; electrical, magnetic, and optical storage devices such as disk drives, magnetic tape, CDs (compact discs) and DVDs (digital versatile discs or digital video discs), solid-state drives, and/or other non-transitory computer-readable media now known or later developed.

(78) Methods and processes described in the detailed description can be embodied as code and/or data, which may be stored in a non-transitory computer-readable storage medium as described above. When a processor or computer system reads and executes the code and manipulates the data stored on the medium, the processor or computer system performs the methods and processes embodied as code and data structures and stored within the medium.

(79) Furthermore, the methods and processes may be programmed into hardware modules such as, but not limited to, application-specific integrated circuit (ASIC) chips, field-programmable gate arrays (FPGAs), and other programmable-logic devices now known or hereafter developed. When such a hardware module is activated, it performs the methods and processes included within the module.

(80) The foregoing embodiments have been presented for purposes of illustration and description only. They are not intended to be exhaustive or to limit this disclosure to the forms disclosed. Accordingly, many modifications and variations will be apparent to practitioners skilled in the art. The scope is defined by the appended claims, not the preceding disclosure.