Active filter for bipolar voltage sources

Abstract

The invention relates to a device for rejecting interference signals in bipolar voltage sources, in particular in high-voltage sources in a powertrain of an electric vehicle, wherein an amplifier circuit is provided, with an input stage the input of which is symmetrically connected by means of an electrically isolated tap to a positive power line and a negative power line of a voltage source in order to tap an interference signal, and with an output stage, actuated by the input stage, the output of which is symmetrically connected in each case via an output capacitor to the positive power line and the negative power line, in order to feed in a correction signal.

Claims

1. A device for rejecting interference signals in a bipolar voltage source, comprising: an amplifier circuit with an input stage, an input of the input stage being symmetrically connected at a tap point, to a positive power line and a negative power line of the bipolar voltage source via respective input capacitors; and an output stage coupled to the input stage to generate a correction signal, an output of the output stage being symmetrically connected, at the tap point, to the positive power line and the negative power line via respective output capacitors, wherein the device has an inductor coupled between the tap point and the bipolar voltage source, and/or an impedance at the tap point in the direction of the bipolar voltage source that is higher than an impedance at the tap point in the direction of a source of interference, and wherein the interference signals are suppressed.

2. The device for rejecting interference signals according to claim 1, wherein the tap point is directly connected to theft source of interference via the positive power line and the negative power line.

3. The device for rejecting interference signals according to claim 1, wherein the amplifier circuit has a signal propagationtransit time between input and output which is less than or equal to 20 ns.

4. The device for rejecting interference signals according to claim 1, wherein the input stage is a single-stage or two-stage amplifier.

5. The device for rejecting interference signals according to claim 1, wherein the output stage is a push-pull output stage or a current mirror.

6. The device for rejecting interference signals according to claim 1, wherein the output stage is cascadable and the input stage is coupled to several cascaded stages making up the output stage.

7. The device for rejecting interference signals according to claim 1, wherein the input stage and the output stage are formed as discrete semiconductors.

8. The device for rejecting interference signals according to one claim 1, wherein the bipolar voltage source has a battery or a rechargeable accumulator and supplies an electric motor with electrical energy.

9. The device for rejecting interference signals according to claim 1, wherein the positive power line and the negative power line each have a voltage magnitude greater than or equal to 50 volts.

10. The device for rejecting interference signals according to claim 1, wherein the inductor has a ferrite body and the positive and/or negative power line is passed through the ferrite body.

11. The device for rejecting interference signals according to claim 1, wherein the source of interference is a converter or a voltage transformer or an inverter or a speed control of an electric powertrain.

12. The device for rejecting interference signals according to claim 1, wherein the output capacitors are formed as SMD capacitors.

13. The device for rejecting interference signals according to claim 1, wherein the output capacitors each have several capacitors connected in parallel.

14. The device for rejecting interference signals according to claim 1, wherein the input stage and the output stage have a symmetrical voltage supply which is either derived from the positive power line and the negative power line or is derived from a separate low-voltage source.

15. The device for rejecting interference signals according to claim 1, wherein the amplifier circuit is arranged with the input stage and the output stage and the output capacitors on a single circuit board or a single PCB.

16. The device for rejecting interference signals according to claim 15, wherein the circuit board or the PCB has two contacting zones for the electrical connection to the power lines, wherein the first contacting zone is formed for connection to the positive power line and the second contacting zone for connection to the negative power line.

17. The device for rejecting interference signals according to claim 16, wherein the circuit board has a slot which is at least partially bordered by one of the contacting zones, and the electrical connection to a power line is effected in that a locking pin or a screw engages in the slot or through the slot in order to electroconductively connect the contacting zone to the power line.

18. An interference suppression module for retrofitting for bipolar voltage sources, comprising a housing in which an amplifier circuit of a device according to claim 1 is accommodated.

19. The interference-suppression module according to claim 18, wherein the housing comprises connection means for mechanically and/or electrically connecting the amplifier circuit to the positive power line and the negative power line of the bipolar voltage source.

20. The device according to claim 1, wherein the source of interference has a housing with an installation space for accommodating a circuit board or the amplifier circuit, wherein the circuit board or the amplifier circuit is accommodated in the installation space and mechanically connected to the housing of the source of interference.

21. A method for suppressing interference in a bipolar voltage source comprising a positive power line and a negative power line, the method comprising: providing a device comprising an amplifier circuit with an input stage, an input of the input stage being symmetrically connected at a tap point, to a positive power line and a negative power line of the bipolar voltage source via respective input capacitors, and an output stage coupled to the input stage to generate a correction signal, an output of the output stage being symmetrically connected, at the tap point, to the positive power line and the negative power line via respective output capacitors, wherein the device has an inductor coupled between the tap point and the bipolar voltage source, and/or an impedance at the tap point in the direction of the bipolar voltage source that is higher than an impedance at the tap point in the direction of a source of interference, and wherein the interference signals are suppressed; and producing an electrical connection to an electrode of the device by the positive power line and by the negative power line.

22. The method according to claim 21, wherein the electrical connection is produced by a plug-in connection or a screw connection.

23. The method according to claim 21, wherein a hinged ferrite core is attached in each case to the positive power line and to the negative power line such that the core is arranged on the power lines between a battery or a rechargeable accumulator on the one hand and the connection of the device on the other.

Description

(1) Embodiment examples of the invention are represented in the figures and explained below. There are shown in:

(2) FIG. 1 circuit arrangement of the device according to the invention for rejecting interference signals;

(3) FIG. 2 representation of a schematic circuit example of an amplifier circuit of the device according to the invention for rejecting interference signals;

(4) FIG. 3 an example of a circuit of the device according to the invention for rejecting interference signals from FIG. 2.

(5) FIG. 1 shows a circuit arrangement with a bipolar high-voltage source 4, a frequency converter 5 and a device 1 for rejecting interference signals. The device 1 has an amplifier circuit 2 and an inductor 3 and is arranged between the high-voltage source 4 and the frequency converter 5.

(6) The amplifier circuit 2 contacts each of the power lines 6 and 7 at only one point. A first point 8 is connected to the positive power line 6. The amplifier circuit 2 is connected to the negative power line 7 at a second point 9. The signal tapping of an interference signal and the signal feeding in of the correction signal formed by the amplifier circuit is thereby effected at the same point on the positive power line 6 or the negative power line 7. The amplifier circuit 2 is arranged between the frequency converter 5 and the inductor 3.

(7) The y-capacitors 10 and 11 shown in FIG. 1 are optionally arranged in the circuit and serve to improve the interference signal rejection.

(8) An example of an amplifier circuit 2 is represented schematically in FIG. 2. As described above, the amplifier circuit 2 is connected to the positive power line 6 at only one first point 8 and to the negative power line at a second point 9. The amplifier circuit 2 has an input stage 12 and an output stage 13 which are electrically isolated from the power lines 6 and 7 by the capacitors C1 to C4.

(9) The interference signal tapped from the power lines 6 and 7 is amplified in the amplifier circuit 2 and is fed as correction signal with reverse polarity into the power lines 6 and 7 again at points 8 and 9 by the output stage. The correction signal delivered by the output stage is fed directly into the two power lines 6 and 7.

(10) As shown in FIG. 2, the output of the output stage 13 via which a correction signal is fed into the power lines 6 and 7 is connected symmetrically via several capacitors C3 and C4 to the positive power line 6 and the negative power line 7. In the embodiment example according to the invention of FIG. 2, five capacitors C3 are connected in parallel and five capacitors C4 are connected in parallel, respectively. As a result of the parallel connection of the five output capacitors C3 and C4 respectively, parasitic inductances are reduced, as a result of which the transit time in the amplifier circuit 2 is reduced, the signal integrity in the amplifier circuit 2 is improved and interfering voltage fluctuations are rejected.

(11) The amplifier circuit 2 from FIG. 2 is represented in detail in a plugging chart in FIG. 3. It comprises the input stage 12 and the output stage 13.

(12) The input stage 12 has a transistor T1 in a grounded emitter circuit. Via the resistors R1 and R3, the operating point is set at the base of the transistor T1. The capacitors C5 and C6 decouple the grounded emitter circuit with respect to ground. Through a symmetrical low-voltage source U1 and U2, a voltage of ±12 V is applied at the transistor T1. The collector circuit is formed via a collector resistor R2 and a decoupling capacitor C7. The emitter circuit comprises the resistors R4 and R5 and the capacitor C5 as frequency-dependent member. The capacitor C7 on the collector side of the transistor T1 acts as output capacitor of the input stage 12 for decoupling the input stage 12 and the output stage 13. A resistor R6 is arranged with respect to ground between the output of the input stage 12 and the input of the output stage 13.

(13) The output stage 13 is connected to the input stage 12 via the input capacitors C9 and C14. The output stage has two cascaded push-pull output stages. The two transistors T4 and T2 form the first push-pull output stage and the two transistors T5 and T3 form the second push-pull output stage. The resistors R7 to R14 set the operating points at the base of the transistors T2 to T5. The transistors T2 and T3 are formed as npn transistors and the transistors T4 and T5 are formed as complementary pnp transistors. The resistors R11 and R12 or R13 and R14 serve for balancing or for current limiting in the output circuit of the push-pull circuits. The capacitors C10, C11, C15 and C16 are provided for reasons of interference decoupling and decouple the voltage supply with respect to ground.

(14) In the output stage 13, up to eight push-pull output stages can be cascaded which are connected to a third low-voltage source U3 (+12 V) and a fourth low-voltage source U4 (−12 V).

(15) For simplicity's sake, the input stage 12 and the output stage 13 can be fed from the same symmetrical low-voltage source. In this case, U1 is equal to U3 and U2 is equal to U4. Alternatively, separate symmetrical low-voltage sources U1, U2 or U3, U4 can be used for the input stage 12 and the output stage 13, respectively.

(16) The symmetrical low-voltage source U1, U2 or U3, U4 can be fed from the high-voltage source via a voltage transformer. Alternatively, the low-voltage source U1, U2 or U3, U4 can be fed from a separate power supply, for example a 12-V or 24-V power circuit of a vehicle.

LIST OF REFERENCE NUMBERS

(17) 1 device for rejecting interference signals

(18) 2 amplifier circuit

(19) 3 inductor

(20) 4 high-voltage source

(21) 5 frequency converter

(22) 6 positive power line

(23) 7 negative power line

(24) 8 first connection point

(25) 9 second connection point

(26) 10 first y-capacitor

(27) 11 second y-capacitor

(28) 12 input stage

(29) 13 output stage

(30) 14 push-pull output stage

(31) C1 to C18 capacitor

(32) R1 to R14 resistor

(33) T1 to T5 transistor

(34) U1 first low-voltage source

(35) U2 second low-voltage source

(36) U3 third low-voltage source

(37) U4 fourth low-voltage source