Method of current monitoring with temperature compensation

Abstract

A power stage, comprising of multiple power MOSFETs and control and monitoring circuits, is an important part of voltage regulators. The voltage regulator controller typically monitors the power stage output current to implement control and protection functions. Traditional power stages mostly adapt monolithic solutions, suffering from performance inefficiencies due to the LDMOS process, while co-packaged solutions with combined VDMOS and LDMOS processes suffer from potential large current monitoring errors due to different operating temperatures. The current invention proposes a current monitoring circuit with temperature compensation to cancel the temperature coefficient mismatch between the external power MOSFET and the current monitoring circuit. Therefore, the gain of the current monitoring circuit doesn't change with the temperature, allowing for high current monitoring precision, and the temperature compensation circuit doesn't affect the bandwidth of the current monitoring circuit, allowing the use of the output current monitoring signal for close-loop control and over-current protection.

Claims

1. A power stage integrated chip, comprising: a PWM pin, a PVIN pin, a VDD pin, an AGND pin, a PGND pin, an SW pin, and an IMON pin; two dies made of power MOSETs, fabricated using a VDMOS process; a third die containing control, logic, and analog circuits, fabricated using a LDMOS process, wherein the third die further comprises a current monitoring circuit to output a current source signal at the IMON pin based on the output current at the SW pin, wherein the current monitoring circuit further comprises: a first operational amplifier; a current source circuit and a resistor in series to generate a voltage reference to the positive input of the first operational amplifier; a second resistor with two terminals: a first terminal is connected to two switches, each of which connects to the SW pin and the AGND pin respectively, and a second terminal is connected to the negative input of the first operational amplifier; a first P-MOSFET with its gate connected to the output of the first operational amplifier, its source connected to the VDD pin and its drain connected to the negative input of the first operational amplifier; a second operational amplifier; a second P-MOSFET with its gate connected to the output of the first operational amplifier, its source connected to the VDD pin, and its drain is connected to the positive input of the second operational amplifier; a third resistor that connects between the positive input of the second operational amplifier and the AGND pin; a fourth resistor that connects between the negative input of the second operational amplifier and the AGND pin; a current mirror circuit implemented by two P-MOSFETs; an N-MOSFET with its gate is connected to the output of the second operational amplifier, its source connected to the negative input of the second operational amplifier, and its drain is connected to the input of the current mirror circuit; a second current source circuit that connects between the output of the current mirror circuit and the AGND pin; and an IMON terminal at the current mirror circuit's output; and bonding wires or other necessary conductors to interconnect among the three dies.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) A more complete understanding of the present embodiments and advantages thereof may be acquired by referring to the following description taken in conjunction with the accompanying drawings, in which like reference numbers indicate like features, and wherein:

(2) FIG. 1 illustrates an example of a typical power stage IC's block diagram with its external circuit.

(3) FIG. 2 illustrates an example implementation of an LDMOS based power stage.

(4) FIG. 3 illustrates an example implementation of an LDMOS and VDMOS co-packaged power stage.

(5) FIG. 4 illustrates an example of current monitoring circuit with temperature compensation in accordance with the invention.

(6) FIG. 5 illustrates a comparison of IMON output to temperature curve between uncompensated current sensing system and the compensated current monitoring system.

DETAILED DESCRIPTION

(7) FIG. 2 depicts an example of the packaging diagram of a monolithic power stage 200, which only includes one single die 201. Two N-MOSFETs as well as the gate driver circuit, the current monitoring circuit, and the temperature monitoring circuit are fabricated onto this die. Terminals on the die are wired out by bonding wires 202 and bonding ribbons 203. First, two N-MOSFETs and the current monitoring circuit are fabricated through the same LDMOS process, so that their temperature coefficients are very close. Second, the two N-MOSFETs and the current monitoring circuit are purposely located close together on the die, which will result in low temperature difference. Therefore, the current monitoring circuit can precisely measure the output current under different operating temperatures. However, the MOSFETs suffer performance degradation due to the disadvantages of the LDMOS structure.

(8) FIG. 3 depicts an example of the packaging diagram of a co-packaged power stage 300, which includes multiple dies. The gate driver circuit, the current monitoring circuit, and the temperature monitoring circuit are implemented on the first die 301, which is fabricated through LDMOS process. Two N-MOSFETs are implemented on the second die 302 and the third die 303, which are fabricated through the VDMOS process. The interconnections between die terminals and package terminals are implemented by bonding wires 304 and bonding ribbons 305. Compared to the monolithic power stage, the co-packaged power stage shows better performance due to the two N-MOSFETs based on VDMOS process. However, since the MOSFETs and the current monitoring circuit are on separated dies, the temperature coefficient mismatch is inevitable, which results in precision degradation of the current monitoring.

(9) FIG. 4 illustrate the detailed circuit diagram of the current monitoring circuit with the temperature compensation circuit 400. The proposed circuit comprises a current monitoring stage 401, a temperature compensation stage 402, and an output offset stage 403, which are all illustrated in detail below.

(10) The current monitoring stage measures the voltage of the half-bridge's SW node 404 and converts the voltage into a current signal I.sub.S 405. First, the current monitoring stage comprises a reference current source I.sub.OS1 406, an operational amplifier OP1 407, a P-MOSFET M1 408, resistor R.sub.S1 409, resistor R.sub.S2 410, switch S.sub.1 411, and switch S.sub.2 412. The current source I.sub.OS1 flow through the resistor R.sub.S1 to generate a positive offset voltage for the op-amp's positive input V.sub.p.op1. Therefore,
V.sub.p.op1=I.sub.OS1.Math.R.sub.S1
When half-bridge's low-side switch is on, switch S.sub.2 also turns on and switch S.sub.1 turns off. The voltage of the SW node is
V.sub.SW=?R.sub.O.Math.I.sub.L
where I.sub.L is the output current of the power stage and R.sub.O is the on-stage resistance of the low-side MOSFET.
The op-amp and the P-MOSFET form a current amplifier circuit. According to the principle of the operational amplifier, V.sub.p.op1=V.sub.n.op1. Therefore,
V.sub.n.op1=V.sub.SW+R.sub.S2.Math.I.sub.S=?R.sub.O.Math.I.sub.L+R.sub.S2.Math.I.sub.S
where I.sub.S is the current flow through the P-MOSFET M1. Let R.sub.S1=R.sub.S2=R.sub.S, I.sub.S can be written as

(11) $I_S=I_{OS1}+\frac{R_O}{R_S}.Math.I_L$

(12) The temperature compensation stage comprises a P-MOSFET M2 413, a zero-temperature coefficient resistor R.sub.Z 414, an operational amplifier OP2 415, another P-MOSFET M3 416, an N-MOSFET M5 417, and a negative temperature coefficient resistor R.sub.N 418. The P-MOSFET M2 along with the P-MOSFET M1 form a current mirror circuit. Since M1 and M2 can be designed to have the same width and length on chip, the current flow through M2 is identical to the current flow through M1. Thus, the voltage at OP2's positive input Vp.op2 is
V.sub.p.op2=R.sub.Z.Math.I.sub.S
Op-amp OP2 and M5 forms a current amplifier circuit. According to the principle of the operational amplifier, V.sub.p.op2=V.sub.n.op2. Therefore,
V.sub.n.op2=R.sub.Z.Math.I.sub.S=R.sub.N.Math.I.sub.S1
where I.sub.S1 is the current flow through M2. Since M3 and M5 are in the same branch, the current flow through M3 is also I.sub.S1, which is

(13) $I_{S1}=\frac{R_Z}{R_N}{I}_S=\frac{R_Z}{R_N}{I}_{OS1}+\frac{R_O{R}_Z}{R_S{R}_N}{I}_L$

(14) The output offset stage comprises a P-MOSFET M4 419 and a current source I.sub.OS2 420. The P-MOSFET M4 and the P-MOSFET M3 forms a current mirror circuit. Also, M4 and M3 can be designed to have the same width and length on chip, the current flow through M3 is identical to the current flow through M4. The current source I.sub.OS2 can be designed to a fixed value, which is

(15) $I_{OS2}=\frac{R_Z}{R_N}{I}_{OS1}$
According to circuit law, the output current IMON is

(16) $I_{MON}=I_{S1}-I_{OS2}=\frac{R_O{R}_Z}{R_S{R}_N}{I}_L$
Assuming the temperature coefficients for R.sub.O is ?.sub.O, temperature coefficient for R.sub.N is an, and temperature coefficient for R.sub.S is as, then R.sub.O, R.sub.N, and R.sub.S can be written as
R.sub.O=r.sub.O(?.sub.OT+1)
R.sub.N=r.sub.N(?.sub.NT+1)
R.sub.S=r.sub.S(?.sub.ST+1)

(17) Where r.sub.O, r.sub.N, r.sub.S are constants and an is less than 0. Since R.sub.Z is zero temperature coefficient resistor, let R.sub.Z=r.sub.Z, where r.sub.Z is constant. Thus, the output current I.sub.MON can be written as

(18) $I_{MON}=\frac{r_O\left({?}_{O}T+1\right)r_Z}{r_S\left({?}_{S}T+1\right)r_N\left({?}_{N}T+1\right)}{I}_L=\frac{r_O{r}_Z\left({?}_{O}T+1\right)}{r_S{r}_N\left({?}_S{?}_N{T}^2+\left({?}_S+{?}_N\right)T+1\right)}{I}_L$
Since ?.sub.S and ?.sub.N are much smaller than 1, the second-order term is negligible. Then,

(19) $I_{MON}=\frac{r_O{r}_Z\left({?}_{O}T+1\right)}{r_S{r}_N\left(\left({?}_S+{?}_N\right)T+1\right)}{I}_L$
When ?.sub.S>?.sub.O, ?.sub.S and an can be designed to satisfy ?.sub.S+?.sub.N=?.sub.O. Thus, the temperature dependent terms are cancelled. Therefore,

(20) $I_{MON}=\frac{r_O{r}_Z}{r_S{r}_N}{I}_L$
As it is shown, the output current signal I.sub.MON is independent of temperature. When ?.sub.S<?.sub.O, the proposed feature can be implemented by switching the position of R.sub.Z and R.sub.N. The output current IMON becomes

(21) $I_{MON}=\frac{r_O{r}_Z\left(\left({?}_O+{?}_N\right)T+1\right)}{r_S{r}_N\left({?}_{S}T+1\right)}{I}_L$
By designing ?.sub.S and ?.sub.N to satisfy ?.sub.S=?.sub.N+?.sub.O, the temperature dependent terms can also be cancelled.

(22) FIG. 5 illustrates a comparison of IMON output to temperature curve between uncompensated current sensing system and the compensated current monitoring system 500. The green curve 501 is the IMON output without temperature compensation. As it is shown, the output voltage variation can be as large as 54.7 mV 502. The red curve 503 is the IMON output with temperature compensation. As it is shown, the output voltage variation is only 7.2 mV 504.