Miniature ultra-low-power LNA employing current reuse and bias sharing

Abstract

A low noise amplifier (LNA) offering one or more of the following benefits: increased gain, reduced power consumption, and/or reduced area, while achieving a similar noise figure, is disclosed. The LNA achieves these benefits by employing an inductorless chip design, current reuse among the transistors, bias sharing, limited AC coupling capacitors, common gate input device feedback, and careful sizing of the transistors.

Claims

1. A low noise amplifier comprising: an input adapted to receive a signal; a first transistor of a first type, a source of the first transistor coupled to the input; a second transistor of the first type, a source of the second transistor coupled a drain of the first transistor; a positive output adapted to output a positive polarity of an amplified signal, the positive output coupled to a drain of the second transistor; a third transistor of the first type, a source of the second transistor coupled to a gate of the third transistor and a source of the third transistor coupled to a gate of the second transistor; a negative output adapted to output a negative polarity of the amplified signal, the negative output coupled to a drain of the third transistor; a fourth transistor of the first type, a drain of the fourth transistor coupled to the source of the third transistor and a gate of the first transistor, a gate of the fourth transistor coupled to the input; a fifth transistor of a second type, a gate of the fifth transistor coupled to the input; and a sixth transistor of the first type, a drain of the sixth transistor coupled a source of the fifth transistor, and a gate of the sixth transistor coupled to the input.

2. The low noise amplifier of claim 1, wherein the first type is NMOS, and the second type is PMOS.

3. The low noise amplifier of claim 1, further comprising an inductor coupled to the input.

4. The low noise amplifier of claim 1, wherein the fifth and sixth transistors implement an inverter function.

5. The low noise amplifier of claim 1, wherein the first, fourth, and sixth transistors have a same length.

6. The low noise amplifier of claim 1, wherein the first, fourth, and sixth transistors have a same finger width.

7. The low noise amplifier of claim 1, wherein sizes of the first, second, third, fourth, and sixth transistors are adapted to produce a voltage at the source of the second transistor that is substantially equal to a voltage at the source of the third transistor when the low noise amplifier is operating.

8. The low noise amplifier of claim 1, wherein the low noise amplifier is adapted to be biased by a current through the fifth transistor when the low noise amplifier is operating.

9. The low noise amplifier of claim 1, wherein an input impedance at the input is approximately 50? or 75?.

10. A low noise amplifier comprising: a first leg including first and second transistors, the first and second transistors having a cascode configuration, with a drain of the first transistor being coupled to a source of the second transistor; a second leg cross-coupled to the first leg, the second leg including third, fourth, fifth, and sixth transistors, the fifth and sixth transistors having an inverter configuration and being coupled to the third and fourth transistors having a cascode configuration, with a drain of the fourth transistor being coupled to a source of the third transistor, and a gate of the first transistor being coupled to the source of the third transistor; an input adapted to receive a signal, the input coupled to the first leg; a positive output adapted to output a positive polarity of an amplified signal, the positive output coupled to the first leg; and a negative output adapted to output a negative polarity of the amplified signal, the negative output coupled to the second leg.

11. The low noise amplifier of claim 10, wherein the first, second, third, fourth, and sixth transistors are NMOS transistors, and the fifth transistor is a PMOS transistor.

12. The low noise amplifier of claim 10, wherein the second and third transistors have a cross-coupled configuration.

13. The low noise amplifier of claim 10, wherein the first leg further includes an inductor coupled to the input.

14. The low noise amplifier of claim 10, wherein the first, fourth, and sixth transistors have a same length.

15. The low noise amplifier of claim 10, wherein the first, fourth, and sixth transistors have a same finger width.

16. The low noise amplifier of claim 10, wherein sizes of the first, second, third, fourth, and sixth transistors are adapted to produce a voltage at the source of the second transistor that is substantially equal to a voltage at the source of the third transistor when the low noise amplifier is operating.

17. The low noise amplifier of claim 10, wherein the low noise amplifier is adapted to be biased by a current through the fifth transistor.

18. The low noise amplifier of claim 10, wherein an input impedance at the input is approximately 50? or 75?.

Description

BRIEF DESCRIPTION OF DRAWINGS

(1) The drawings illustrate several embodiments of the invention, wherein identical reference numerals refer to identical or similar elements or features in different views or embodiments shown in the drawings. The drawings are not to scale and are intended only to illustrate the elements of various embodiments of the present invention.

(2) FIG. 1 illustrates a single-ended programmable delay device in accordance with one or more embodiments of the present invention.

(3) FIG. 2 illustrates a timing diagram for a programmable delay device in accordance with one or more embodiments of the present invention.

(4) FIG. 3A illustrates a block diagram, while FIGS. 3B-3E illustrate corresponding circuit diagrams, for a differential embodiment of a programmable delay device in accordance with one or more embodiments of the present invention.

(5) FIG. 4 is a photomicrograph of a programmable delay device in accordance with one or more embodiments of the present invention.

(6) FIG. 5 illustrates the measured delay performance across all delay settings for a programmable delay device in accordance with one or more embodiments of the present invention.

(7) FIG. 6 illustrates the measured differential nonlinearity and integral nonlinearity across all delay settings for a programmable delay device in accordance with one or more embodiments of the present invention.

(8) FIGS. 7A and 7B illustrate the measured delay response at minimum and maximum delay settings, respectively, across a 0.2to ?2 GHz input frequency range for a programmable delay device in accordance with one or more embodiments of the present invention.

(9) FIGS. 8A-8D illustrate the measured gain, noise figure, matching, and power consumption breakdown, respectively, for a programmable delay device in accordance with one or more embodiments of the present invention.

(10) FIG. 9 illustrates a block diagram for a second differential embodiment of a programmable delay device in accordance with one or more embodiments of the present invention.

(11) FIGS. 10A and 10B illustrate the measured delay response at minimum and maximum delay settings, respectively, at both ?40? C. and 85? C., across a 0.2to ?2 GHz input frequency range for a programmable delay device in accordance with one or more embodiments of the present invention.

(12) FIGS. 11A and 11B illustrate the measured gain and noise figure between ?40? C. and 85? C., respectively, for a programmable delay device in accordance with one or more embodiments of the present invention.

(13) FIGS. 12A and 12B illustrate the measured output spectrum up to FS/2 given an input tone at 1 GHz with signal levels ?30 dBm and ?37 dBm, respectively, for a programmable delay device in accordance with one or more embodiments of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

(14) FIG. 1 illustrates a single-ended configuration programmable delay device 100 in accordance with one or more embodiments employing a time-interleaved multistage switched-capacitor (TIMS-SC) architecture. The programmable delay device is preferably implemented in a differential manner as described below with reference to FIG. 3. The programmable delay device 100 includes an input sampling stage 120 of eight sampling switched capacitor storage elements 121.sub.0-121.sub.7. Each sampling switched capacitor storage element 121.sub.0-121.sub.7 includes a corresponding input sampling switch 122.sub.0-122.sub.7 and corresponding input sampling capacitor 123.sub.0-123.sub.7. The eight sampling switched capacitor storage elements 121.sub.0-121.sub.7 are sequentially coupled to an input RF signal 110 via corresponding input sampling switches 122.sub.0-122.sub.7, thereby sequentially sampling the input RF signal 110. For example, sampling switched capacitor storage element 121.sub.0 temporarily stores samples 1, 9, etc., while sampling switched capacitor storage element 121.sub.1 temporarily stores samples 2, 10, etc. This sampling process will be described below with respect to FIG. 2. The signals held by the eight sampling switched capacitor storage elements 121.sub.0-121.sub.7 are termed input sampled signals. Each of the eight sampling switched capacitor storage elements 121.sub.0-121.sub.7 is coupled to a corresponding programmable switched capacitor bank 131.sub.0-131.sub.7 in a programmable delay stage 130 via a corresponding buffer 124.sub.0-124.sub.7.

(15) In this illustrated embodiment, the input sampling stage 120 is an 8-phase switched capacitor network sampling at the full sampling rate of F.sub.S. While the input sampling stage 120 illustrated in FIG. 1 has eight sampling switched capacitor storage elements 121.sub.0-121.sub.7, i.e., is an 8-phase switched capacitor network, other embodiments may have an input sampling stage with M sampling switched capacitor storage elements, resulting in an M-phase switched capacitor network. In these embodiments, M may be smaller or larger than 8, though M is preferrable 4 or greater. Further, in this embodiment with eight programmable switched capacitor banks 131.sub.0-131.sub.7, each programmable switched capacitor bank 131.sub.0-131.sub.7 has a sampling rate of F.sub.S/8.

(16) As illustrated in FIG. 1, each programmable switched capacitor bank 131.sub.0-131.sub.7 includes 186 delay switched capacitor storage elements 132.sub.0-132.sub.185. Each delay switched capacitor storage element 132.sub.0-132.sub.185 includes a corresponding input switched bank switch 133.sub.0-133.sub.185 and corresponding switched bank sampling capacitor 134.sub.0-134.sub.185. The 186 delay switched capacitor storage elements 132.sub.0-132.sub.185 are coupled to a corresponding buffer 124.sub.0-124.sub.7 via corresponding input switched bank switches 133.sub.0-133.sub.185 in a time interleaved manner, thereby sampling a corresponding input sampled signal. Thus, the programmable delay stage 130 includes a total of 8?186=1,488 delay switched capacitor storage elements, i.e., 1,488 input switched bank switches and 1,488 switched bank sampling capacitors. The signals held by the 1,488 delay switched capacitor storage elements are termed delay sampled switched signals. Each delay switched capacitor storage element 132.sub.0-132.sub.185 is coupled to a corresponding delay buffer 135.sub.0-135.sub.185 and delay output switch 136.sub.0-136.sub.185.

(17) While the programmable delay stage 130 illustrated in FIG. 1 has eight programmable switched capacitor banks 131.sub.0-131.sub.7, other embodiments may have a programmable delay stage with M programmable switched capacitor banks. In these embodiments, M may be smaller or larger than 8, though the number of programmable switched capacitor banks in the programmable delay stage must equal the number of sampling switched capacitor storage elements in the input sampling stage. Further, while each programmable switched capacitor bank 131.sub.0-131.sub.7 illustrated in FIG. 1 includes 186 delay switched capacitor storage elements 132.sub.0-132.sub.185, other embodiments may have programmable switched capacitor banks with N delay switched capacitor storage elements. In these embodiments, N may be smaller or larger than 186, with a larger value for N resulting in a greater range of programmable delay times and a larger physical device. N is preferably 64 or greater.

(18) Each of the eight programmable switched capacitor banks 131.sub.0-131.sub.7 is coupled to a corresponding output reconstruction switch 142.sub.0-142.sub.7 via a corresponding optional output buffer 141.sub.0-141.sub.7 in an output reconstruction stage 140. The signals output by the eight optional output buffer 141.sub.0-141.sub.7 are termed output reconstruction signals. In this embodiment, the output reconstruction stage 140 is an 8-phase switching network operating at the full sampling rate of F.sub.S. The output reconstruction stage 140, based on the sequential switching of the output reconstruction switches 142.sub.0-142.sub.7, outputs a reconstructed delayed output RF signal 150, that corresponds to a programmed time delayed version of the input RF signal 110.

(19) The programmable delay device 100 illustrated in FIG. 1 includes a first set of eight buffers 123.sub.0-123.sub.7 between the input sampling stage 120 and the programmable delay stage 130, along with a second set of eight optional output buffers 141.sub.0-141.sub.7 between the programmable delay stage 130 and the output reconstruction stage 140. The programmable delay device 100 further includes delay buffers 135.sub.0-135.sub.185 in each of the eight programmable switched capacitor banks 131.sub.0-131.sub.7. In other embodiments, these delay buffers 135.sub.0-135.sub.185 may be deleted leading to a passive implementation, thereby creating a tradeoff between power consumption, loss of gain, area, and area efficiency.

(20) FIG. 2 illustrates a timing diagram 200 for the programmable delay device 100 illustrated in FIG. 1. The first two lines 210.sub.0, 210.sub.1 of the timing diagram 200 correspond to the sampling of the input signal 110 by the first two sampling switched capacitor storage elements 121.sub.0, 121.sub.1 via input sampling switches 122.sub.0, 122.sub.1, i.e., clocks P.sub.0 and P.sub.1. The next three lines 220.sub.0,0, 220.sub.0,1, 220.sub.1,0 correspond to the sampling of the signals output by the first two sampling switched capacitor storage elements 121.sub.0, 121.sub.1 by the first two delay switched capacitor storage elements 132.sub.0, 132.sub.1 of the first programmable switched capacitor bank 131.sub.0, i.e., clocks PI.sub.0,0 and PI.sub.0,1, and the first delay switched capacitor storage element 132.sub.0 of the second programmable switched capacitor bank 131.sub.1, i.e., clock P.sub.1,0, respectively. The last two lines 230.sub.0,0, 230.sub.1,0 of the timing diagram 200 correspond to the output timing of the first delay switched capacitor storage element 132.sub.0 of the first programmable switched capacitor bank 131.sub.0 and the first delay switched capacitor storage element 132.sub.0 of the second programmable switched capacitor bank 131.sub.1, i.e., clocks P0.sub.0,0 and P0.sub.1,0, respectively.

(21) As reflected by the first two lines 210.sub.0, 210.sub.1, the input signal 110 is sampled at a sampling rate of F.sub.S with a period of T=1/Fs, with the first two sampling switched capacitor storage elements 121.sub.0, 121.sub.1 sampling the first ?th T and second ?th T, respectively. The first line 210.sub.0 shows the sampling of the input signal 110 that generates input sampled signals 1, 9, 17, etc., while the second line 210.sub.1 shows the sampling of the input signal 110 that generates input sampled signals 2, 10, 18, etc. The third line 220.sub.0,0 shows the storage of input sampled signal 1 by the first delay switched capacitor storage element 132.sub.0 in the first programmable switched capacitor bank 131.sub.0 as delay sampled switched signal 1. The fourth line 220.sub.0,1 shows the storage of input sampled signal 9 by the second delay switched capacitor storage element 132.sub.1 in the first programmable switched capacitor bank 131.sub.0 as delay sampled switched signal 9. The fifth line 220.sub.1,0 shows the storage of input sampled signal 2 by the first delay switched capacitor storage element 132.sub.0 in the second programmable switched capacitor bank 131.sub.1 as delay sampled switched signal 2. The sixth line 230.sub.0,0 shows the passing of delay sampled switched signal 1 stored by the first delay switched capacitor storage element 132.sub.0 in the first programmable switched capacitor bank 131.sub.0 to the output reconstruction switch 142.sub.0 via the output buffer 141.sub.0 as output reconstruction signal 1. The seventh line 230.sub.1,0 shows the passing of delay sampled switched signal 2 stored by the first delay switched capacitor storage element 132.sub.0 in the second programmable switched capacitor bank 131.sub.1 to the output reconstruction switch 142.sub.1 via the output buffer 1411 as output reconstruction signal 2.

(22) While the settling time T is 1/Fs in the input sampling stage 120, settling time expansion is created in the programmable delay stage 130 by allowing sample transfer from the input sampling stage 120 to the programmable delay stage 130 to continue during the input sampling stage 120 hold time. With the expanded sample time, the sampler bandwidth required in the programmable delay stage 130 is greatly reduced. This allows the use of much smaller input switched bank switches 133.sub.0-133.sub.185 in the delay switched capacitor storage elements 132.sub.0-132.sub.185 of the programmable delay stage 130, which in turn enables a large reduction in OFF state sample leakage. This leakage reduction enables a corresponding increase in the maximum achievable hold time, which is key to achieving more than 100 ns of delay. (The programmable delay device 100 illustrated in FIG. 1 achieved a maximum delay of approximately 450 ns at a sampling frequency F.sub.S of 3.3 GHz.)

(23) To reduce timing skew sensitivity, the programmable delay stage 130 input clock signal PI.sub.x,y transitions prior to the input sampling stage 120 input sample clock signal P.sub.x, where x corresponds to the path in the input sampling stage 120 (i.e., it has a value from 0 to 7) and y corresponds to the path in the programmable delay stage 130 (i.e., it has a value from 0 to 185). Thus, the programmable delay stage 130 input is static during clock transitions (e.g., PI.sub.1,0 before P.sub.1). After the programmed delay, a programmable delay stage 130 output clock signal PO.sub.x,y initiates the transfer of the delay sampled switched signal to the input of the corresponding output buffer 141.sub.0-141.sub.7, again time expanded. The output buffers 141.sub.0-141.sub.7 output the delay sampled switched signals employing the same 8-phase clock timing as the input sampling stage 120 (P.sub.x) as corresponding output reconstruction signals. Timing skew is again mitigated by transitioning the programmable delay stage 130 output clock signal PO.sub.x,y after the output reconstruction stage 140 output clock signal P.sub.x. The input and output clocks in the programmable delay stage 130 are generated by two separate, but synchronous, divide-by-186 clocks, as will be described below with reference to FIG. 3. The delay is programmed by delaying the enable timing (described below with reference to FIG. 3) of the programmable delay stage 130 output clock signal PO.sub.x,0 relative to the associated input clock signal PI.sub.x,0. For the programmable delay device 100 illustrated in FIG. 1, the delay can be programmed over a range from 8/Fs to 1480/Fs (in 8/Fs increments) and scales with the sample frequency F.sub.S.

(24) FIG. 3A illustrates a block diagram while FIGS. 3B-3E illustrate corresponding exemplary circuit diagrams for a differential configuration embodiment of a programmable delay device 300 in accordance with one or more embodiments. The programmable delay device 300 may, for example, be formed of CMOS circuitry on a single Si substrate, though other embodiments may, for example, employ circuitry formed of other IV, III-V, or II-VI semiconductor materials. An optional inductorless low noise amplifier (LNA) 304 receives an input RF signal 302 and provides both gain and differential conversion with NMOS bias sharing (see FIG. 3B) to reduce AC coupling capacitors for area savings. An optional device input buffer 306 provides isolation between the output of the LNA 304 and sampling switched capacitor storage elements 308 of the input sampling stage, and employs a push-pull output stage (see FIG. 3C). Each sampling switched capacitor storage element 308 employs a differential capacitor (see FIG. 3D), having, for example, a capacitance of 250 fF, for small area and sampling noise. The differential capacitors store corresponding input sampled signals. The optional buffers 310 between the sampling switched capacitor storage elements 308 and the 186 delay switched capacitor storage elements 312 per programmable switched capacitor bank each employs an NMOS common-source with diode-connected load for unity gain matching between the 8 paths. All the buffers 310 are preferably closely placed in the layout to limit gain mismatch induced signal distortion. The 186 delay switched capacitor storage elements 312 per programmable switched capacitor bank each employs a differential capacitor for storing corresponding delay sampled switched signals.

(25) The LNA 304, illustrated in FIG. 3B, includes several features not found in prior art LNA designs. Specifically, the LNA 304 uses current reuse, bias sharing, a limited number of AC coupling capacitors, and common gate input device feedback to reduce area and power consumption compared to prior art inductorless LNAs. The design of LNA 304 provides one or more benefits over prior art inductorless LNAs including comparable noise figure, high linearity performance, 25-320% power savings, and 19-100? area savings.

(26) Details of the design of the LNA 304 are as follows. The source of a common gate transistor 304A is directly connected to the RF input signal, while the common gate transistor 304A is DC biased by a single off-chip inductor 304B to ground. To save power, the gate of the common gate transistor 304A is connected in feedback to the output of a second leg 304C having an inverter-plus-common-source configuration. The input impedance of the LNA 304 is 1/(g.sub.m*(1+g.sub.net)) where g.sub.m is the transconductance of transistor 304A and g.sub.net can be approximated as the combined transconductances of transistors 304D, 304E, and 304H divided by the transconductance of transistor 304G given that the combined transconductances of transistors 304D and 304E are much larger than the transconductance of transistor 304A. This enables, for example, an approximately 50? or 75? input impedance match with the external input circuitry (the most common desired impedances).

(27) Further, this provides significant power savings, at least a factor of 2?, via current reuse through both the PMOS and NMOS transistors 304D, 304E in the inverter, which add to the transconductance of transistor 304H. A further benefit is that the size of the common gate transistor 304A can be optimized by the feedback gain provided by the inverter path.

(28) The cross-coupled transistors 304F, 304G provide good gain balance between the differential outputs of the balun LNA 304. Differential signals see between 1/g.sub.m and 1/(2*g.sub.m) looking into the sources of the cascode transistors 304F, 304G, while common mode signals see ideally infinite impedance, i.e., they are rejected before being output. It should be noted that only two devices are stacked in the design of the LNA 304, which allows for low voltage operation, for example, 1 V or less, as may be found with advanced node CMOS.

(29) One of the key innovations of this design of the LNA 304 is the biasing structure, which saves significant area and increases the gain of the LNA 304. This enables a DC short of the output of the inverter transistors 304D, 304E and node B. Without this DC short, a DC blocking capacitor is required between these nodes, which is placed into a low impedance 1/g.sub.m node. This would necessitate a very large capacitor, which takes up considerable area and creates considerable loss in the gain of the LNA.

(30) The design of the LNA 304 requires careful sizing of the NMOS transistors 304A, 304E, 304F, 304G, 304H. Proper sizing results in the LNA 304 at DC being biased such that nodes A and B are at substantially the same voltage level across process, supply voltage, and temperature variation. By making the common gate transistor 304A, the common source transistor 304H, and the NMOS transistor 304E of the inverter with the same length and per device finger width, but varying the transistor finger number for device sizing, each of these NMOS transistors can share a gate and drain voltage at DC and have a bias current that is exactly the ratio of the number of fingers used in each transistor. This design thus allows for the entire LNA 304 to be current biased using the current in the PMOS transistor 304D in the inverter portion.

(31) The various coupling capacitors feed nodes with high impedances, making them very small in size, thereby ensuring a small overall layout size for the LNA 304.

(32) Table 1 provides simulation performance details comparing one embodiment of the present invention with various prior art LNAs. In Table 1, Bozorg 2021 corresponds to A. Bozorg et al. A 0.02-4.5-GHz LN(T)A in 28-nm CMOS for 5G Exploiting Noise Reduction and Current Reuse, Yu 2019 corresponds to H. Yu et al., A 0.044-mm.sup.2 0.5to ?7-GHz Resistor-Plus-Source-Follower-Feedback Noise-Cancelling LNA Achieving a Flat NF of 3.3?0.45 dB, and Regulagadda 2019 corresponds to S. S. Regulagadda et al., A Packaged Noise-Canceling High-Gain Wideband Low Noise Amplifier. As shown in Table 1, this implemented embodiment of the present invention yielded simulated performance after extraction of the proposed design of ?7 dB more gain, a similar noise figure, and 25-320% power savings over other prior art LNAs, while consuming 19-100? less area.

(33) TABLE-US-00001 TABLE 1 LNA performance comparison. Present Bozorg Regulagadda Invention 2021 Yu 2019 2019 Freq 0.1-6.0 GHz 0.02-4.5 GHz 0.5-7.0 GHz 0.4-2.2 GHz Process 45 nm 28 nm 65 nm 65 nm Gain 24 dB 15 dB 17 dB 16.4 dB NF 3.5 dB 3.2 dB 3.3 dB 2.5 dB IIP3 ?3.6 dBm ?4.6 dBm ?4.5 dBm ?5.0 dBm Power 3.5 mW 4.5 mW 11.3 mW 29 mW Size 0.0016 mm.sup.2 0.03 mm.sup.2 0.044 mm.sup.2 0.16 mm.sup.2

(34) The optional delay buffers 314 of the programmable switched capacitor banks each employs a dynamic inverter clocked at both VSS and VDD by POy, where one of the 186 delay buffers 314 in each path are enabled at a time and all 186 delay buffers 314 share an optional self-biased inverter load 316 for common-mode stability in each of the 8 delay paths. The optional output buffers 318, which incorporate the non-optional output reconstruction switches, are preferably closely placed in the layout for unity gain matching and employ dynamic common-source amplifiers with a shared resistive load. The output reconstruction switches 318 output corresponding output reconstruction signals. An optional device output buffer 320, coupled to the output reconstruction switches 318 provides balun and matching operation and employs a common-source amplifier and push-pull output stage (see FIG. 3E) that outputs a reconstructed delayed output RF signal 322.

(35) Clocking is provided from an input clock 330 at a frequency F.sub.S through a divide-by-2 (F.sub.CLK=2F.sub.S) clock 332. While the programmable delay device 300 illustrated in FIG. 3A includes a divide-by-2 clock 332, other embodiments may not include any divide-by clock at this point in the clock tree, or may include a divide-by-P clock as desired. An input divide-by 8 clock 334 generates the input sample clock signal P.sub.x and an output divide-by-8 clock 336 generates the output reconstruction clock signal P.sub.x, the output reconstruction clock signal P.sub.x being synchronous with the input sample clock signal P.sub.x for low timing skew at the input sampling stage (sampling switched capacitor storage elements 308) and the output reconstruction stage (output reconstruction switches 318) based on the clock signal from the divide-by-2 clock 332. In the more general case, the input divide-by-8 clock 334 and the output divide-by-8 clock 336 would both be divide-by-M clocks. The input sample clock signal P.sub.x from the input divide-by-8 clock 334 is pulse extended to a 50% duty cycle by an input pulse extend clock 338. The input pulse extend clock 338 drives input divide-by-186 clocks 340, which generate the input clock signals PI.sub.x,y, and which are placed inside each programmable switched capacitor bank area for standard logic implementation compatibility. The output reconstruction clock signal P.sub.x from the output divide-by-8 clock 336 is pulse extended to a 50% duty cycle by an output pulse extend clock 342. The output pulse extend clock 342 drives output divide-by-186 clocks 344, which generate output clock signals PO.sub.x,y, and which are placed inside each programmable switched capacitor bank area for standard logic implementation compatibility. In the more general case, the input divide-by-186 clocks 340 and the output divide-by-186 clocks 344 would be divide-by-N clocks. While the programmable delay device 300 illustrated in FIG. 3A includes an input pulse extend clock 338 and an output pulse extend clock 342, other embodiments may not include one or both pulse extend clocks 338, 342, though this may require custom logic circuitry. While the programmable delay device 300 illustrated in FIG. 3A includes both an input divide-by-8 clock 334 and an output divide-by-8 clock 336, other embodiments may employ a single divide-by-8 clock (or more generally a divide-by-M clock), though this may result in clock timing skew issues.

(36) The programmable delay operates as follows. The desired delay value Z (between 1 and 185 in the illustrated embodiment), corresponding to delays of 8/Fs to 1480/Fs in 8/Fs increments, is entered using a serial programming interface 350 by an external programming source. The serial programming interface 350 outputs the desired delay value Z, which generates a delay of Z*8/Fs, to a digital counter in the enable timing circuit 352. The digital counter is enabled at the same time as the input divide-by-186 clocks 340, which generate the input clock signals PI.sub.x,y. The digital counter counts up to the programmed delay value Z. Once the digital counter reaches Z, the output divide-by-186 clocks 344, which generate output clock signals PO.sub.x,y, are enabled, thereby causing the first sample to transfer to the corresponding output reconstruction switch 318. The output clock signals PO.sub.x,y continue to cause the transfer of samples to the output reconstruction switches 318 indefinitely and are delayed relative to the input clock signals PI.sub.x,y by the desired delay Z*8/Fs.

(37) A programmable delay device in accordance with at least one embodiment was implemented in a 45 nm SOI CMOS process, resulting in a 4 mm.sup.2 chip area and 1.36 mm.sup.2 active area, as illustrated in the photomicrograph of FIG. 4. The programmable delay device was packaged in a 5?5 mm.sup.2 quad-flat no-leads (QFN) package for testing. The sample frequency was chosen to be F.sub.S=3.3 GHz (F.sub.CLK=6.6 GHz) for full characterization. The programmable delay device was found to operate beyond F.sub.S=4.4 GHz (F.sub.CLK=8.8 GHz) and below F.sub.S=3.3 GHz, providing system flexibility in clock frequency, delay range, and frequency coverage. In general, the sample frequency Fs may be selected based upon the maximum desired delay (M*(N?1)/Fs), the desired incremental delay (M/Fs), and the number of delay switched capacitor storage elements N per programmable switched capacitor bank. Conversely, for a given sample frequency F.sub.S, one may determine the required M and N values to achieve the desired maximum delay and desired incremental delay.

(38) Delay performance was verified across all delay settings, as illustrated in FIG. 5, using an RF input signal having a frequency F.sub.RFIN=1 GHz. The maximum achieved delay was 448.6 ns, the minimum achieved delay was 2.55 ns, and the delay slope showed the expected 2.42 ns/step (8/Fs) over a 175.9? delay range. Both the measured differential nonlinearity (DNL) and integral nonlinearity (INL) of the delay was less than ?4 ps across all delay codes, as illustrated in FIG. 6. The measured delay response was relatively flat at minimum and maximum delay settings across a 0.2-to ?2 GHz input frequency (F.sub.RFIN) range, as illustrated in FIGS. 7A, 7B, respectively, with the delay variation at the maximum delay being less than 0.12%.

(39) FIGS. 8A-8D illustrate the measured gain, noise figure (NF), matching (input S11/output S22), and power consumption breakdown, respectively, for the programmable delay device illustrated in FIG. 4. The programmable delay device achieved 24 dB of gain, a 1.1 GHz3 dB bandwidth, and a 7.1 dB NF at its maximum delay setting. The programmable delay device achieved less than 0.1 dB difference in both gain and NF at its minimum delay setting, demonstrating successful sample leakage mitigation. Gain flatness across any 100 MHz bandwidth was better than ?0.5 dB across 0.2to ?2 GHz frequency range. As will be appreciated by one of ordinary skill in the art, the bandwidth and flatness can be further improved by increasing the sampling frequency F.sub.S to reduce the Sinc roll-off in the zero-order hold operation. The measured gain dropped by 1 dB (i.e., IP1 dB) for input RF signals having ?27 dBm and ?25 dBm at 1 GHz and 2 GHz, respectively, dominated by the device output buffer 320. The measured S11 (S22) magnitude for the programmable delay device input (output) were less than ?10 dB over the 0.2to ?3 GHz frequency range. The measured S11 magnitude for the clock input, including an open-stub board match, was less than ?10 dB over the 3.5to ?9 GHz frequency range. The programmable delay device consumed a total of 80 mW from a 1V supply, the vast majority consumed by the buffers 306, 310, 314, 316, and 318, and the clocks 332-344. The LNA 304 and the device output buffer 320 consumed comparatively little power.

(40) Table 2 provides performance details comparing one embodiment of the present invention with various prior art delay devices. In Table 2, ISSCC 2021 corresponds to Nagulu, ISSCC 2012 corresponds to Garakoui, JSSC 2017 corresponds to Mondal, and SSCL 2020 corresponds to M. Li et al., An 800-ps Origami True-Time-Delay-Based CMOS Receiver Front End for 6.5-9-GHz Phased Arrays, IEEE Solid-State Circuit Letters, vol. 3, pp. 382-385 (2020), the contents of which are incorporated herein by reference. As shown in Table 2, this implemented embodiment of the present invention yielded a factor of 9? improvement in area efficiency and nearly a factor of 60? increase in maximum delay relative to the best prior art.

(41) TABLE-US-00002 TABLE 2 Delay device performance comparison. Present ISSCC ISSCC JSSC SSCL Invention 2021 2012 2017 2020 Design Delay SIC 4 Channel Delay Delay Element Receiver Beamformer Element Element + Attenuator Archi- TIMS Switched- G.sub.m-C G.sub.m-C Delay Line tecture Switched-Cap Cap Delay 0.2-2.0 GHz 0.1-1.0 GHz 1.0-2.5 GHz 0.1-2.0 GHz 6.5-9.0 GHz Frequency Range 3 dB 0.2-1.1 GHz.sup.a 0.1-0.5 GHz.sup.b 1.0-2.5 GHz 0.1-2.0 GHz 6.5-9.0 GHz Bandwidth Max Delay 448.6 ns.sup.a 7.75 ns.sup.b 0.55 ns 1.7 ns 0.8 ns Delay per 330 ns/mm.sup.2,a 37 ns/mm.sup.2,b 7.9 ns/mm.sup.2 5.9 ns/mm.sup.2 0.4 ns/mm.sup.2 Unit Area Delay 175.9x 31x.sup.b 39.3x.sup.c 6.8x 32x.sup.c Range Gain 24 dB ?18 dB.sup.b 12 dB 0.6 dB 18 dB Noise 7.1 dB 8.0 dB 23 dB 3.6 dB Figure IP1dB ?27 dBm ?21 dBm ?13 dBm ?17 dBm Power 80 mW.sup.a 7.4 mW.sup.b 90 mW.sup.d 364 mW 107 mW Tech- 45 nm 65 nm 140 nm 130 nm 65 nm nology SOI CMOS CMOS CMOS CMOS CMOS Delay 1.36 mm.sup.2 0.21 mm.sup.2,b 0.07 mm.sup.2 0.29 mm.sup.2 2.25 mm.sup.2 Active Area .sup.aFs = 3.3 GHz, .sup.bMax delay element, .sup.cBased on delay step, .sup.dSingle channel

(42) Additional characterization of the programmable delay device 300 revealed higher than desired clock feed-through to the RF output 322 and relied on off-chip currents to properly bias the on-chip amplifiers. This led to a second programmable delay device 900 in accordance with another embodiment of the present invention. FIG. 9 illustrates this programmable delay device 900. As most of the features of the programmable delay device 900 are the same as the original programmable delay device 300, only the differences will be described.

(43) Since complementary switches were employed in the switched-capacitor circuit switches and the chosen CMOS process has equal strength PMOS and NMOS devices, extremely small clock feed-through was found from this mechanism in the original programmable delay device 300. Simulation of DC offsets in the buffers, including buffers 310 and device output buffers 318, employed within the switched-capacitor circuits were found to produce the clock feed-through levels found in the original programmable delay device 300. Specifically, buffers 310 and device output buffers 318 created the largest spurious tones at F.sub.S/8 since they repeat every 8 clock cycles. The self-biased inverter load 316 also shares the F.sub.S/8 response since there are only 8 in the original programmable delay device 300. The delay buffers 314 produced negligible spurious tones since they only repeat once every 1480 clock cycles and each of the delay buffers 314 produces a random DC offset value.

(44) To reduce DC offsets in the amplifiers, two approaches were used. Since mismatch limited DC offsets are directly reduced through increased device sizing (width times length), the length of the amplifiers in both the buffers 910 and the self-biased inverter loads 920 were increased from 40 nm to 232 nm for a DC offset reduction of ?30?. The device output buffers 318 were completely removed and replaced with an intermediate buffer 940 after the output reconstruction switches 930 where a DC blocking capacitor could be employed to remove DC offset. The device output buffers 318 could be removed since the parasitic routing capacitance from the outputs of the delay buffers 314 to the output reconstruction switches 930 was significantly higher than the input capacitance of the device output buffers 318, therefore limiting memory effects and gain reduction from the removal of the output buffers 318. The intermediate buffer 940 is followed by an output buffer 950.

(45) The programmable delay device 900 includes an on-chip bandgap reference 960. This bandgap reference 960 provides all reference currents needed by the various RF circuits. The programmable delay device 900 includes the digital scan chain SPI interface 350, which enables programming of gain and calibration of the bandgap reference 960.

(46) Lastly, the divide-by-2 (F.sub.CLK=2F.sub.S) clock 332 has been upgraded. The clock divider 970 is now a programmable divide by 1/2/4 clock divider for greater flexibility. This upgraded clock divider 970 allows operation of the programmable delay device 900 over a wider range of applications operating at a wider range of clock frequencies F.sub.CLK.

(47) Characterization of the programmable delay device 900 showed several improvements over the original programmable delay device 300. F.sub.CLK was verified to properly operate from 2 GHz to 13 GHz with a minimum required input power of less than ?10 dBm. The supported ranges, combined with the on-chip programmable clock divider 970, provide system flexibility in clock frequency, delay range, and frequency coverage. At F.sub.S=3.3 GHz and F.sub.CLK=6.6 GHz, the device consumes 74 mW (3.5 mW LNA 304, 3.5 mW output buffer 950, 29 mW clocking, 38 mW delay buffers 304) from a 1V core supply and less than 250 ?W from a 1.8V supply used for digital I/O and the bandgap reference 960.

(48) Delay measurements were repeated inside a temperature chamber over a temperature range of ?40? C. to 85? C. as shown in FIG. 10A at the minimum delay over an RF input frequency range of 0.2-2 GHz. FIG. 10B illustrates the same test with the maximum delay. Delay performance was found to be maintained across the 125? C. temperature range, showing the robustness of the proposed delay approach.

(49) The noise figure was measured at room temperature and gain was verified over a temperature range of ?40? C. to 85? C. during the delay measurements as illustrated in FIGS. 11A and 11B, respectively. The programmable delay device 900 achieved a minimum noise figure of 7.4 dB which increases below 400 MHz due to flicker noise and above 1.1 GHz as device gain reduces. The gain is a maximum of 26 dB at room temperature and varies by ?2.4 dB over the full temperature range. The programmable delay device 900 achieved a 3-dB bandwidth of 1.1 GHz and less than 0.25 dB gain variation was observed between the maximum and minimum delay settings showing successful sample leakage mitigation. Gain flatness across any 100 MHz bandwidth was less than ?0.5 dB across 0.2-2 GHz. Bandwidth and flatness can be further improved by operating at F.sub.S greater than 3.3 GHz to reduce the Sinc roll-off inherent to the zero-order hold operation as described above. Input-referred P1 dB was ?29 dBm at 300 MHz and ?27 dBm at 1 GHz, dominated by the output buffer 950. S11/S22 was measured to be less than ?10 dB across 0.2-3 GHz for the RF input/output, and from 1-9 GHz for F.sub.CLK.

(50) FIGS. 12A and 12B illustrate the measured device output spectrum up to F.sub.S/2 given an input tone at 1 GHz with RF input signal levels of ?30 dBm (3 dB below P1 dB) and ?37 dBm (10 dB below P1 dB). The dominant clock spur is located at F.sub.S/8 at an output level of ?45 dBm (input-referred ?71 dBm) and broadband clock spurs are less than ?53 dBm (input-referred less than ?78 dBm) across the spectrum. This represents a 24 dB improvement in spurious performance at F.sub.S/8 compared to the original programmable delay device 300, showing successful implementation of DC offset mitigation approaches employed in the programmable delay device 900. Clock spurious limited spurious-free dynamic range (SFDR) is found to be a maximum of 44 dB, while overall SFDR including signal distortion is a maximum of 32 dB at an RF input signal level of ?34 dBm at 1 GHz. SFDR performance was measured to be constant across a temperature range of ?40? C. to 85? C.

(51) The invention may be embodied in other specific forms without departing from its spirit or essential characteristics. The described embodiments are to be considered in all respects only as illustrative and not restrictive. The scope of the invention is, therefore, indicated by the appended claims rather than by the foregoing description. All changes which come within the meaning and range of equivalency of the claims are to be embraced within their scope.