Arrangement For Current Sharing Of Parallel-Connected Inverters

Abstract

A power inverter system includes switching mode inverter legs connected in parallel between a common DC input and, via leg output inductors, a common phase output to feed a phase output current to a common load. The commutations of the parallel-connected inverter legs are initiated by essentially simultaneous commutation commands. The leg output current is sensed before and after a commutation in each of the parallel-connected inverter legs to obtain a pre-commutation current value and a post-commutation current value. Alternatively, a voltage pulse over the leg output inductor is sensed in each of the parallel-connected inverter legs during the commutation. A current sharing between the parallel-connected inverter legs is balanced by means of adjusting switching instants of main switches of the parallel-connected inverter legs for subsequent commutation autonomously in each of the parallel-connected inverter legs based on a difference between the pre-commutation and the post-commutation current values or based on the sensed voltage pulse of the respective parallel-connected inverter leg.

Claims

1. A power inverter system, comprising: two or more switching mode inverter legs connected in parallel between a common DC input and a common phase output to feed a phase output current to a common load, the phase output current being formed by combined leg output currents of the parallel-connected inverter legs, wherein commutations of the parallel-connected inverter legs are initiated by essentially simultaneous commutation commands, a control arrangement configured to balance current sharing between the parallel-connected inverter legs by means of adjusting switching instants of main switches of the parallel-connected inverter legs, wherein the control arrangement is configured to sense the leg output current before and after a commutation in each of the parallel-connected inverter legs to obtain a pre-commutation current value and a post-commutation current value, and wherein the control arrangement is configured to adjust switching instants of the main switches for subsequent commutation autonomously in each of the parallel-connected inverter legs based on a difference between the pre-commutation and the post-commutation current values of the respective parallel-connected inverter leg to control the difference towards zero, the difference being representative of a timing difference between switching instants of the respective parallel-connected inverter leg and at least one of the other parallel-connected inverter legs.

2. The power inverter system as claimed in claim 1, wherein, if a sign of the difference between the pre-commutation and the post-commutation current values is negative, the control arrangement is configured to adjust switching instants for subsequent commutation so as to increase the negative difference towards zero, and wherein, if a sign of the difference between the pre-commutation and the post-commutation current values is positive, the control arrangement is configured to adjust switching instants for subsequent commutation so as to decrease the positive difference towards zero.

3. The power inverter system as claimed in claim 1, wherein the sign of the difference between the pre-commutation and the post-commutation current values indicates whether the switching instant of the parallel-connected inverter leg is earlier or later relative to a corresponding switching instant of at least one of the other parallel-connected inverter legs, and wherein the control arrangement is configured to advance the switching instants of the main switch, if the sign of the difference between the pre-commutation and the post-commutation current values indicates the switching instant of the parallel-connected inverter leg is later relative to a corresponding switching instants of at least one other parallel-connected inverter leg.

4. The power inverter system as claimed in claim 1, wherein the control arrangement is configured to carry out the sensing and adjustment of the switching instants during all commutations or during a selected portion of the commutations.

5. The power inverter system as claimed in claim 1, wherein the control arrangement is configured to carry out the sensing at each turn-on and turn-off of the main switches.

6. The power inverter system as claimed in claim 1, wherein the control arrangement is configured to adjust the switching instants of the main switches to control the commutation-induced current difference or a timing difference in an individual commutation towards zero but not to zero thereby causing a stepwise swing of a phase output voltage of the inverter system during an individual commutation.

7. The power inverter system as claimed in claim 11, wherein the control arrangement is configured to adjust the switching instant of the main switches to control the commutation-induced current difference or a timing difference in an individual commutation towards zero to a non-zero value or to a predetermined non-zero value that is equal for turn-on and turn-off of the main switches, thereby causing a stepwise swing of a phase output voltage of the inverter system during an individual commutation.

8. The power inverter system as claimed in claim 1, wherein the control arrangement comprises a leg-specific controller for each of the two or more parallel-connected inverter legs to adjust the switching instants of the main switches.

9. The power inverter system as claimed in claim 1, wherein the power inverter system comprises two or more inverters, each of the inverters having one or more inverter phase legs, wherein the parallel-connected inverter legs are the corresponding inverter phase legs of the two or more inverters modules connected in parallel.

10. The power inverter system as claimed in claim 9, wherein the control arrangement comprises inverter-specific switching controllers for the two or more inverters, each of the inverter-specific switching controllers being configured to provide the autonomous adjustment of switching instants for each of the inverter phase legs of the respective inverter.

11. A power inverter system, comprising: two or more switching mode inverter legs connected in parallel between a common DC input and, via leg output inductors, a common phase output to feed a phase output current to a common load, the phase output current being formed by combined leg output currents of the parallel-connected inverter legs, wherein commutations of the parallel-connected inverter legs are initiated by essentially simultaneous commutation commands, a control arrangement configured to balance current sharing between the parallel-connected inverter legs by means of adjusting switching instants of main switches of the parallel-connected inverter legs, wherein the control arrangement is configured to sense a voltage pulse over the leg output inductor in each of the parallel-connected inverter legs during the commutation, and wherein the control arrangement is configured to adjust the switching instants autonomously in each of the parallel-connected inverter legs based on the duration and/or sign of the sensed output inductor voltage pulse or an integral of the voltage pulse of the respective parallel-connected inverter leg to control the magnitude and direction of a commutation-induced current difference towards zero.

12. The power inverter system as claimed in claim 11, wherein the integral of the sensed voltage pulse represents a magnitude of the commutation-induced current difference in the parallel-connected inverter leg.

13. The power inverter system as claimed in claim 11, wherein the duration of the sensed voltage pulse represents a timing difference of a switching instant of the parallel-connected inverter leg relative to a corresponding switching instant of at least one other parallel-connected inverter leg.

14. The power inverter system as claimed in claim 11, wherein the sign of the sensed voltage pulse indicates whether the switching instant of the parallel-connected inverter leg is earlier or later relative to a corresponding switching instant of at least one other parallel-connected inverter leg.

15. The power inverter system as claimed in claim 11, wherein the control arrangement is configured to advance the switching instant of the parallel-connected inverter leg, if the sign of the voltage pulse indicates the switching instant of the parallel-connected inverter leg is later relative to a corresponding switching instant of at least one other parallel-connected inverter leg; and wherein the control arrangement is configured to delay the switching instant of the parallel-connected inverter leg, if the sign of the voltage pulse indicates the switching instant of the parallel-connected inverter leg is earlier relative to a corresponding switching instant of at least one other parallel-connected inverter leg.

16. The power inverter system as claimed in claim 11, wherein the control arrangement is configured to carry out the sensing and adjustment of the switching instants during all commutations or during a selected portion of the commutations.

17. The power inverter system as claimed in claim 11, wherein the control arrangement is configured to carry out the sensing at each turn-on and turn-off of the main switches.

18. The power inverter system as claimed in claim 11, wherein the control arrangement is configured to adjust the switching instants of the main switches to control the commutation-induced current difference or a timing difference in an individual commutation towards zero but not to zero thereby causing a stepwise swing of a phase output voltage of the inverter system during an individual commutation.

19. The power inverter system as claimed in claim 11, wherein the control arrangement is configured to adjust the switching instant of the main switches to control the commutation-induced current difference or a timing difference in an individual commutation towards zero to a non-zero value or to a predetermined non-zero value that is equal for turn-on and turn-off of the main switches, thereby causing a stepwise swing of a phase output voltage of the inverter system during an individual commutation.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In the following the invention will be described in greater detail by means of exemplary embodiments with reference to the accompanying drawings, in which:

[0031] FIG. 1 is a block diagram that schematically illustrates an exemplary inverter system having a plurality of parallel-connected inverters;

[0032] FIG. 2 is a schematic of an exemplary inverter system having two parallel-connected inverters;

[0033] FIG. 3 is a schematic block diagram of an exemplary embodiment of a switching controller;

[0034] FIGS. 4A-4G illustrate an example of principal waveforms for the gate control signals at turn-on and turn-off off for upper switches and for corresponding leg output currents, voltages across output inductors and an inverter output voltage of two parallel-connected inverter legs of FIG. 2;

[0035] FIG. 5 is a flow diagram illustrating an exemplary procedure for an autonomous switching timing adjustment of parallel-connected inverter legs based on measuring output current before and after the commutation; and

[0036] FIG. 6 is a flow diagram illustrating an exemplary procedure for an autonomous switching timing adjustment of parallel-connected inverter legs based on measuring a voltage across an output inductor during the commutation.

DETAILED DESCRIPTION

[0037] FIG. 1 shows a block diagram that schematically illustrates an exemplary inverter system having a plurality of (i.e., two or more) inverters INV1, INV2, . . . , INVN connected in parallel from their DC side (e.g., DC link) input terminals (e.g., dc+, dc?) and their AC side output terminals (e.g., U.sub.1, V.sub.1, W.sub.1, U.sub.2, V.sub.2, W.sub.2). In the illustrated example, the inverters INV1 and INV2 are three-phase inverters providing three phase outputs U.sub.1, V.sub.1, W.sub.1 and U.sub.2, V.sub.2, W.sub.2, but it should be appreciated that parallel-connected inverters may be implemented as single-phase inverters, or generally include any number of inverter phases or phase legs. The parallel-connected inverters are fed by a common DC voltage source 4 with voltage U.sub.dc, and inverters are feeding a common AC load 6. A typical application area of the parallel-connected inverters fed by a common DC voltage source 4 is an electric motor drive having an AC electric motor as a common load 6. It should be noted that the load 6 does not have to be of AC type. It can be DC as well, for example a battery energy storage or similar. Parallel connected inverter phase legs apply this invention similarly, regardless of the load type. There is a non-zero impedance at each phase output of the inverters, represented by inductances L.sub.o in FIG. 1. The output inductances Lo may be intentionally implemented (e.g., an inductor, a coil, a choke, etc.) or it may be just some leakage impedance of practical components and materials, such as cabling. The output inductances Lo may be substantially equal, but it must not necessarily be so. The corresponding phase outputs U.sub.1, U.sub.2, V.sub.1, V.sub.2, and W.sub.1, W.sub.2 of the parallel-connected inverters INV1 and INV2 are connected through the output inductances Lo to the common phase outputs U, V, and W, respectively. The corresponding phase outputs U.sub.1, U.sub.2, V.sub.1, V.sub.2, and W.sub.1, W.sub.2 of the parallel-connected inverters INV1 and INV2 may be connected together right after the output inductances Lo, and a single cable or multiple cables per phase U, V, and W may be used to connect the phase outputs to the load 6. Alternatively, each parallel-connected inverter INV1 and INV2 can be connected by means of its own cabling to the load 6, and the phase outputs U.sub.1, U.sub.2, V.sub.1, V.sub.2, and W.sub.1, W.sub.2 can be connected in parallel first at the terminals of the load 6. Output phase current Io of each phase U, V, W supplied to the load 6 is formed by combining phase output currents I.sub.o1 and I.sub.o2 of the respective phase outputs U.sub.1, U.sub.2, V.sub.1, V.sub.2, and W.sub.1, W.sub.2 of the parallel-connected inverters INV1 and INV2. The common DC supplied parallel-connected inverters INV1 and INV2 can be controlled to act like one high power inverter. This can be achieved by controlling the parallel inverters with essentially same control commands.

[0038] Each inverter INV1 and INV2 may have one or more half bridge legs, which can be functionally independent of each other or parallel connected inside an inverter (INV1 or INV2). The functionally similar bridge legs of the same phase of different inverters (INV1 and INV2) are connected in parallel with one another. Each bridge circuit can include a plurality of electronic switching elements or devices (e.g. insulated gate bipolar transistors (IGBTs)) that operate in a switch mode, meaning that that they are controlled to transition from a blocking state (OFF state) to a conducting state (ON state), and vice-versa, by providing control pulses (often called switching control signals or gating signals) at a high switching frequency. In a PWM modulation scheme, the width of control pulses provided to the control inputs of the switching devices is varied to provide a desired output of the inverter. The parallel-connected inverters INV1 and INV2 may have a common switching control (e.g., as a part of the higher level control 86 in FIG. 1) that provides switching signals or gating signals to operate switching devices of all inverters, or each parallel-connected inverter INV1 and INV2 may have a dedicated switching control unit 8.sub.1 and 8.sub.2 that provides switching signals or gating signals to operate switching devices of the respective inverter, as illustrated in FIG. 1. Alternatively, the control may be distributed among a common switching control unit and inverter-specific switching control units. In the latter cases, the inverters may be normal inverters (i.e., that can be used as single units) that can be connected in parallel as such. In embodiments, the switching control(s) 8.sub.1 and 8.sub.2 of the parallel-connected inverters INV1 and INV2 may be controlled by a higher-level control system 86 with simultaneous and essentially similar control signals or commands.

[0039] In embodiments, the higher-level control system 86 may be an electric motor control system or similar. It can also include a common PWM generation function (for example, a PWM modulator) for all system elements and phases.

[0040] The schematic of an exemplary inverter system (e.g., single-phase inverter system) having two inverters INV1 and INV2 connected in parallel is illustrated in FIG. 2 and described herein in order to alleviate comprehending operation and configuration of embodiments of the invention in relation to exemplary basic parallel-connected inverters. It is not intended to limit embodiments of the invention to the described and illustrated exemplary inverters. It shall be appreciated that the current sharing control according to embodiments of the invention is universally applicable to any number of parallel inverters, any type of inverters and their derivates and modifications regardless the specific design, configuration, and operation variations of an inverter from the exemplary inverter.

[0041] The parallel-connected inverters INV1 and INV2 may preferably be identical inverters having the same configuration and operation. The inverters INV1 and INV2 comprise power switching sections 10, such as half-bridge circuits, and dc-link rails 22 (positive dc-link potentials P) are connected to a first voltage terminal U.sub.dc+ of the common DC power source 4, and dc-link rails 24 (negative dc-link potentials N) are connected to a second voltage terminal U.sub.dc? of the common DC power source 4. The output node 110 of each power switching section 10 can be connected through the corresponding output inductance L.sub.o1 and L.sub.o2 to the corresponding phase terminal of an ac load 6, such as an ac motor or ac grid or any applicable electric load. and thereby the corresponding phase outputs 110 of the inverters INV1 and INV2 (e.g., phase legs U.sub.1 and U.sub.2) are connected in parallel via L.sub.o1 and L.sub.o2. It should be appreciated that although a half-bridge inverter is illustrated as an example herein, the inverter may have other configurations, particularly a full-bridge configuration.

[0042] The common dc power input to the parallel-connected inverters INV1 and INV2 may be obtained from any kind of a dc power source 4, such as from an existing power supply network through a rectifier, or from a battery, fuel cell, photovoltaic array, etc. It shall be appreciated that dc-link 2 may be provided in several forms and may have a number of voltages and other attributes. It shall also be appreciated that the voltage difference between positive and negative dc-link rails is flexible, depending on how the dc-link 2 is fed. It shall be further appreciated the term bus may be utilized in place of the term link such that, for example, references to a dc-link are understood to encompass a dc-bus and vice versa.

[0043] It should be appreciated that although a single-phase inverter is illustrated as an example herein, an inverter may be implemented as a three-phase inverter, or generally include any number of inverter phases or phase legs. For example, inverters INV1 and INV2 illustrated in FIG. 2 may be implemented as three-phase inverters including a power section 10.sub.U, 10.sub.V and 10.sub.W for each phase or phase leg U.sub.1, U.sub.2, V.sub.1, V.sub.2, W.sub.1 and W.sub.2, respectively. Operation and configuration of the other phases or phase legs V.sub.1, V.sub.2, W.sub.1 and W.sub.2 of the inverters INV1 and INV2 can be identical to the operation and configuration described for the phases or phase legs U.sub.1 and U.sub.2 above.

[0044] In embodiments, three-phase inverters INV1 and INV2 may each comprise a dc-link with dc-link capacitors (e.g., a dc-link illustrated in FIG. 3) common to all the power sections 10.sub.U, 10.sub.V and 10.sub.W of the respective inverter.

[0045] In embodiments, all power sections 10.sub.U, 10.sub.V and 10.sub.W of phase legs U.sub.1, V.sub.1 and W.sub.1 in the inverter INV1 may be controlled by the same inverter-specific switching controller 8.sub.1. Similarly, in embodiments, all power sections 10.sub.U, 10.sub.V and 10.sub.W of phase legs U.sub.2, V.sub.2 and W.sub.2 in the inverter INV2 may be controlled by the same inverter-specific switching controller 8.sub.2.

[0046] FIG. 3 is a schematic block diagram of an exemplary embodiment of a switching controller 8.sub.1 or 8.sub.2 having switching control function 84 that includes a dedicated switching control module 841A, 841B, and 841C adapted to provide control signals, such as G.sub.1, G.sub.2, . . . , G.sub.n to each phase leg U.sub.1, V.sub.1 and W.sub.1, respectively, based on a respective PWM signal PWM.sub.U, PWM.sub.V and PWM.sub.W received from a PWM modulator. The PWM modulator may be common for all parallel-connected inverters INV1 . . . . INVn (e.g., as a part of the higher-level control 86 in FIG. 1, and the PWM commands may be sent via a communication link to the inverters. In embodiments, a leg-specific output current sensing and/or a leg-specific inductor voltage sensing feedback FD may be provided for each leg-specific switching control module 841A, 841B, and 841C. In embodiments, a leg-specific current balancing may be included in the switching control 84, and particularly in the leg-specific switching control modules 841A, 841B, and 841C. In embodiments, a leg-specific current balancing may be implemented by means of Field Programmable Gate Arrays (FPGAs).

[0047] Referring again to FIG. 2, the exemplary half-bridge power section 10 of the inverter INV1 illustrated in FIG. 2 includes a pair of main or power switching devices S.sub.11 and S.sub.21 coupled in parallel to the dc-link rails 22 and 24. The first (upper) main switching device S.sub.11 may have a first terminal electrically coupled to the positive dc-link rail 22 and a second terminal electrically coupled to an output node 110. The second (lower) main switching device S.sub.21 having a first terminal coupled to output node 110 and a second terminal coupled to the negative dc-link rail 24. Across the upper main switching device S.sub.11 between the positive dc-link rail 22 and the output node 110 is connected a first antiparallel diode D.sub.11, and across the lower main switching device S.sub.21 between the output node 110 and the negative dc-link rail 24 is connected a second antiparallel diode D.sub.21. The upper main switching device S.sub.21 is operable to turn on and turn off, and thereby to respectively connect and disconnect the dc-link rail 22 and the output node 110, in response to control signal(s) G.sub.11 received from a control and driver circuitry, such as an inverter-specific switching controller 8.sub.1 illustrated in FIG. 2. The lower main switching device S.sub.21 is operable to turn on and turn off, and thereby to respectively connect and disconnect the dc-link rail 24 and the output node 110, in response to control signal(s) G.sub.21 received from the control and driver circuitry, such as the switching controller 8.sub.1. Similarly, the exemplary half-bridge power section 10A of the inverter INV2 illustrated in FIG. 2 includes a pair of main or power switching devices S.sub.12 and S.sub.22, a first antiparallel diode D.sub.12, a second antiparallel diode D.sub.22, and switching control signals G.sub.12 and G.sub.22 from a control and driver circuitry, such as an inverter-specific switching controller 8.sub.2. In embodiments, the switching devices S.sub.11, S.sub.12, S.sub.21 and S.sub.22 may be insulated gate bipolar transistors (IGBT), or other type of semiconductor switching devices, such as integrated gate-commutated thyristors (IGCT), metal-oxide-semiconductor field-effect transistors (MOSFET), or silicon carbide (SIC) MOSFETs to name several examples.

[0048] In operation, when the output current I.sub.o is positive (I.sub.o1>0, I.sub.o2>0) and the upper main switch S.sub.11/S.sub.12 is turned on (to a conductive state), a first switch current I.sub.s11/I.sub.s12 can flow between the dc-link rail 22 and the output node 110. Similarly, when the output current I.sub.o is negative (I.sub.o1<0, I.sub.o2<0) and the lower main switching device S.sub.21/S.sub.22 is turned on (to a conductive state), a second switch current I.sub.s21/I.sub.s22 can flow between the output node 110 and the dc-link rail 24. On the other hand, when the upper switching device S.sub.11/S.sub.12 is turned off (to a non-conductive state), the first switch current I.sub.s11/I.sub.s12 will not flow in the switch-forward direction between the dc-link rail 22 and the output node 110, although a current I.sub.d11/I.sub.d12 may flow in the switch-reverse direction through the first anti-parallel diode D.sub.11/D.sub.12 of the upper main switching device S.sub.11/S.sub.12, if the output current Io is negative (I.sub.o1<0, I.sub.o2<0). Similarly, when the lower main switching device S.sub.21/S.sub.22 is turned off (to a non-conductive state), the second switch current I.sub.s21/I.sub.s22 will not flow in the switch-forward direction between the output node 110 and the dc-link rail 24, although a current I.sub.d21/I.sub.d22 may flow in the switch-reverse direction through the anti-parallel diode D.sub.21/D.sub.22 of the lower switching device S.sub.21/S.sub.22, if the output current I.sub.o is positive (I.sub.o1>0, I.sub.o2>0). Thus, by turning on and off and closing the upper main switching device S.sub.11/S.sub.12 and the lower main switching device S.sub.21/S.sub.22, the output voltage at the output node 110 will be controlled or commutated to be either the potential P from the dc-link rail 22 or the potential N from the dc-link rail 24.

[0049] More specifically, when the output current I.sub.o is positive (I.sub.o1>0, I.sub.o2>0), it is the upper switches S.sub.11 and S.sub.12 that commutate their currents (I.sub.s11 and I.sub.s12, respectively) to diodes D.sub.21 and D.sub.22, respectively, and the output voltage U.sub.o swings from the potential P (the dc-link 22) to the potential N (the dc-link 24). When the output current Io is negative (I.sub.o1<0, I.sub.o2<0), it is the lower switches S.sub.21 and S.sub.22 that commutate their currents (I.sub.s21 and I.sub.s22, respectively) to diodes D.sub.11 and D.sub.12, respectively, and the output voltage U.sub.o swings from the potential N (the dc-link 24) to the potential P (the dc-link 22).

[0050] The commutation for a corresponding phase in the plurality of parallel-connected inverters, e.g., for the phase U.sub.1 of the inverter INV1 and the phase U.sub.2 of the inverter INV2, can be initiated by similar commutation commands at the same time instant. In an ideal case, the output currents I.sub.o1 and I.sub.o2 of the parallel-connected inverters would be equal and their difference or a differential output current I.sub.do would be zero, (e.g., I.sub.do=I.sub.o1?I.sub.o2=0). However, the ideal behavior during commutations would require that the corresponding switches, e.g., upper switches S.sub.11 and S.sub.12, in the parallel operated inverters turn on at the same instant when commutating the output potential U.sub.o, for example from N to P. Likewise, the corresponding switches, e.g., upper switches S.sub.11 and S.sub.12, in the parallel operated inverters should turn off at the same instant when commutating the output potential, for example from P to N. Unfortunately, the parallel operated inverters do not behave similarly, for example due to parameter differences of switch components and differing impedances in parallel branches, the output currents from the parallel inverters can be unequal in magnitude, and a current difference, here defined as I.sub.do=I.sub.o1?I.sub.o2?0, will evolve. In other words, there can be uneven current sharing between the inverters. Due to thermal and economic reasons, it is of utmost importance that the parallel-connected inverters share the load current as evenly as possible.

[0051] According to an aspect of the invention, a current sharing between the parallel-connected inverter legs is balanced by means of adjusting switching instants of main switches of the parallel-connected inverter legs, by a control arrangement, such as the switching controls functions 84 or switching control module 841.sub.U, 841.sub.V, and 841.sub.W. The control arrangement may sense the leg output current before and after a commutation in each of the parallel-connected inverter legs to obtain a pre-commutation current value and a post-commutation current value, and the control arrangement may adjust switching instants of the main switches for next commutation autonomously in each of the parallel-connected inverter legs based on a difference between the pre-commutation and the post-commutation current values of the respective parallel-connected inverter leg to control the difference towards zero, the difference being representative of a timing difference and/or a commutation-induced current difference between the respective parallel-connected inverter leg and at least one of the other parallel-connected inverter legs. Thereby, the control arrangement can balance the current sharing by fine tuning the switching instants which may otherwise be generated in a conventional manner.

[0052] Let us examine the situation for a case where the output current I.sub.o is positive (I.sub.o1>0, I.sub.o2>0) in the exemplary inverter system shown in FIG. 2, i.e., the upper switches S.sub.11 and S.sub.12 commutate their currents (I.sub.s11 and I.sub.s12, respectively) to diodes D.sub.21 and D.sub.22, respectively.

[0053] FIGS. 4A-4F illustrate an example of principal wave forms for the gate control signals G.sub.11 and G.sub.12 at turn-on and turn-off off for upper switches S.sub.11 and S.sub.12 of both half-bridges, together with corresponding current and voltage wave forms of Io.sub.1, Io.sub.2, U.sub.L1 and U.sub.L2. An example of a principal wave form of the output voltage U.sub.o of the inverter system, referred to N potential is also shown in FIG. 4G. In FIG. 4A, the gate signal G.sub.11 causes the upper switch S.sub.11 to turn on (N to P commutation) at a turn-on instant t.sub.onS11 and to turn off (P to N commutation) at turn-off instant t.sub.offS11. Similarly, in FIG. 4B, the gate signal G.sub.12 causes the upper switch S.sub.12 to turn on (N to P commutation) at a turn-on instant t.sub.onS12 and to turn off (P to N commutation) at turn-off instant t.sub.offS12.

[0054] Let us also define the timing difference ?t of the parallel-connected inverter legs for turn-on and turn-off as

[00001]$\begin{array}{cc}?t_{\mathrm{on}}=t_{\mathrm{onS}12}-t_{\mathrm{onS}11}& \left(1\right)\end{array}$$\begin{array}{cc}?t_{\mathrm{off}}=t_{\mathrm{offS}12}-t_{\mathrm{offS}11}& \left(2\right)\end{array}$

[0055] wherein [0056] t.sub.onS11 is a turn-on instant of S.sub.11 [0057] t.sub.onS12 is a turn-on instant of S.sub.12 [0058] t.sub.offS11 is a turn-off instant of S.sub.11 [0059] t.sub.offS12 is a turn-off instant of S.sub.12.

[0060] If there is a difference of magnitude ?t in either the turn-on instants or the turn-off instants of the upper switches S.sub.11 and S.sub.12, a differential current increment ?I.sub.d will be induced into the circuit, as illustrated in FIGS. 4C and 4D. The increment ?I.sub.d is the change of the differential current I.sub.d during the commutation. The magnitude of the increment will be

[00002]$\begin{array}{cc}?I_d=\frac{?{\mathrm{tU}}_{\mathrm{dc}}}{L_{o1}+L_{o2}}& \left(3\right)\end{array}$

[0061] wherein [0062] ?t is ?t.sub.on or ?t.sub.off [0063] U.sub.dc is the dc link voltage (known or measured) [0064] L.sub.o1 and L.sub.o2 are output inductances.

[0065] It can be seen in equation (3) that the differential current increment ?I.sub.d is directly proportional to the timing difference ?t. The sign of ?I.sub.d in the parallel-connected inverter leg INV1 will depend on whether ?I.sub.d was during turn-on or turn-off of the switches, and whether S.sub.11 was switching earlier or later than S.sub.12 (i.e., the sign of ?t) as shown in Table I below. Similarly, the sign of of ?I.sub.d in the parallel-connected inverter leg INV2 for S.sub.12 is shown in Table II below. It can be seen that the sign of ?I.sub.d and the sign of ?t in one of the parallel-connected inverter legs INV1 and INV2 are opposite to those in the other one of the parallel-connected inverter legs INV1 and INV2. The Tables I and II represent the same situation but from perspective of different inverter INV1 and INV2, respectively. The top row of Table I and bottom row of Table II describe the same situation and they have opposite polarity for the differential current increment ?I.sub.d. Same applies for bottom row of Table I and top row of Table II. Similar tables can be readily provided for a case where the output current I.sub.o is negative (I.sub.o1<0, I.sub.o2<0) in the exemplary inverter system shown in FIG. 2, i.e., the lower switches S.sub.21 and S.sub.22 commutate their currents (I.sub.s21 and I.sub.s22, respectively) to upper diodes D.sub.11 and D.sub.12, respectively.

TABLE-US-00001 TABLE I Turn-on Turn-off INV1 (U.sub.o from N to P) (U.sub.o from P to N) S.sub.11 turns on or off before ?I.sub.d > 0 ?I.sub.d < 0 S.sub.12 (?t.sub.on > 0 or ?t.sub.off > 0) S.sub.11 turns on or off after ?I.sub.d < 0 ?I.sub.d > 0 S.sub.12 (?t.sub.on < 0 or ?t.sub.off < 0)

TABLE-US-00002 TABLE II Turn-on Turn-off INV2 (U.sub.o from N to P) (U.sub.o from P to N) S.sub.12 turns on or off before ?I.sub.d > 0 ?I.sub.d < 0 S.sub.11 (?t.sub.on > 0 or ?t.sub.off > 0) S.sub.12 turns on or off after ?I.sub.d < 0 ?I.sub.d > 0 S.sub.11 (?t.sub.on < 0 or ?t.sub.off < 0)

[0066] In the example shown in FIGS. 4A-4G, the switch S.sub.11 is early to turn on and early to turn off relative to the switch S.sub.12. Thus, in the leg INV1, the leg output current I.sub.o1 increases by ?I.sub.d (?I.sub.d>0) at turn-on of S.sub.11 and decreases by ?I.sub.d (?I.sub.d<0) at turn-off of S.sub.11 (FIG. 4C). In the leg INV2, the leg output current I.sub.2 decreases by ?I.sub.d (?I.sub.d<0) at turn-on of S.sub.12 and increases by ?I.sub.d (?I.sub.d>0) at turn-off of S.sub.12 (FIG. 4D). For simplicity, the timing difference ?t is drawn to be as long both in turn-on and turn-off in FIGS. 4A-4G so that in this example the differential current changes cancel each other out. If the timing differences ?t at turn-on and turn-off were not equal in durations, the changes would not cancel each other.

[0067] In embodiments, each parallel-connected inverter leg (INV1, INV2, . . . , INVn), preferably the corresponding switching control (8.sub.1, 8.sub.2, . . . , 8.sub.n) thereof, is arranged to sense or measure its leg output current (I.sub.o1, I.sub.o2, . . . , I.sub.0n) before (step 62 in FIG. 5) and after (step 64) the commutation (step 63) to obtain a pre-commutation output current sample (I.sub.o1(pre), I.sub.o2(pre), . . . , I.sub.on(pre and a post-commutation output current sample (I.sub.o1(post), I.sub.o2(post), . . . , I.sub.on(post)). This way each parallel-connected inverter leg (INV1, INV2, . . . , INVn), preferably the switching control (8.sub.1, 8.sub.2, . . . , INVn) thereof, can acquire the increment ?I.sub.d as differences ?I.sub.o1=I.sub.o1(post)?I.sub.o1(pre), ?I.sub.o2=I.sub.o2(post)?I.sub.o2(pre), . . . , ?I.sub.on=I.sub.on(post)?I.sub.on(pre), respectively (step 65). The sign of the difference ?I.sub.o1, ?I.sub.o2, . . . , ?I.sub.on in each parallel-connected inverter leg will indicate the sign of the timing difference ?t in the respective leg, i.e., whether the switching instant of the respective parallel-connected inverter leg is earlier or later relative to a corresponding switching instant of at least one of the other parallel-connected inverter legs.

[0068] Further, the differences ?I.sub.o1, ?I.sub.o2, . . . , ?I.sub.on will be of opposite sign in the parallel-connected inverters having a timing difference, as illustrated in Tables I and II. Hence, based on the sign of the difference ?I.sub.o1, ?I.sub.o2, . . . , ?I.sub.on (or the sign of ?t) in the respective parallel-connected leg (step 66), each parallel-connected inverter INV1, INV2, . . . , INVn can deduce that its own ?t must have been positive (>0) (e.g., its timing has been early) or its ?t must have been negative (<0) (e.g., its timing has been late). Each parallel-connected inverter leg INV1, INV2, . . . , INVn can now make an adjustment to its turn-off instant t.sub.off or turn-on instant t.sub.on in such way that the adjustment either increases ?I.sub.d (?t) from negative towards zero (step 67) or decreases ?I.sub.d (?t) from positive towards zero (step 68). If the difference ?I.sub.o (or ?t) is approximately zero, no timing adjustment may be needed (step 69). The sensing, analysis and adjustment is preferably carried out for each commutation event, i.e., every turn-on or turn-off of the switch (every N to P or P to N commutation). The adjusted t.sub.off or t.sub.on can be used in in a subsequent (in the next, for example) turn-off or turn-on of the switch. In embodiments, the adjustments may be stored and further adjusted in the subsequent commutations, e.g., using an integral action controller. In embodiments, if a less optimal adjustment is satisfactory, sensing, analysis and adjustment may not be carried out for each commutation event as in an optimal adjustment but for a selective portion all commutations, such as for sequentially selected commutations, for certain commutations only, or for alternating commutations.

[0069] In embodiments, also a duration of the timing difference ?t can be estimated from the difference ?I.sub.o1, ?I.sub.o2, . . . , ?I.sub.on (step 66 in FIG. 5), e.g., using equation (3). The duration of the timing difference ?t can be used in determining the amount of adjustment of the turn-off instant t.sub.off or turn-on instant t.sub.on in the adjustment steps 67 and 68, for example.

[0070] The leg output currents I.sub.o1, I.sub.o2, . . . , I.sub.on may be measured in various alternative ways obvious for a person skilled in the art, such as using a shunt current measurement or magnetic sensors. The pre-commutation current values I.sub.o1(pre), I.sub.o2(pre), . . . , I.sub.on(pre and the post-commutation current values I.sub.o1(post), I.sub.o2(post), . . . , I.sub.on(post) can be sampled either in an analogue circuit or a digital circuit. An existing current measurement needed for other control purposes in an inverter leg may also be used for the purposes of the present invention, if the filtering and limited sampling rate of the current did not deteriorate the useful signal for the extraction of I.sub.o(post)?I.sub.o(pre).

[0071] According to an aspect of the invention, a control arrangement, such as the switching controls functions 84 or switching control module 841.sub.U, 841.sub.V, and 841.sub.W, is configured to sense a voltage pulse over the leg output inductor in each of the parallel-connected inverter legs during the commutation, and the control arrangement is configured to adjust the switching instants autonomously in each of the parallel-connected inverter legs based on the duration and/or sign of the sensed output inductor voltage pulse or an integral of the voltage pulse of the respective parallel-connected inverter leg to control the magnitude and direction of a commutation-induced current difference towards zero. Thereby, the control arrangement can balance the current sharing by fine tuning the switching instants which may otherwise be generated in a conventional manner.

[0072] Referring to the exemplary inverter system shown in FIG. 2, the inverter leg INV1, INV2, . . . , INVn may monitor a voltage U.sub.Lo1, U.sub.Lo2, . . . , U.sub.Lon (step 74 in FIG. 6) which is created across the output inductor L.sub.o1, L.sub.o2, . . . , L.sub.on during commutation (step 73), if there is a timing difference ?t in the switching. As can be seen in FIGS. 4E and 4F, positive or negative voltage pulses U.sub.Lo1 and U.sub.Lo2 will be created across the inductors L.sub.o1 and L.sub.o2 of the inverter legs INV1 and INV2, respectively, due to a timing difference ?t The sign of voltage pulse U.sub.Lo1 or U.sub.Lo2 in the parallel-connected inverter leg INV1 or INV2 will depend on whether the voltage pulse was during turn-on or turn-off of the switches, and whether the switching in the respective parallel inverter leg earlier (?t>0) or later (?t<0) than the switching in the other parallel-connected inverter leg (i.e., the sign of ?t). Finally, the positive and negative differential current increments ?I.sub.d in the output currents I.sub.o1 and I.sub.o2 of the inverter legs INV1 and INV2, respectively, are formed as an integral of the inductor voltage pulses U.sub.Lo1 and U.sub.Lo2 over the timing difference ?t.

[0073] In the example shown in FIGS. 4A-4G, the switch S.sub.11 is early to turn on and early to turn off relative to the switch S.sub.12 (?t>0). Thus, in the leg INV1, a negative voltage pulse U.sub.Lo1 is created across the inductor L.sub.o1 at turn-on of S.sub.11 and a positive voltage pulse U.sub.Lo1 is created across the inductor L.sub.o1 at turn-off of S.sub.11 (FIG. 4E), causing a positive ?I.sub.d (?I.sub.d>0) at turn-on of S.sub.11 and a negative ?I.sub.d (?I.sub.d<0) at turn-off of S.sub.11. In the leg INV2, a positive voltage pulse U.sub.Lo2 is created across the inductor L.sub.o2 at turn-off of S.sub.12 and a negative voltage pulse U.sub.Lo2 is created across the inductor L.sub.o2 at turn-on of S.sub.12 (FIG. 4F), causing a negative ?I.sub.d (?I.sub.d<0) at turn-off of S.sub.12 and a positive ?I.sub.d (?I.sub.d>0) at turn-on of S.sub.12.

[0074] Further, the voltages U.sub.Lo1, U.sub.Lo2, . . . , U.sub.Lon will be of opposite sign in the parallel-connected inverters having a timing difference. Hence, based on the sign of the voltage U.sub.Lo1, U.sub.Lo2, . . . , U.sub.Lon (or the sign of ?t) in the respective parallel-connected leg (step 76), each parallel-connected inverter INV1, INV2, . . . , INVn can deduce that its own ?t must have been positive (>0) (e.g., its timing has been early) or its ?t must have been negative (<0) (e.g., its timing has been late). Each parallel-connected inverter leg INV1, INV2, . . . , INVn can now make an adjustment to its turn-off instant t.sub.off or turn-on instant t.sub.on in such way that the adjustment either increases ?I.sub.d (?t) from negative towards zero (step 77) or decreases ?I.sub.d (?t) from positive towards zero (step 78). If the voltage U.sub.Lo1, U.sub.Lo2, . . . , U.sub.Lon (or ?t) is approximately zero, no timing adjustment may be needed (step 79). The monitoring, analysis and adjustment is preferably carried out for each commutation event, i.e., every turn-on or turn-off of the switch (every N to P or P to N commutation). The adjusted t.sub.off or t.sub.on can be used in a subsequent (in the next, for example) turn-off or turn-on of the switch. In embodiments, the adjustments may be stored and further adjusted in the subsequent commutations, e.g., using an integral action controller. In embodiments, if a less optimal adjustment is satisfactory, sensing, analysis and adjustment may not be carried out for each commutation event as in an optimal adjustment but for a selective portion all commutations, such as for sequentially selected commutations, for certain commutations only, or for alternating commutations.

[0075] In embodiments, the duration of the timing difference ?t can also be acquired directly from the width or duration of the voltage pulse U.sub.Lo1, U.sub.Lo2, . . . , U.sub.Lon. Therefore, a benefit of voltage measurement-based approach may be the speed and simplicity of measurement, as there is no need for a current sampling and indirect estimation of ?t from the ?I.sub.o by means of equation (3), for example. The duration of the timing difference ?t can be used in determining the amount of adjustment of the turn-off instant t.sub.off or turn-on instant t.sub.on in the adjustment steps 77 and 78, for example.

[0076] In embodiments, the voltage U.sub.Lo1, U.sub.Lo2, . . . , U.sub.Lon may be integrated by an integrator circuit during the commutation to acquire a measure of ?I.sub.d. The measure of ?I.sub.d can be used in determining the amount of adjustment of the turn-off instant t.sub.off or turn-on instant ton in the adjustment steps 77 and 78, for example.

[0077] The determination of the duration or width of the voltage pulse across the output inductor, and/or the integration of the voltage pulse across the output inductor can be implemented in an analogue or digital circuit. The voltage measurement-based approach could possibly be made faster and real-time with analogue electronics.

[0078] In embodiments, the timing adjustment may comprise postponing the turn-off instant t.sub.off or the turn-on instant t.sub.on of the respective switch to decrease the current increment ?I.sub.d and/or the timing difference ?t towards zero, if the switch is switching early (?t>0), and advancing the turn-off instant t.sub.off or the turn-on instant t.sub.on of the respective switch to increase the current increment ?I.sub.d and/or the timing difference ?t towards zero, if the switch is switching early (?t<0).

[0079] In embodiments, the timing difference ?t and/or the current increments ?I.sub.d in individual commutations are controlled by adjusting the switching instants so that the timing difference ?t and/or the current increment ?I.sub.d is not zero during commutations but stays bounded while an output voltage of the inverter system will swing in a stepwise manner.

[0080] In embodiments, the timing difference ?t and/or the current increments ?I.sub.d in individual commutations are controlled to a fixed non-zero value by adjusting the switching instants, the fixed non-zero value being equal in a turn-on commutation and a turn-off commutation. As a consequence, the differential current I.sub.d jumps back and forth by ?I.sub.d but stays bounded. An example of a resulting behavior of the output voltage U.sub.o of the inverter system is illustrated in FIG. 4G: the swings of the output voltage U.sub.o from N to P and from P to N occur in a step wise manner. The stepwise swing of the output voltage may be beneficial in some applications. In motor drive applications, a stepwise output voltage fed to a motor winding, for example, would ease the stress on motor insulation and bearings.

[0081] In embodiments, the amount of adjustment of the turn-off instant t.sub.off or the turn-on instant ton of the respective switch may be approximately half of the duration of the timing difference ?t. Because the adjustment is made to opposite directions in the two parallel-connected inverter legs, the total amount of adjustments will be approximately ?t, thereby cancelling the timing difference or the current difference between the two legs in subsequent commutations.

[0082] The switching control and timing adjustment techniques described herein may be implemented by various means. For example, these techniques may be implemented in hardware (one or more analog or digital and/devices), firmware (one or more devices), software (one or more modules), or combinations thereof. For a firmware or software, implementation can be through modules (e.g., procedures, functions, and so on) that perform the functions described herein. The software codes may be stored in any suitable, processor/computer-readable data storage medium(s) or memory unit(s) and executed by one or more processors/computers. The data storage medium or the memory unit may be implemented within the processor/computer or external to the processor/computer, in which case it can be communicatively coupled to the processor/computer via various means as is known in the art. Additionally, components of systems described herein may be rearranged and/or complimented by additional components in order to facilitate achieving the various aspects, goals, advantages, etc., described with regard thereto, and are not limited to the precise configurations set forth in a given figure, as will be appreciated by one skilled in the art.

[0083] It will be obvious to a person skilled in the art that, as the technology advances, the inventive concept can be implemented in various ways. The invention and its embodiments are not limited to the examples described above but may vary within the scope of the claims.