Electronic device and memristor-based logic gate circuit thereof

Abstract

An electronic device and a memristor-based logic gate circuit thereof. In the present application, a control end of a controllable switch is connected to a negative end of an output memristor in a MAGIC-based AND logic gate, and whether a second memristor is powered on is controlled by the controllable switch. Thus, when resistance value states of two input memristors in the AND logic gate are different, the controllable switch will conduct and power on the second memristor, and the second memristor will present a low-resistance state at this time. When the resistance value states of the two input memristors are the same, the controllable switch will not conduct and the second memristor will then remain the state unchanged, i.e., presents a high-resistance state. An exclusive OR logic gate is formed by combining the two input memristors and the second memristor.

Claims

1. A memristor-based logic gate circuit, comprising: an AND logic gate based on a memristor-aided logic (MAGIC) auxiliary logic gate, used for realizing an operation of logic AND based on three first memristors connected in series within the AND logic gate; a first power supply, used for outputting electric energy when the AND logic gate is in a steady state; a second memristor having a first end connected to the first power supply, used for presenting a low-resistance state merely when the first power supply supplies power to itself; and a controllable switch having a first end connected to a second end of the second memristor, a second end being grounded, and a control end connected to a negative end of the first memristor as an output memristor, wherein the controllable switch is used for conducting merely when two first memristors as input memristors in the AND logic gate present different resistance value states.

2. The memristor-based logic gate circuit according to claim 1, wherein the AND logic gate based on the auxiliary logic gate MAGIC comprises a second power supply, a first control switch, a first input memristor, a second input memristor, and the output memristor; and the second power supply is connected to a first end of the first control switch, a second end of the first control switch is connected to a negative end of the first input memristor, a positive end of the first input memristor is connected to a negative end of the second input memristor, a positive end of the second input memristor is connected to a negative end of the output memristor, and a positive end of the output memristor is grounded.

3. The memristor-based logic gate circuit according to claim 2, wherein the output memristor presents a high-resistance state in an initial state.

4. The memristor-based logic gate circuit according to claim 2, wherein the first power supply comprises a power supply unit and a second control switch; the first power supply is connected to a first end of the second control switch, and a second end of the second control switch is connected to the first end of the second memristor; and the second control switch is used for being controlled to be turned off when the AND logic gate is in the steady state, so that the power supply unit outputs the electric energy.

5. The memristor-based logic gate circuit according to claim 4, wherein the second power supply and the power supply unit are a same power source.

6. The memristor-based logic gate circuit according to claim 4, wherein the first control switch and the second control switch are of a same type.

7. The memristor-based logic gate circuit according to claim 6, wherein the first control switch and the second control switch are both gated switches.

8. The memristor-based logic gate circuit according to claim 4, wherein the first control switch and the second control switch are of different types.

9. The memristor-based logic gate circuit according to claim 4, wherein the second power supply and the power supply unit are mutually independent power sources.

10. The memristor-based logic gate circuit according to claim 1, wherein the controllable switch is an N-type metal-oxide-semiconductor (NMOS).

11. The memristor-based logic gate circuit according to claim 10, wherein a threshold voltage of the N-type metal-oxide-semiconductor (NMOS) is greater than one third of a nominal voltage of the first power supply and less than a half of the nominal voltage of the first power supply.

12. The memristor-based logic gate circuit according to claim 10, wherein a drain electrode of the N-type metal-oxide-semiconductor (NMOS) is connected to the second end of the second memristor, a source electrode of the N-type metal-oxide-semiconductor (NMOS) is grounded, and a gate electrode of the N-type metal-oxide-semiconductor (NMOS) is connected to the negative end of the first memristor as the output memristor.

13. The memristor-based logic gate circuit according to claim 1, wherein the first memristor and the second memristor are of a same type.

14. The memristor-based logic gate circuit according to claim 13, wherein the first memristor and the second memristor are threshold-type memristors.

15. The memristor-based logic gate circuit according to claim 14, wherein a voltage of the first power supply is greater than a first threshold voltage of the threshold memristor and less than twice the first threshold voltage of the threshold-type memristor; and the first threshold voltage of the threshold-type memristor is a voltage threshold at which the threshold-type memristor transitions from a low-resistance state to a high-resistance state.

16. The memristor-based logic gate circuit according to claim 1, wherein the second memristor presents a high-resistance state in an initial state.

17. The memristor-based logic gate circuit according to claim 1, wherein the memristor-based logic gate circuit is configured to form a half adder circuit.

18. The memristor-based logic gate circuit according to claim 17, wherein a sum of outputs of the half adder circuit is a sum of exclusive OR operations of logic states corresponding to the resistance value states of the two first memristors as the input memristors.

19. The memristor-based logic gate circuit according to claim 17, wherein a carrying value of the half adder circuit is a dot product of logic states corresponding to the resistance value states of the two first memristors as the input memristors.

20. An electronic device, comprising a memristor-based logic gate circuit, wherein the memristor-based logic gate circuit includes: an AND logic gate based on a memristor-aided logic (MAGIC) auxiliary logic gate, used for realizing an operation of logic AND based on three first memristors connected in series within the AND logic gate; a first power supply, used for outputting electric energy when the AND logic gate is in a steady state; a second memristor having a first end connected to the first power supply, used for presenting a low-resistance state merely when the first power supply supplies power to itself; and a controllable switch having a first end connected to a second end of the second memristor, a second end being grounded, and a control end connected to a negative end of the first memristor as an output memristor, wherein the controllable switch is used for conducting merely when two first memristors as input memristors in the AND logic gate present different resistance value states.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) In order to provide a clearer explanation of the technical solution in the embodiments of the present application, a brief introduction will be given below to the prior art and the accompanying drawings required in the embodiments. It is evident that the accompanying drawings described below are merely some embodiments of the present application. For those skilled in the art, other accompanying drawings can be obtained based on these drawings without creative labor.

(2) FIG. 1 is a schematic structural diagram of a memristor-based logic gate circuit according to the present application;

(3) FIG. 2 is a schematic structural diagram of another memristor-based logic gate circuit according to the present application; and

(4) FIG. 3 is a schematic diagram of a resistance of a memristor changing with voltages at two ends.

DETAILED DESCRIPTION

(5) The core of the present application is to provide a memristor-based logic gate circuit, an exclusive OR logic gate is formed by combining two input memristors and a second memristor in a MAGIC-based AND logic gate, and at the same time, the logic gate circuit may also be used as a half adder, facilitating the application of MAGIC technology and improving user experience; another object of the present application is to provide an electronic device including the above-mentioned memristor-based logic gate circuit, the exclusive OR logic gate is formed by combining the two input memristors and the second memristor in the MAGIC-based AND logic gate, and at the same time, the logic gate circuit may also be used as the half adder, facilitating the application of MAGIC technology and improving user experience.

(6) In order to clarify the purpose, technical solution, and advantages of the embodiments of the present application, the following will provide a clear and complete description of the technical solution in the embodiments of the present application in conjunction with the accompanying drawings. Obviously, the described embodiments are a part of the embodiments of the present application, not the entire embodiments. Based on the embodiments in the present application, all other embodiments obtained by persons skilled in the art without creative labor fall within the scope of protection of the present application.

(7) Referring to FIG. 1, FIG. 1 is a schematic structural diagram of a memristor-based logic gate circuit according to the present application, and the memristor-based logic gate circuit includes: an AND logic gate based on an auxiliary logic gate MAGIC, used for realizing an operation of logic AND based on three first memristors connected in series within the AND logic gate; a first power supply 2, used for outputting electric energy when the AND logic gate is in a steady state; a second memristor 3 having a first end connected to the first power supply 2, used for presenting a low-resistance state merely when the first power supply 2 supplies power to itself; and a controllable switch 4 having a first end connected to a second end of the second memristor 3, a second end being grounded, and a control end connected to a negative end of the first memristor as an output memristor; where the controllable switch 4 is used for conducting merely when two first memristors as input memristors in the AND logic gate present different resistance value states.

(8) In order to better explain the embodiments of the present application, reference can be made to FIG. 2 and FIG. 3, FIG. 2 is a schematic structural diagram of another memristor-based logic gate circuit provided in the present application, FIG. 3 is a schematic diagram of a resistance of a memristor changing with voltages at two ends, and FIG. 3 shows how the resistance of the memristor changes with the voltages at the two ends; the working principle of the memristor is that when a certain condition is satisfied, a reversible turnover of two states of a high resistance value and a low resistance value occurs, the high resistance value and the low resistance value may represent two states of 0 and 1 in logic, and the reversible turnover under the condition satisfied ensures a controllable jump between logic states, and after power is removed, the resistance state of the memristor remains stable and has a non-transitory characteristic, therefore, the memristor may satisfy the implementation of a non-transitory logic function. Non-transitory logic operations based on the memristor have great potential value in the field of computing.

(9) The memristors used in the embodiments of the present application are all threshold-type memristors, namely, two types of threshold voltages are required to change the corresponding boundary resistance. For example, the two boundary resistances R.sub.on and R.sub.off (R.sub.off>>R.sub.on) represent logic 1 and 0, respectively, the voltage required to be applied to change the memristor from logic 0 to logic 1 should be greater than or equal to the threshold voltage V.sub.T-ON, and the voltage required to be applied to change the memristor from logic 1 to logic 0 should be less than or equal to the threshold voltage V.sub.T-OFF.

(10) In some embodiments, in FIG. 2, M.sub.in1 and M.sub.in2 are two input memristors in the AND logic gate, M.sub.out1 is an output memristor, the controllable switch 4 is NMOS.sub.1, and the second memristor 3 is M.sub.out2.

(11) The exclusive OR gate circuit and the half adder circuit based on the memristor MAGIC logic proposed in the present application are improved and optimized on the basis of the AND gate circuit of the MAGIC logic. Therefore, the AND gate circuit of the MAGIC logic is first built, namely, the voltage sources V.sub.0, M.sub.in1, M.sub.in2, and M.sub.out1 are connected in series, and the operation process of realizing the AND logic is as follows: (1) setting an initial state, and setting the resistance value of the output memristor MOUT1 as R.sub.off, namely, the logic state is 0; (2) setting a corresponding input state for two input memristors; (3) switch S.sub.1 is closed and voltage V.sub.0 is applied to branch 1.

(12) The above operation process may complete the logical operation of the AND gate. Assuming that the two logic values of the input signal are 00, the corresponding input memristor resistance values are both R.sub.off, and at this time, the two input memristors and the output memristor M.sub.out1 are connected in series, and the resistance values are both R.sub.off. Therefore, the voltage at the two ends of the output memristor M.sub.out1 is V.sub.0/3, which does not reach the threshold voltage at which the output memristor M.sub.out1 transitions from R.sub.off to R.sub.on, so the logic state of the output memristor M.sub.out1 is still 0. Similarly, when the logic value of the input signal is 10 or 01, the voltage at the two ends of the output memristor M.sub.out1 is

(13) $\frac{R_{\mathrm{off}}{V}_0}{2R_{\mathrm{off}}+R_{on}},$
approximately V.sub.0/2, and the voltages at the two ends of the output memristor M.sub.out1 in both cases are less than V.sub.T_ON, which do not reach the threshold voltage at which the output memristor M.sub.out1 transitions from R.sub.off to R.sub.on, so the logic state of the output memristor M.sub.out1 is still 0. Merely when the input logic is 11, the voltage at the two ends of the output memristor M.sub.out1 is

(14) $\frac{R_{\mathrm{off}}{V}_0}{R_{\mathrm{off}}+2R_{on}},$
which is greater than V.sub.T_ON, thereby enabling the output logic to transition from 0 to 1. The inputs and outputs of the above signals correspond to the truth table of the AND gate, thereby realizing the function of the AND logic gate. The truth table of the AND logic gates is shown in Table 1.

(15) TABLE-US-00001 TABLE 1 Input A Input B A AND B A XOR B 0 0 0 0 0 1 0 1 1 0 0 1 1 1 1 0

(16) Wherein, in the AND logic gate of FIG. 2,

(17) $\frac{R_{\mathrm{off}}{V}_0}{2R_{\mathrm{off}}+R_{on}}<V_{\mathrm{T\_ON}}<\frac{R_{\mathrm{off}}{V}_0}{R_{\mathrm{off}}+2R_{on}};$

(18) Since R.sub.off>>R.sub.on, the value range of V.sub.0 is:
V.sub.T_ON<V.sub.0<2V.sub.T_ON;

(19) the threshold voltage V.sub.TH of the above-mentioned NMOS (N-type metal-oxide-semiconductor) ranges from:
V.sub.0/3<V.sub.TH<V.sub.0/2;

(20) wherein V.sub.0 is the nominal voltage of the first power supply 2.

(21) In some embodiments, the exclusive OR logic operation is performed after the AND logic operation is finished, namely, after the voltages at each end of branch 1 are stabilized. The operation process of realizing exclusive OR logical operation is as follows: (1) setting an initial state, and setting the resistance value of the output memristor M.sub.OUT2 as R.sub.off, namely, the logic state is 0, and this step can be performed simultaneously with step (1) in the above-mentioned AND logic operation; (2) switch S.sub.2 is turned off and voltage V.sub.0 is applied to branch 2.

(22) The above operation process may complete the logical operation of the exclusive OR gate. Assuming that the two logic values of the input signal are 00, the logic state of the AND logic output memristor M.sub.out1 is still 0, at this moment, the voltage value at two ends of the M.sub.out1 is V.sub.0/3, which is less than the threshold voltage of the NMOS, the source and drain of the NMOS are in an off state, and the logic state of the output memristor M.sub.out2 is still 0 unchanged; when the two logic values of the input signal are 11, then the final logic state of the AND logic output memristor M.sub.out1 is 1, at this moment, the voltage value at two ends of the M.sub.out1 is V.sub.0/3, which is still less than the threshold voltage of the NMOS, the source and drain of the NMOS are in an off state, and the logic state of the output memristor M.sub.out2 remains 0 unchanged; when the two logic values of the input signal are 10 or 01, the logic state of the AND logic output memristor M.sub.out1 is 0, at this moment, the voltage value at two ends of the M.sub.out1 is

(23) $\frac{R_{\mathrm{off}}{V}_0}{2R_{\mathrm{off}}+R_{on}},$
approximately V.sub.0/2, which is greater than the threshold voltage of the NMOS, the source and drain of the NMOS are in a conduction state, and the voltage at two ends of the output memristor M.sub.out2 is V.sub.0, which is greater than V.sub.T_ON, so as to realize that the logic of the output memristor M.sub.out2 is converted from 0 to 1. The inputs and outputs of the above signals correspond to the truth table of the exclusive OR gate, thereby implementing the function of the exclusive OR logic gate. The exclusive OR logic gate truth table is shown in Table 1.

(24) The logical expression for a half adder is:
S=A?B;
C=A.Math.B; where A and B are addends (inputs), S is a sum, and C is the carry towards a high position. According to the logic expression of the half adder, it can be seen that the two output ends of the half adder are the exclusive OR and AND logic operation results of the two input ends respectively. Therefore, the circuit designed by the embodiments of the present application can also be used as a half adder circuit.

(25) The present application provides a memristor-based logic gate circuit, considering that in an AND logic gate based on an auxiliary logic gate MAGIC, the voltage of the negative end of the output memristor will merely present two different voltage levels, i.e., a high voltage level and a low voltage level, and when presenting the high voltage level, the resistance value states of the two input memristors are opposite. Therefore, in the present application, the control end of the controllable switch is connected to the negative end of the output memristor, and whether the second memristor is powered on is controlled by the controllable switch, such that when the resistance value states of the two input memristors in the AND logic gate are different from each other, the controllable switch will conduct and enable the second memristor to be powered on; the second memristor then presents a low-resistance state (representing a logic 1); when the resistance state the resistance value states of the two input memristors in the AND logic gate are the same, the controllable switch will not conduct and the second memristor will then remain the state unchanged, i.e. represents a high-resistance state (representing a logic 0). That is to say, an exclusive OR logic gate is formed by combining the two input memristors and the second memristor, and at the same time, the logic gate circuit can also be used as a half adder, facilitating the application of MAGIC technology and improving user experience.

(26) On the basis of the above embodiments: in some embodiments, the AND logic gate based on the auxiliary logic gate MAGIC includes a second power supply, a first control switch S.sub.1, a first input memristor, a second input memristor, and an output memristor; the second power supply is connected to a first end of the first control switch S.sub.1, a second end of the first control switch S.sub.1 is connected to a negative end of the first input memristor, a positive end of the first input memristor is connected to a negative end of the second input memristor, a positive end of the second input memristor is connected to a negative end of the output memristor, and a positive end of the output memristor is grounded.

(27) In some embodiments, the MAGIC-based AND logic gate 1 may have other configurations in addition to the specific configuration, and the embodiment of the present application is not limited thereto.

(28) In some embodiments, the first power supply 2 includes a power supply unit V.sub.0 and a second control switch S.sub.2;

(29) the first power supply 2 is connected to a first end of the second control switch S.sub.2, and a second end of the second control switch S.sub.2 is connected to a first end of the second memristor 3;

(30) the second control switch is used for being controlled to be turned off when the AND logic gate is in a steady state so that the power supply unit V.sub.0 outputs electric energy.

(31) In some embodiments, in the embodiment of the present application, whether the power supply unit V.sub.0 outputs the electric energy or not may be controlled by the second control switch S.sub.2, and the function of the second control switch S.sub.2 is to prevent the influence on the voltage of the control end of the controllable switch 4 caused by the unstable voltage at each endpoint in the branch 1 at the moment when the first control switch S.sub.1 is turned off, thereby resulting in the misoperation of on and off states of the controllable switch 4.

(32) In some embodiments, the first power supply 2 in the embodiment of the present application has the advantages of simple structure and low cost.

(33) Certainly, the first power supply 2 may be of other types than the specific configuration, and the embodiment of the present application is not limited thereto.

(34) In some embodiments, the second power supply is the same power supply as the power supply unit V.sub.0.

(35) In some embodiments, designing the second power supply to be the same power supply as the power supply unit V.sub.0 may simplify the structure and reduce the cost.

(36) Certainly, the second power supply and the power supply unit V.sub.0 may be independent power sources, and the embodiment of the present application is not limited herein.

(37) In some embodiments, the first control switch S.sub.1 and the second control switch S.sub.2 are of the same type.

(38) In some embodiments, designing the first control switch S.sub.1 and the second control switch S.sub.2 to be the same type may simplify the structure and reduce the cost.

(39) Certainly, the first control switch S.sub.1 and the second control switch S.sub.2 may be of different types, and the embodiment of the present application is not limited thereto.

(40) In some embodiments, the first control switch S.sub.1 and the second control switch S.sub.2 are gated switches.

(41) In some embodiments, the gated switch has the advantages of high automation and long life.

(42) Certainly, in addition to the gated switch, the first control switch S.sub.1 and the second control switch S.sub.2 may be of other types, and the embodiment of the present application is not limited thereto.

(43) In some embodiments, the controllable switch 4 is an N-type metal-oxide-semiconductor (NMOS).

(44) In some embodiments, NMOS has the advantages of small size, fast response, and long life.

(45) Certainly, the controllable switch 4 may be of other types than NMOS, and the embodiments of the present application are not limited herein.

(46) The present application also provides an electronic device including a memristor-based logic gate circuit as in the previous embodiments.

(47) For a description of the electronic devices provided by the embodiments of the present application, reference is made to the aforementioned embodiments of the memristor-based logic gate circuit, and the embodiments of the present application will not be described in detail herein.

(48) The embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same and similar parts between the embodiments can be referred to each other. It should also be noted that in the specification, relational terms such as first and second are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms including, comprising, or any other variation thereof are intended to encompass non-exclusive inclusion, such that a process, method, item, or device that includes a series of elements not merely includes those elements, but also includes other elements that are not explicitly listed, or also includes elements inherent to such process, method, item, or device. Without further limitations, the element limited by the statement including one . . . does not exclude the existence of another identical element in the process, method, item, or device that includes that element.

(49) The above explanation of the disclosed embodiments enables persons skilled in the art to implement or use the present application. The various modifications to these embodiments will be apparent to persons skilled in the art, and the general principles defined in the specification can be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.