Metal circuit structure based on FPC and method of making the same
12089331 ยท 2024-09-10
Assignee
Inventors
- Cheng-Neng Chen (Changzhou, CN)
- Sui-Ho Tsai (Changzhou, CN)
- Yun-Nan Wang (Changzhou, CN)
- Chiao-Hui Wang (Changzhou, CN)
Cpc classification
C23C28/028
CHEMISTRY; METALLURGY
H05K2201/0341
ELECTRICITY
H05K2201/0338
ELECTRICITY
H05K1/118
ELECTRICITY
H05K1/11
ELECTRICITY
C25D5/10
CHEMISTRY; METALLURGY
H05K3/244
ELECTRICITY
H05K1/147
ELECTRICITY
International classification
C23C18/16
CHEMISTRY; METALLURGY
C23C28/02
CHEMISTRY; METALLURGY
C25D5/10
CHEMISTRY; METALLURGY
Abstract
A metal circuit structure based on a flexible printed circuit (FPC) contains: a substrate, a first metal layer attached on the substrate, a second metal layer formed on the first metal layer, and an intermediate layer defined between the first metal layer and the second metal layer. A first surface of the intermediate layer is connected with the first metal layer, and a second surface of the intermediate layer is connected with the second metal layer. The intermediate layer is made of a first material, the second metal layer is made of a second material, and the first material of the intermediate layer does not act with the second material of the second metal layer.
Claims
1. A metal circuit structure based on a flexible printed circuit (FPC) comprising: a substrate; a copper layer attached on the substrate; a tin layer formed on the copper layer; an intermediate layer defined between the copper layer and the tin layer, wherein a first surface of the intermediate layer is connected with the copper layer, and a second surface of the intermediate layer is connected with the tin layer, wherein the intermediate layer comprises a first speculum metal layer to form the second surface, wherein the intermediate layer comprises a nickel layer to form the first surface; and two metal layers formed on two sides of the copper layer, wherein the two metal layers are each made of a second speculum metal.
2. The metal circuit structure as claimed in claim 1, wherein a thickness of the copper layer is 1 ?m to 12 ?m.
3. The metal circuit structure as claimed in claim 1, wherein a thickness of the tin layer is 100 nm to 200 nm.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
(1)
(2)
(3)
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
(4) With reference to
(5) The intermediate layer 3 is defined between the first metal layer 2 and the second metal layer 4 so as to separate the first metal layer 2 from the second metal layer 4, such that a thickness of the second metal layer 4 is limited within a predetermined range to avoid a removal of a circuit from the substrate 1.
(6) Preferably, the intermediate layer 3 is made of any one or at least two of titanium, nickel, chromium, molybdenum, tungsten, cobalt, vanadium, and niobium. Preferably, the intermediate layer 3 is nickel so as to reduce fabrication cost.
(7) The first metal layer 2 is made of copper, wherein a thickness of the first metal layer 2 is 1 ?m to 12 ?m, and a preferred thickness of the first metal layer 2 is 8 ?m to 10 ?m, thus obtaining a balance of a processing performance and a conductivity of the first metal layer 2.
(8) The second metal layer 4 is made of tin, and a thickness of the second metal layer 4 is 100 nm to 200 nm.
(9) The metal circuit structure further comprises: two third metal layers 5 formed on two sides of the first metal layer 2.
(10) The third metal layer 5 is made of speculum metal.
(11) A thickness of the intermediate layer 3 is 5 nm to 50 nm. Preferably, a thickness of the intermediate layer 3 is 30 nm so as to separate the first metal layer 2 from the second metal layer 4.
(12) Referring to
(13) S00) sputtering metal atoms on the substrate 1 so as to form a seed layer 6 and adhering a photoresist film on the seed layer 6 to execute exposure and developing treatment so that a portion of the seed layer 6 on which no metal circuit is arranged, is covered by a photoresist 7;
(14) S10) plating copper on the substrate 1 so as to form the first metal layer 2;
(15) S20) forming the intermediate layer 3 on the first metal layer 2;
(16) S30) plating copper on the intermediate layer 3 so as to form a copper layer 8;
(17) S40) washing the photoresist 7 away and having micro-nano etching on the substrate 1 until the portion of the seed layer 6 on which no metal circuit is arranged, is etched completely, and having immersion tin on the circuit;
(18) S50) backing the first metal layer 2 after steps of S10) and S20 so as to release stress form the first metal layer 2 and to maintain a stable crystalline state.
(19) In a first embodiment, the first metal layer 2 is made of copper and has a thickness of 8 ?m, the intermediate layer 3 is made of nickel, and a thickness of the intermediate layer 3 is 30 nm. The second metal layer 4 is made of tin, and a thickness of the second metal layer 4 is 100 nm, wherein the thicknesses of the first metal layer 2, the intermediate layer 3, and the second metal layer 4 remain unchanged after being baked.
(20) In a second embodiment, the first metal layer 2 is made of copper and a thickness of the first metal layer 2 is 8 ?m, the intermediate layer 3 is made of nickel and a thickness of the intermediate layer 3 is 30 nm, and the second metal layer 4 is made of tin and a thickness of the second metal layer 4 is 200 nm, wherein the thicknesses of the first metal layer 2, the intermediate layer 3, and the second metal layer 4 remain unchanged after being baked.
(21) In a third embodiment, the first metal layer 2 is made of copper and a thickness of the first metal layer 2 is 8 ?m, the intermediate layer 3 is made of nickel and a thickness of the intermediate layer 3 is 30 nm, and the second metal layer 4 is made of tin and a thickness of the second metal layer 4 is 160 nm, wherein the thicknesses of the first metal layer 2, the intermediate layer 3, and the second metal layer 4 remain unchanged after being baked.
(22) In a fourth embodiment, the first metal layer 2 is made of copper and a thickness of the first metal layer 2 is 8 ?m, the intermediate layer 3 is made of nickel and a thickness of the intermediate layer 3 is 4 nm, and the second metal layer 4 is made of tin and a thickness of the second metal layer 4 is 160 nm, wherein the intermediate layer 3 has speculum metal after being baked.
(23) In a fifth embodiment, the first metal layer 2 is made of copper and a thickness of the first metal layer 2 is 8 ?m, the intermediate layer 3 is made of nickel and a thickness of the intermediate layer 3 is 50 nm, and the second metal layer 4 is made of tin and a thickness of the second metal layer 4 is 160 nm, wherein the thicknesses of the first metal layer 2, the intermediate layer 3, and the second metal layer 4 remain unchanged after being baked.
(24) In comparison, as shown in
(25) A thickness of tin of a conventional circuit reduces after forming the intermediate layer 3 in a backing process so that the intermediate layer 3 is connected with a pin of a chip in a hot pressing manner so as to increase the thickness of the intermediate layer 3, thus enhancing isolation between copper and tin.
(26) Conventionally, the thickness of tin of the circuit remain unchanged so as to reduce consumption of tin and a height of the circuit, thus avoiding the removal of the circuit from the substrate 1. When a thickness of tin of Chip On Flex (COF) is low, the pin is not welded on the chip. When the thickness of the tin is thick, the tin leaks in a welding process to contact with the circuit, thus causing a short circuit. Accordingly, the method of the present invention is applicable for COF.
(27) While the preferred embodiments of the invention have been set forth for the purpose of disclosure, modifications of the disclosed embodiments of the invention as well as other embodiments thereof may occur to those skilled in the art. The scope of the claims should not be limited by the preferred embodiments set forth in the examples, but should be given the broadest interpretation consistent with the description as a whole.