SIGMA-DELTA MODULATOR BASED ANALOG-TO-DIGITAL CONVERTER AND DITHERING METHOD THEREOF

Abstract

The disclosed invention is a sigma-delta modulator based ADC and a dithering method thereof. An analog dither circuit of an input stage in a quantizer, which is configured to perform dithering, receives an integrator output signal from an output of an integrator and a plurality of digital dither signals from digital dither generator, and employs these signals to produce multi-level analog dither signals via the operation of a plurality of transistors as switches coupled with a plurality of resistors coupled in series. The multi-level analog dither signals can prevent, reduce, or eliminate limit cycle in the sigma-delta modulator based ADC. Furthermore, disclosed invention does not require fixed load capacitance, resulting in no extra power consumption and solve the problem as the kickback noise variation.

Claims

1. A sigma-delta modulator based analog-to-digital converter (ADC) (100), comprising: a digital dither generator (101) configured to provide a plurality of digital dither signals S.sub.di the digital dither generator (101) comprising a dither pattern generator (601) and a binary decoder (602); a sigma-delta modulator loop (102) configured to receive an input analog signal S.sub.in and the plurality of digital dither signals S.sub.di, and to provide a quantizer output signal S.sub.q; and a processor (103) configured to provide a digital representation of the input analog signal S.sub.in. where the sigma-delta modulator loop (102) comprising an integrator (104) configured to provide an integrator output signal S.sub.int; a feedback digital to analog converter (DAC) (105) configured to receive the quantizer output signal S.sub.q and to produce a feedback signal S.sub.fb; and a quantizer (106) configured to receive the integrator output signal S.sub.int and the plurality of digital dither signals S.sub.di and to output the quantizer output signal S.sub.q, where the quantizer (106) comprising an input stage (201) configured to receive the integrator output signal S.sub.int and the plurality of digital dither signals S.sub.di and to provide an output signal S.sub.cmp; and a gain stage (202) configured to receive the output signal S.sub.cmp and to output the quantizer output signal S.sub.q. where the input stage (201) comprising a current source (301); a pair of input transistors (302) configured to produce first and second output current signals S.sub.curr_a, S.sub.curr_b in relation to the integrator output signal S.sub.int and a threshold signal S.sub.threshold; a load network (303) configured to convert the first and second output current signals S.sub.curr_a, S.sub.curr_b into the output signals S.sub.cmp_a, S.sub.cmp_b of the input stage (201); and an analog dither circuit (304) characterized in that the analog dither circuit (304), coupled in series between the current source (301) and the pair of input transistors (302) and configured to receive the plurality of digital dither signals S.sub.di and to divide a bias current from the current source (301) to each transistor of the pair of input transistors (302).

2. The sigma-delta modulator based analog-to-digital converter (ADC) of claim 1 wherein the analog dither circuit (304) comprises a plurality of resistors (401) coupled in series and configured to provide resistance; and a plurality of transistors as switches (402) configured to function as switches.

3. The sigma-delta modulator based analog-to-digital converter (ADC) of claim 2 wherein the plurality of resistors (401) provide resistance between a first source terminal S.sub.source_a of the pair of input transistors (302) to an output S.sub.current of the current source (301) and a second source terminal S.sub.source_b of the pair of input transistors (302) to the output S.sub.current of the current source (301).

4. The sigma-delta modulator based analog-to-digital converter (ADC) of claim 2 or 3 wherein the plurality of resistors (401) providing resistance depending on current division ratio of the divided current.

5. The sigma-delta modulator based analog-to-digital converter (ADC) of claim 2 wherein the transistors of the plurality of transistors as switches (402) are coupled with terminals of resistors of the plurality of resistors (401) at drain terminals.

6. The sigma-delta modulator based analog-to-digital converter (ADC) of claim 2 wherein the plurality of transistors as switches (402) are coupled with the plurality of digital dither signals S.sub.di at control terminals (405).

7. The sigma-delta modulator based analog-to-digital converter (ADC) of claim 2 wherein the plurality of transistors as switches (402) are coupled with the output S.sub.current of the current source (301) at source terminals (406).

8. The sigma-delta modulator based analog-to-digital converter (ADC) of claim 2 wherein each transistor of the plurality of transistors as switches (402) is configured to provide a current path from the output S.sub.current of the current source (301) to one of the terminals of the plurality of resistors (401) when one of the transistors of the plurality of transistors as switches (402) is turned on.

9. The sigma-delta modulator based analog-to-digital converter (ADC) of claim 2 or 8 wherein the transistor of the plurality of transistors as switches (402) providing the current path is controlled by the plurality of digital dither signals S.sub.di.

10. The sigma-delta modulator based analog-to-digital converter (ADC) of claim 2 or 8 wherein each transistor of the plurality of transistors as switches (402) is configured to receive each signal of the plurality of digital dither signals S.sub.di.

11. The sigma-delta modulator based analog-to-digital converter (ADC) of claim 1 wherein the plurality of digital dither signals Sai is generated from the binary decoder (602) and then received by the analog dither circuit (304).

12. The sigma-delta modulator based analog-to-digital converter (ADC) of claim 11 wherein the binary decoder (602) is N-to-M binary decoder (701) configured to decode a plurality of binary representation of a dither pattern S.sub.di_bin and produce the plurality of digital dither signal S.sub.di, wherein a number of decoded output bits (M) are correlated to a number of a binary coded input (N), calculated as M=2.

13. The sigma-delta modulator based analog-to-digital converter (ADC) of claim 1 wherein the analog dither circuit (304), coupled in series between the first and second source terminals S.sub.source_a, S.sub.source_b of the pair of input transistors (302) and to the output S.sub.current of the current source (301).

14. The sigma-delta modulator based analog-to-digital converter (ADC) of claim 2 wherein left and right terminals of the plurality of resistors (403, 404) are coupled to the first and second source terminals S.sub.source_a, S.sub.source_b respectively of the pair of input transistors (302).

15. The sigma-delta modulator based analog-to-digital converter (ADC) of claim 2 wherein a number of the plurality of transistors as switches (402) are the same as a number of the plurality of digital dither signals S.sub.di; and a number of the plurality of resistors (401) are at least one more than the number of the plurality of transistors as switches (402).

16. The sigma-delta modulator based analog-to-digital converter (ADC) of claim 2 wherein the plurality of resistors (401) can be replaced by a plurality of transistors, configured to function as resistors, biased in linear region.

17. The sigma-delta modulator based analog-to-digital converter (ADC) of claim 2 wherein all resistors in the plurality of resistors (401) can be of the same predetermined values.

18. The sigma-delta modulator based analog-to-digital converter (ADC) of claim 2 wherein each transistor of the plurality of transistors as switches (402) is only coupled with one digital dither signal from the plurality of digital dither signals S.sub.di.

19. The sigma-delta modulator based analog-to-digital converter (ADC) of claim 1 wherein the current division ratio of the divided current depends on the plurality of digital dither signals S.sub.di.

20. The sigma-delta modulator based analog-to-digital converter (ADC) of claim 1 or 19 wherein the plurality of digital dither signals Sai control the current division ratio by controlling which transistor belonging to the plurality of transistors as switches (402) to turn on.

21. The sigma-delta modulator based analog-to-digital converter (ADC) of claim 1 or 19 wherein the current division ratio from the first and second source terminals S.sub.source_a, S.sub.source_b of the pair of input transistors (302) affects the first and second output current signals S.sub.curr_a, S.sub.curr_b.

22. The sigma-delta modulator based analog-to-digital converter (ADC) of claim 1 wherein the first and second output current signals S.sub.curr_a, S.sub.curr_b affects, in proportional values, the first and second output signals S.sub.cmp_a, S.sub.cmp_b of the input stage (201).

23. The sigma-delta modulator based analog-to-digital converter (ADC) of claim 1 wherein only one digital dither signal from the plurality of digital dither signals S.sub.di can be of logic HIGH at a given time.

24. The sigma-delta modulator based analog-to-digital converter (ADC) of claim 1 or 23 wherein only one digital dither signal from the plurality of digital dither signals S.sub.di to be logic HIGH can control a transistor in the plurality of transistors as switches (402) to turn on.

25. A dithering method of sigma-delta based modulator analog-to-digital converter (ADC), comprising: receiving an input analog signal S.sub.in and a feedback signal Se at an integrator (104) to provide an integrator output signal S.sub.int; receiving the integrator output signal S.sub.int and a plurality of digital dither signal S.sub.di at an input stage (201) of a quantizer (106) and comparing the integrator output signal S.sub.int and the plurality of digital dither signal S.sub.di against a threshold signal S.sub.threshold to produce an output signal S.sub.cmp of the input stage (201); amplifying the output signal S.sub.cmp of the input stage (201) at a gain stage (202) to produce a quantizer output signal S.sub.q; receiving the quantizer output signal S.sub.q at a processor (103) to produce a plurality of output digital signals S.sub.out as a digital representation of the input analog signal S.sub.in; characterized in that receiving the plurality of digital dither signals S.sub.di at control terminals (405) of a plurality of transistors as switches (402) to control the plurality of transistors as switches (402) as turning on or off; providing current from a current source (301) to first and second source terminals S.sub.source_a, S.sub.source_b of a pair of input transistors (302) through the plurality of transistors as switches (402) and a plurality of resistors (401) respectively; receiving the integrator output signal S.sub.int and the threshold signal S.sub.threshold at control terminals (305) of the pair of input transistors (302); producing first and second output current signals S.sub.curr_a, S.sub.curr_b in relation to the integrator output signal S.sub.int and the threshold signal S.sub.threshold; and converting the first and second output current signals S.sub.curr_a, S.sub.curr_b at a load network (303) to the output signals S.sub.cmp_a, S.sub.cmp_b of the input stage (201).

26. The dithering method of sigma-delta based modulator analog-to-digital converter (ADC) of claim 25, further comprising generating the plurality of digital dither signals S.sub.di at a binary decoder (602) of a digital dither generator (101).

27. The dithering method of sigma-delta based modulator analog-to-digital converter (ADC) of claim 26 wherein generating the plurality of digital dither signals S.sub.di includes generating logic HIGH and LOW of the plurality of digital dither signals S.sub.di; and propagating the logic HIGH and LOW of the plurality of digital dither signals Sai wherein controlling the plurality of transistors as switches (402) to turn on or off.

28. The dithering method of sigma-delta based modulator analog-to-digital converter (ADC) of claim 27 wherein controlling the plurality of transistors as switches (402) to turn on if logic HIGH and controlling the plurality of transistors as switches (402) to turn off if logic LOW.

29. The dithering method of sigma-delta based modulator analog-to-digital converter (ADC) of claim 25, further comprising providing current path by one of transistors of the plurality of transistors as switches (402) turned on, from an output S.sub.current of the current source (301) to one of terminals of the plurality of resistors (401).

30. The dithering method of sigma-delta based modulator analog-to-digital converter (ADC) of claim 25, further comprising dividing current between the first and second source terminals S.sub.source_a, S.sub.source_b of the pair of input transistors (302) according to the current division ratio of the divided current wherein controlled by transistor of the plurality of transistors as switches (402) which is turned on.

Description

BRIEF DESCRIPTION OF THE DRAWING

[0070] FIG. 1 is an example block diagram of a sigma-delta modulator based ADC having a digital dither generator according to the invention.

[0071] FIG. 2 is an example block diagram of a quantizer of the sigma-delta modulator based ADC according to the invention.

[0072] FIG. 3 is an example implementation of an input stage of the quantizer of the sigma-delta modulator based ADC according to the invention.

[0073] FIG. 4 is an example implementation of an analog dither circuit of the quantizer of the sigma-delta modulator based ADC according to the invention having X dither signal levels.

[0074] FIG. 5 is an example embodiment of an analog dither circuit of the quantizer of the sigma-delta modulator based ADC according to the invention having seven dither signal levels.

[0075] FIG. 6 is an example block diagram of a digital dither generator of the sigma-delta modulator based ADC according to the invention.

[0076] FIG. 7 is an example implementation of a binary decoder, N-to-M binary decoder, of the digital dither generator of the sigma-delta modulator based ADC according to the invention.

[0077] FIG. 8 is an example embodiment of the binary decoder as 3-to-8 binary decoder of the digital dither generator of the sigma-delta modulator based ADC according to the invention.

DETAILED DESCRIPTION

[0078] As recognized by the inventors of the U.S. Pat. No. 9,356,617 B2, in order to sufficiently eliminate the effect of limit cycles in sigma-delta modulator based analog-to-digital converter (ADC), a dither signal with multiple levels added to the input of the quantizer is required. A general example of a first-order, sigma-delta modulator based ADC is presented here, however the working principle of this method and apparatus holds true for a higher order of sigma-delta modulator based ADC.

[0079] A general example of a sigma-delta modulator based ADC (100) is illustrated in FIG. 1. The sigma-delta modulator based ADC (100) comprises a digital dither generator (101), a sigma-delta modulator loop (102) and a processor (103). A digital dither generator (101) is configured to provide a plurality of digital dither signals S.sub.di. The sigma-delta modulator loop (102) is configured to receive an input analog signal S.sub.in and the plurality of digital dither signals S.sub.di of digital dither generator (101) to provide a quantizer output signal S.sub.q. The bitstream representation is then processed via the processor (103); for example, a digital filter, to produce a plurality of output digital signals S.sub.out as a digital representation of the input analog signal S.sub.in. The sigma-delta modulator loop (102) comprises an integrator (104), a feedback digital to analog converter (DAC) (105) and a quantizer (106).

[0080] The quantizer (106) is coupled to an integrator (104) via an integrator output signal S.sub.int. The feedback DAC (105) is coupled to the quantizer (106) via the quantizer output signal S.sub.q. The integrator (104) is also coupled to the feedback DAC (105) via a feedback signal S.sub.fb.

[0081] The input analog signal S.sub.in is received by the integrator (104). The integrator (104), when receiving the input analog signal S.sub.in and the feedback signal S.sub.fb, produces the integrator output signal S.sub.int representing an integration of a summation product of the input analog signal S.sub.in and the feedback signal S.sub.fb, to the quantizer (106).

[0082] In another embodiment according to this invention, the integrator (104) can produce the integrator output signal S.sub.int up to 2 signals.

[0083] The quantizer (106) receives the integrator output signal S.sub.int from the integrator (104) and receives a plurality of digital dither signals S.sub.di from the digital dither generator (101). The quantizer (106) can be a single-bit or a multi-bit quantizer. For example, the quantizer (106) as single-bit quantizes the integrator output signal S.sub.int with a particular single threshold in combination with the plurality of digital dither signals S.sub.di and outputs the quantizer output signal S.sub.q as a representation of the input analog signal S.sub.in and the plurality of digital dither signals S.sub.di.

[0084] In another embodiment, the quantizer (106) as multi-bit quantizes the integrator output signal S.sub.int with a plurality of thresholds in combination with the plurality of digital dither signals S.sub.di and outputs the quantizer output signal S.sub.q as a representation of the input analog signal S.sub.in and the plurality of digital dither signals S.sub.di.

[0085] In some examples, the plurality of digital dither signals S.sub.di can be used to alter the single threshold or the plurality of thresholds of the quantizer (106) to produce dithering with analog dither circuit (304).

[0086] In some further examples, the plurality of digital dither signals S.sub.di is configured to prevent limit cycles from the sigma-delta modulator based ADC (100).

[0087] The feedback DAC (105) receives the quantizer output signal S.sub.q to produce the feedback signal S.sub.fb as the sigma-delta modulator loop feedback.

[0088] In an example of a sigma-delta modulator based ADC (100), the feedback DAC (105) can be configured as a direct feedback path.

[0089] In an example, the feedback DAC (105) can be configured as a direct feedback path in the sigma-delta modulator loop (102) with the single-bit quantizer.

[0090] The quantizer (106), as an example according to this invention, comprises an input stage (201) and a gain stage (202) as illustrated in FIG. 2. The input stage (201) can receive two input signals, comprising the integrator output signal S.sub.int and the plurality of digital dither signals S.sub.di from the digital dither generator (101). The input stage (201) is configured to compare the integrator output signal S.sub.int and the plurality of digital dither signals S.sub.di against a threshold signal S.sub.threshold to produce an output signal S.sub.cmp of the input stage (201) to represent the result of the comparison. In an example, the threshold signal S.sub.threshold can be generated using a bandgap voltage reference.

[0091] In another embodiment, the input stage (201) can be configured to compare the integrator output signal S.sub.int and the plurality of digital dither signals S.sub.di against a plurality of threshold signals S.sub.thredhold to produce a plurality of output signals S.sub.cmp of the input stage (201) to represent the result of the comparison. In an example, the plurality of threshold signals S.sub.thredhold can be generated using a plurality of resistors coupled in series to form a voltage divider.

[0092] The gain stage (202) is configured to receive the output signal S.sub.cmp of the input stage (201) and then, as an example, to amplify the output signal S.sub.cmp of the input stage (201) to produce the quantizer output signal S.sub.q appropriated to be received by the subsequent stage.

[0093] In further example, the gain stage (202) can include a latch to produce the quantizer output signal S.sub.q in a dynamic quantizer.

[0094] In an example implementation, the input stage (201) comprises a current source (301), a pair of input transistors (302), a load network (303) and an analog dither circuit (304) as illustrated in FIG. 3. The current source (301) is coupled with the analog dither circuit (304). The analog dither circuit (304) is coupled in series between the current source (301) and the pair of input transistors (302).

[0095] The current source (301) has a purpose of maintaining a bias current for the rest of the components in the input stage (201). The pair of input transistors (302) receives the integrator output signal S.sub.int and the threshold signal S.sub.threshold at control terminals (305) of the pair of input transistors (302). The pair of input transistors (302) then produces first and second output current signals S.sub.curr_a, S.sub.curr_b in relation to the integrator output signal S.sub.int and the threshold signal S.sub.threshold respectively to be received by the subsequent load network (303). For example, the first output current signal S.sub.curr_a can be higher than the second output current signal S.sub.curr_b when the integrator output signal S.sub.int is higher than the threshold signal S.sub.threshold.

[0096] In another embodiment, the first output current signal S.sub.curr_a can be lower than the second output current signal S.sub.curr_b when the integrator output signal S.sub.int is lower than the threshold signal S.sub.threshold.

[0097] The load network (303) serves as a means to convert the first and second output current signals S.sub.curr_a, S.sub.curr_b from the pair of input transistors (302) into the first and second output signals S.sub.curr_a, S.sub.curr_b of the input stage (201) to be amplified by the subsequent stages.

[0098] As a general example, the load network (303) can be realized by a number of ways, depending on the intended specification and its subsequent stage. In an example embodiment, the load network 303 can be realized as a pair of resistors, where one terminal of the resistors is connected to the power supply and the other is connected to receive the first and second output current signals S.sub.curr_a, S.sub.curr_b.

[0099] In another embodiment, the load network (303) can be realized by a network of transistors, configured to work in saturation region to achieve a high voltage gain.

[0100] The analog dither circuit (304), as an example implementation, is coupled in series between the first and second source terminals S.sub.source_a, S.sub.source_b of the pair of input transistors (302) and to an output S.sub.current of the current source (301) and is coupled to the plurality of digital dither signals S.sub.di.

[0101] FIG. 4 illustrates an example embodiment of the analog dither circuit (304) according to this invention. The analog dither circuit (304) comprises a plurality of resistors (401) biased in linear region, coupled in series, and a plurality of transistors as switches (402). The transistors belonging to the plurality of transistors as switches (402) are configured to function as switches. The plurality of resistors (401) can comprise R0 through RX, coupled in series, all of which can be of the same or different predetermined resistance values. The plurality of transistors as switches (402) comprise M0 through MY. The number of the plurality of transistors as switches (402) must be the same as the number bits of the plurality of digital dither signals S.sub.di. The number of the plurality of resistors (401) must be at least one more than the number of the plurality of transistors as switches (402).

[0102] In another embodiment, the plurality of resistors (401) can be replaced by a plurality of transistors biased in linear region.

[0103] FIG. 5 illustrates an example embodiment of the analog dither circuit (304) which is coupled in series between the first and second source terminals S.sub.source_a, S.sub.source_b of the pair of input transistors (302) and to the output S.sub.current of the current source (301) and is coupled to the plurality of digital dither signals S.sub.di. The analog dither circuit (304) comprises the plurality of resistors (401) biased in linear region, coupled in series and the plurality of transistors as switches (402). The plurality of resistors (401) can comprise a first resistor R0 through an eighth resistor R7, all of which can be of the same or different predetermined resistance values. The plurality of transistors as switches (402) can comprise a first transistor M0 through a seventh transistor M6. The left and right terminals (403, 404) of the plurality of resistors (401) are coupled to the first and second source terminals S.sub.source_a, S.sub.source_b respectively of the pair of input transistors (302) S.sub.source_a, S.sub.source_b. Transistors of the plurality of transistors as switches (402) are coupled with terminals of resistors belonging to the plurality of resistors (401) at drain terminals.

[0104] The example embodiment according to FIG. 5 is described as follows.

[0105] A drain terminal (501) of first transistor M0 is coupled to the terminal between the first resistor R0 and a second resistor R1. A drain terminal (502) of second transistor M1 is coupled to the terminal between the second resistor R1 and a third resistor R2. A drain terminal (503) of third transistor M2 is coupled to the terminal between the third resistor R2 and a fourth resistor R3. A drain terminal (504) of fourth transistor M3 is coupled to the terminal between the fourth resistor R3 and a fifth resistor R4. A drain terminal (505) of fifth transistor M4 is coupled to the terminal between the fifth resistor R4 and a sixth resistor R5. A drain terminal (506) of sixth transistor M5 is coupled to the terminal between the sixth resistor R5 and a seventh resistor R6. And a drain terminal (507) of seventh transistor M6 is coupled to the terminal between the seventh resistor R6 and a eighth resistor R7. The plurality of digital dither signals S.sub.di are coupled to the plurality of transistors as switches (402) at control terminals (405) such that each transistor of the plurality of transistors as switches (402) is only, but not limited to, coupled with one digital dither signal from the plurality of digital dither signals S.sub.di. The plurality of transistors as switches (402) are coupled with the output S.sub.current of the current source (301) at source terminals (406).

[0106] The analog dither circuit (304) divides the bias current from the current source (301) to each transistor, belonging to the pair of input transistors (302), in which the current division ratio of the divided current depends on the plurality of digital dither signals S.sub.di. The plurality of digital dither signals S.sub.di controls the current division ratio by controlling which transistor, belonging to the plurality of transistors as switches (402), to turn on. When one of the transistors, belonging to the plurality of transistors as switches (402), is turned on, the transistor provides a current path from the output S.sub.current of the current source (301) to one of the terminals of the plurality of resistors (401).

[0107] In an example of the operation of the analog dither circuit (304) referred to FIG. 5, the plurality of digital dither signals S.sub.di controls the fourth transistor M3 to turn on while the others, first transistor M0 through third transistor M2 and fifth transistor M4 through seventh transistor M6 are turned off. In this example, a current path between the output S.sub.current of the current source (301) and the terminal between the fourth resistor R3 and the fifth resistor R4 is provided by the fourth transistor M3. The current between the first and second source terminals S.sub.source_a, S.sub.source_b of the pair of input transistors (302) is divided equally because the resistance between the first source terminal S.sub.source_a of the pair of input transistors (302) to the output S.sub.current of the current source (301) is equal to the resistance between the second source terminal S.sub.source_b of the pair of input transistors (302) and to the output S.sub.current of the current source (301), this assumes that the voltage at the first and second source terminals S.sub.source_a, S.sub.source_b of the pair of input transistors (302) are the same.

[0108] In further example of the operation of the analog dither circuit (304) referred to FIG. 5, the plurality of digital dither signals S.sub.di controls the second transistor M1 to turn on while the others, first transistor M0 and third transistor M2 through seventh transistor M6 are turned off. In this example, a current path between the output S.sub.current of the current source (301) and the terminal between the second resistor R1 and the third resistor R2 is provided by the second transistor M1. The current between the first and second source terminals S.sub.source_a, S.sub.source_b of the pair of input transistors (302) is divided with a ratio of 3:1 because the resistance between the first source terminal S.sub.source_a of the pair of input transistors (302) to output S.sub.current of the current source (301) is three times less than the resistance between the second source terminal S.sub.source_b of the pair of input transistors (302) to output S.sub.current of the current source (301), this assumes that the voltage at the first and second source terminals S.sub.source_a, S.sub.source_b of the pair of input transistors (302) are the same. Such difference in current values between the first and second source terminals S.sub.source_a, S.sub.source_b of the pair of input transistors (302), controlled by the plurality of digital dither signals S.sub.di, also affects, regarding their values, the first and second output current signals S.sub.curr_a, S.sub.curr_B, according to the current division ratio from the first and second source terminals S.sub.source_a, S.sub.source_b of the pair of input transistors (302), which affects, regarding their values, the first and second output signals S.sub.cmp_a, S.sub.cmp_b of the input stage (201) proportional to the first and second output current signals S.sub.curr_a, S.sub.curr_b, regarding their values, respectively.

[0109] FIG. 6 illustrates an example block diagram of the digital dither generator (101) according to this invention. The digital dither generator (101) comprises a dither pattern generator (601) and a binary decoder (602) which are coupled together. The binary decoder (602) is configured to receive, for example, a plurality of binary representation of a dither pattern S.sub.di_bin from the dither pattern generator (601) and to output the plurality of digital dither signals S.sub.di.

[0110] The dither pattern generator (601) generates the plurality of binary representation of a dither pattern S.sub.di_bin. The dither pattern generator (601) can comprise, for example, a pseudo-random pattern generator.

[0111] The plurality of binary representation of a dither pattern S.sub.di_bin from the dither pattern generator (601) can have a set of preferable characteristics such as a uniform amplitude distribution, multi levels of amplitude representation, or a random pattern or combination of the mentioned.

[0112] The plurality of binary representation of a dither pattern S.sub.di_bin is received by the binary decoder (602) which generates the plurality of digital dither signals S.sub.di, received by the analog dither circuit (304).

[0113] FIG. 7 illustrates example implementation of the binary decoder (602) of the digital dither generator (101) according to the invention. The binary decoder (602) mainly comprises a N-to-M binary decoder (701) for decoding the plurality of binary representation of a dither pattern S.sub.di_bin, which is as a plurality of binary coded inputs, a0 to a(N?1). The N-to-M binary decoder (701), then produces the plurality of digital dither signals S.sub.di, which is as a plurality of decoded outputs, b0 to b(M?1). A number of decoded output bits (M) are correlated to a number of binary coded input bits (N) and can be calculated as M=2N. The state of the plurality of decoded outputs corresponds to the binary value of the plurality of binary coded inputs. The plurality of decoded outputs with the number of decoded output bits equal to M can be referred to as a M-bit decoded output. The plurality of binary coded inputs with the number of binary coded input bits equal to N can be referred to as a N-bit binary coded input.

[0114] As would be well known by the person skilled in the art, a suitable value for M is dictated by the required number of levels of amplitude of dithering, which depends on the requirement of the practical system.

[0115] FIG. 8 illustrates an example embodiment of the binary decoder (602) according to this invention suitable for, but not limited to, the analog dither circuit (304) referred to FIG. 5. In this example, the binary decoder (602) comprises a 3-to-8 binary decoder (801) which receives a 3-bit binary coded input (also meaning three representations of a dither pattern of the plurality of representation of a dither pattern) and then produces an 8-bit decoded output (also meaning eight digital dither signals of the plurality of digital dither signals S.sub.di). In a certain example of the 3-to-8 binary decoder (801), the 3-to-8 binary decoder (801) can include three NOT gates (901) and eight three-input AND gates (902), connected in a specific way, as shown in FIG. 8. The 8-bit decoded output, which is able to refer to in this example as the plurality of digital dither signals S.sub.di, is coupled to the control terminals (405) of the plurality of transistors as switches (402), where one of the 8-bit decoded output is to be intentionally left unconnected because the number of transistors belonging to the plurality of transistors as switches (402) is seven while the number of decoded output bits is equal to eight.

[0116] As an example, referring to FIG. 5 and FIG. 8, some signals belonging to the plurality of decoded outputs, for example b1 to b7, are respectively coupled to the transistors, for example M0 to M6, belonging to the plurality of transistors as switches (402) where, in this example, b0 is to be intentionally left uncoupled. If, for example, the state of the inputs belonging to the plurality of binary coded inputs have the digital logic LOW at a0, the digital logic HIGH at a1 and the digital logic LOW at a2, only the decoded output b2, belonging to the plurality of decoded outputs, has the digital logic HIGH, which turns the transistor M1 belonging to the plurality of transistors as switches (402) on since the decoded output b2 is directly coupled with the transistor M1, belonging to the plurality of transistors as switches (402). While the decoded outputs b1, b3, b4, b5, b6 and b7, belonging to the plurality of decoded outputs have the digital logic LOW which turn the transistors M0, M2, M3, M4, M5 and M6 belonging to the plurality of transistors as switches (402) off.

[0117] Noted that for the plurality of decoded outputs which is as the plurality of digital dither signals S.sub.di, only one of the plurality of the decoded outputs can be of logic HIGH at a given time. The decoded output (also called digital dither signal) of the plurality of decoded outputs which is of logic HIGH, controls only one transistor, coupled with the decoded output, in the plurality of transistors as switches (402) to turn on, while turning off for other transistors in the plurality of transistors as switches (402).

[0118] In a practical system, depending on the dithering requirement of the sigma-delta modulator based ADC (100), the number of bits generated from the digital dither generator (101) can be less for simplicity and relatively lower cost and for more uniform distribution of the plurality of digital dither signals S.sub.di. The number of the binary coded input bits must be the same as the number of bits generated from the dither pattern generator (601). The number transistors, belonging to the plurality of transistors as switches (402) in the analog dither circuit (304) must be the same as the number of the decoded output bits.