Gate drive circuit and control circuit for switching circuit, and switching power supply

Abstract

A gate drive circuit in a switching circuit including a switching terminal connected to a node that is connected to a high-side transistor and a low-side transistor, and connected to an end of a boot-strap capacitor, a bootstrap terminal connected to another end of the bootstrap capacitor, a high-side driver having an output terminal connected to a gate of the high-side transistor, an upper power supply node connected to the bootstrap terminal, and a lower power supply node connected to the switching terminal, a low-side driver having an output terminal connected to a gate of the low-side transistor, a rectifying device for applying a constant voltage to the bootstrap terminal, and a dead time controller for controlling a length of a dead time during which the high-side transistor and the low-side transistor are simultaneously turned off, based on a potential difference between the bootstrap terminal and the switching terminal.

Claims

1. A gate drive circuit for use in a switching circuit, the gate drive circuit comprising: a switching terminal connected to a node, wherein the node is connected to a high-side transistor of the switching circuit, a low-side transistor of the switching circuit, and a first end of a bootstrap capacitor of the switching circuit, and the high-side transistor is connected in series with the low-side transistor; a bootstrap terminal connected to a second end of the bootstrap capacitor; a high-side driver that includes: an output terminal connected to a gate of the high-side transistor; an upper power supply node connected to the bootstrap terminal; and a lower power supply node connected to the switching terminal; a low-side driver that includes an output terminal connected to a gate of the low-side transistor; a rectifying device configured to apply a constant voltage to the bootstrap terminal; and a dead time controller configured to control a length of a dead time during which the high-side transistor and the low-side transistor are simultaneously turned off, wherein the length of the dead time is controlled based on a potential difference between the bootstrap terminal and the switching terminal, wherein the dead time controller is further configured to feedback-control the dead time to cause the potential difference to approach a predetermined target voltage.

2. The gate drive circuit according to claim 1, wherein the dead time controller includes a comparator, the comparator is configured to compare the potential difference with the predetermined target voltage, and the dead time controller is further configured to increase or reduce the dead time based on an output signal from the comparator.

3. The gate drive circuit according to claim 1, wherein the dead time controller is further configured to control a dead time during which the high-side transistor is turned on and a dead time during which the low-side transistor is turned on, independently of each other.

4. A control circuit for controlling a direct current/direct current converter, comprising: the gate drive circuit according to claim 1.

5. A control circuit for controlling a switching circuit, the control circuit comprising: a pulse modulator configured to generate a pulse signal that is modulated to cause a feedback signal to approach a predetermined target value, wherein the switching circuit includes: a high-side transistor, a low-side transistor, and a gate drive circuit, connected to a bootstrap capacitor, to: drive the high-side transistor based on a high-side pulse signal, and drive the low-side transistor based on of a low-side pulse signal; and a dead time controller configured to: generate the high-side pulse signal and the low-side pulse signal based on the generated pulse signal; and control a length of a dead time during which the high-side transistor and the low-side transistor are simultaneously turned off, wherein the length of the dead time is controlled based on a voltage across the bootstrap capacitor, wherein the dead time controller is further configured to feedback-control the dead time to cause the voltage across the bootstrap capacitor to approach a predetermined target voltage.

6. The control circuit according to claim 5, wherein the dead time controller includes a comparator, the comparator is configured to compare the voltage across the bootstrap capacitor with the predetermined target voltage, and the dead time controller is further configured to increase or reduce the dead time based on an output signal from the comparator.

7. The control circuit according to claim 5, wherein the dead time controller is further configured to control a dead time during which the high-side transistor is turned on and a dead time during which the low-side transistor is turned on, independently of each other.

8. The control circuit according to claim 5, wherein the switching circuit is part of a switching power supply.

9. The control circuit according to claim 8, wherein the switching power supply is an insulated power supply, the gate drive circuit is disposed on a primary side of the insulated power supply, and the control circuit is disposed on a secondary side of the insulated power supply, and the high-side pulse signal and the low-side pulse signal are supplied through a coupler to the gate drive circuit.

10. A switching power supply, comprising: the control circuit according to claim 5.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a circuit diagram, partly in block form, of a switching circuit according to the related art;

(2) FIG. 2 is a circuit diagram, partly in block form, of a switching circuit incorporating a gate drive circuit according to Embodiment 1 of the present disclosure;

(3) FIG. 3 is a diagram illustrating the waveforms of signals of the switching circuit while in operation;

(4) FIG. 4 is a diagram illustrating the manner in which a bootstrap capacitor CB is charged;

(5) FIG. 5 is a diagram illustrating the relationship between the length of a dead time Td and a high-side power supply voltage VBS;

(6) FIG. 6 is a circuit diagram, partly in block form, of a configurational example of the gate drive circuit;

(7) FIG. 7 is a flowchart of a dead time optimizing process carried out by a dead time controller illustrated in FIG. 6;

(8) FIG. 8 is a circuit diagram, partly in block form, of a DC/DC converter incorporating the gate drive circuit;

(9) FIG. 9 is a circuit diagram, partly in block form, of a DC/DC converter according to a modification;

(10) FIGS. 10A through 10F are circuit diagrams of DC/DC converters each incorporating the gate drive circuit;

(11) FIG. 11 is a circuit diagram, partly in block form, of a switching circuit according to Embodiment 2 of the present disclosure;

(12) FIG. 12 is a circuit diagram, partly in block form, of a DC/DC converter incorporating the switching circuit illustrated in FIG. 11; and

(13) FIG. 13 is a circuit diagram, partly in block form, of an insulated power supply.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

(14) Preferred embodiments of the present disclosure will hereinafter be described in detail below with reference to the drawings. Components, members, and processes that are identical or equivalent to each other in the drawings will be denoted by identical reference characters, and their redundant description will be omitted. The embodiments do not limit the present disclosure and are illustrative, and all features and combinations thereof described in the embodiments may not necessarily be essential to the disclosure.

(15) In the present description, a state where “a member A is connected to a member B” covers a state where the member A and the member B are physically connected directly to each other and a state where the member A and the member B are connected indirectly to each other through another member that may not essentially affect the electrical connection therebetween or that does not impair functions or effects provided by their connection.

(16) Similarly, a state where “a member C is provided between a member A and a member B” covers a state where the member A and the member C or the member B and the member C are connected directly to each other and a state where they are connected indirectly to each other through another member that may not essentially affect the electrical connection therebetween or that does not impair functions or effects provided by their connection.

Embodiment 1

(17) FIG. 2 is a circuit diagram, partly in block form, of a switching circuit 100 incorporating a gate drive circuit 200 according to Embodiment 1 of the present disclosure. The switching circuit 100 includes a high-side transistor MH, a low-side transistor ML, a bootstrap capacitor CB, and the gate drive circuit 200. The high-side transistor MH and the low-side transistor ML are constructed as GaN-HEMTs (GaN-field effect transistors (FETs)).

(18) The gate drive circuit 200 receives a pulsed input signal at its input pin or terminal IN, and controls the high-side transistor MH and the low-side transistor ML in response to the input signal IN. When the input signal IN is high, for example, the high-side transistor MH is turned on and the low-side transistor ML is turned off, making a voltage V.sub.S at a switching terminal SW high. When the input signal IN is low, the high-side transistor MH is turned off and the low-side transistor ML is turned on, making the voltage V.sub.S at the switching terminal SW low.

(19) The gate drive circuit 200 includes a high-side driver 202, a low-side driver 204, a level shifter 206, a dead time controller 210, and a diode D1, and is integrated on one semiconductor board.

(20) The gate drive circuit 200 has an output pin HO connected to the gate of the high-side transistor MH and a switching pin or terminal VS connected to the source of the high-side transistor MH and the drain of the low-side transistor ML. The gate drive circuit 200 has an output pin LO connected to the gate of the low-side transistor ML.

(21) The dead time controller 210 generates two pulse signals, i.e., a high-side pulse signal SH and a low-side pulse signal SL, that go complementarily high, on the basis of the input signal IN. The high-side pulse signal SH has high intervals corresponding to high intervals of the input signal IN, and the low-side pulse signal SL has high intervals corresponding to low intervals of the input signal IN. The dead time controller 210 inserts dead times during which both the high-side pulse signal SH and the low-side pulse signal SL are turned off, each time the input signal IN changes in level, so that the high-side transistor MH and the low-side transistor ML will not simultaneously be turned on.

(22) The low-side driver 204 drives the low-side transistor ML on the basis of the low-side pulse signal SL. The high-side pulse signal SH is input through the level shifter 206 to the high-side driver 202. The high-side driver 202 has an upper power supply node N1 connected to a bootstrap pin VB and a lower power supply node N2 connected to the switching pin VS. The high-side driver 202 drives the high-side transistor MH on the basis of a high-side pulse signal SH′ output from the level shifter 206 after it has shifted the level of the high-side pulse signal SH.

(23) The bootstrap capacitor CB has one end connected to the switching pin VS and another end connected to the bootstrap pin VB. The diode D1 has a cathode connected through the bootstrap pin VB to the other end of the bootstrap capacitor CB and an anode to which a constant voltage V.sub.REG is applied.

(24) The high-side driver 202 operates at a power supply voltage applied as the potential difference V.sub.BS=V.sub.B−V.sub.S between the bootstrap pin VB and the switching pin VS, i.e., the voltage across the bootstrap capacitor CB. Therefore, V.sub.BS will also be referred to as a high-side power supply voltage.

(25) The dead time controller 210 controls the lengths of dead times Td during which the high-side transistor MH and the low-side transistor ML are simultaneously turned off on the basis of the high-side power supply voltage V.sub.BS.

(26) The switching circuit 100 is constructed as described above. FIG. 3 is a diagram illustrating the waveforms of signals of the switching circuit 100 while in operation. FIG. 3 illustrates the input signal IN, the high-side pulse signal SH, the low-side pulse signal SL, and the voltage V.sub.S at the switching terminal SW. The low-side pulse signal SL goes low at a positive-going edge of the input signal IN. The high-side pulse signal SH goes high after elapse of the dead time Td from the positive-going edge of the input signal IN. The high-side pulse signal SH goes low at a negative-going edge of the input signal IN. The low-side pulse signal SL goes high after elapse of the dead time Td from the negative-going edge of the input signal IN. During the dead time Td, the voltage V.sub.S at the switching terminal SW, also referred to as the switching voltage V.sub.S, becomes a negative voltage depending on the drain-to-source voltage V.sub.DS of the low-side transistor ML through which a reverse current flows.

(27) FIG. 4 is a diagram illustrating the manner in which the bootstrap capacitor CB is charged. While the switching voltage V.sub.S is low, i.e., 0 V, 0 V is applied to the one end of the bootstrap capacitor CB and a voltage of V.sub.REG−Vf is applied to the other end thereof. Therefore, the voltage V.sub.BS across the bootstrap capacitor CB becomes V.sub.REG−Vf. In the subsequent dead time Td, when the voltage V.sub.S at the one end of the bootstrap capacitor CB becomes −V.sub.DS, the bootstrap capacitor CB is further charged, resulting in a further rise ΔV in the voltage V.sub.BS across the bootstrap capacitor CB. The longer the dead time Td is, the larger the rise ΔV is, and the shorter the dead time Td is, the smaller the rise ΔV is.

(28) FIG. 5 is a diagram illustrating the relationship between the length of the dead time Td and the high-side power supply voltage V.sub.BS. The high-side power supply voltage V.sub.BS increases monotonously with the dead time Td. The dead time controller 210 establishes a target value V.sub.BS(REF) for the high-side power supply voltage V.sub.BS, and controls the dead time Td such that the dead time Td becomes shorter when the high-side power supply voltage V.sub.BS is higher than the target value V.sub.BS(REF) and the dead time Td becomes longer when the high-side power supply voltage V.sub.BS is lower than the target value V.sub.BS(REF), thereby preventing the high-side power supply voltage V.sub.BS from becoming an overvoltage.

(29) FIG. 6 is a circuit diagram, partly in block form, of a configurational example of the gate drive circuit 200. The dead time controller 210 includes a comparator 212, a level shifter 213, a dead time adjusting circuit 214, and a pulse generator 216.

(30) The comparator 212 operates using a switching line VS for a reference voltage. The comparator 212 compares a voltage produced by dividing the high-side power supply voltage V.sub.BS with a predetermined threshold voltage V.sub.TH, and outputs a comparison signal COMP. The comparison signal COMP is converted, by the level shifter 213, into a comparison signal COMP′ using a ground voltage of 0 V as a reference voltage. The dead time adjusting circuit 214 increases or reduces the set value of the dead time Td depending on the value of the comparison signal COMP′. The pulse generator 216 generates two pulse signals SH and SL on the basis of the set value of the dead time Td adjusted by the dead time adjusting circuit 214. The pulse generator 216 is not limited to any particular configuration, and may be a combination of an up counter or down counter whose count varies depending on the output from the dead time adjusting circuit 214 and a flip-flop. Alternatively, the pulse generator 216 may include a delay circuit whose delay varies depending on the output from the dead time adjusting circuit 214.

(31) FIG. 7 is a flowchart of a dead time optimizing process carried out by the dead time controller 210 illustrated in FIG. 6. The dead time Td includes a dead time Td1 immediately after a positive-going edge of the input signal IN and a dead time Td2 immediately after a negative-going edge of the input signal IN. Since the dead time Td1 and the dead time Td2 suffer from respective independent factors for varying themselves, the dead time controller 210 should control the two dead times Td1 and Td2 independently of each other.

(32) First, the dead time controller 210 sets the two dead times Td1 and Td2 to respective initial values Td1_init and Td2_init in step S100.

(33) Then, the dead time controller 210 measures an initial value V.sub.BS_init of the high-side power supply voltage V.sub.BS in step S102. Then, the dead time controller 210 gives perturbation to the dead time Td1 in step S104. The dead time Td1 should be as short as possible for higher efficiency as long as no through current flows. Therefore, the perturbation is given in a direction to reduce the dead time Td1, as follows:
Td1=Td1−Δtd1
where Δtd1 represents a perturbation range.

(34) The high-side power supply voltage V.sub.BS to which the perturbation has been given is measured in step S106, and a fluctuation range ΔV.sub.BS=|V.sub.BS−V.sub.BS_init| of the high-side power supply voltage V.sub.BS to which the perturbation has been given is calculated in step S108. Then, the perturbation is canceled in step S110, as follows:
Td1=Td1+Δtd1

(35) In a region where the dead times Td1 and Td2 are small, the sensitivity of the high-side power supply voltage V.sub.BS to the dead times Td1 and Td2 is lowered, as illustrated in FIG. 5. In this region, there is a high risk of a through current to flow. In order to avoid the risk, the fluctuation range ΔV.sub.BS due to the perturbation is compared with a minute threshold value A in step S112. If ΔV.sub.BS<A (Y in step S112), then, since there is a possibility that a through current may flow, the dead time Td1 is increased in step S116.

(36) If ΔV.sub.BS>A (N in step S112), then the possibility that a through current may flow is low. In this case, the high-side power supply voltage V.sub.BS is compared with its target level V.sub.BS(REF) in step S114. If V.sub.BS>V.sub.BS(REF) (Y in step S114), then the dead time Td1 is reduced in step S116. If V.sub.BS<V.sub.BS(REF) (N in step S114), then the dead time Td1 is increased in step S118.

(37) In steps S202 through S218, the same process as steps S102 through S118 is carried out on the dead time Td2.

(38) An application of the gate drive circuit 200 will be described below.

(39) FIG. 8 is a circuit diagram, partly in block form, of a DC/DC converter 300 incorporating the gate drive circuit 200. The DC/DC converter 300 is a step-down, i.e., buck, converter and includes, in addition to the gate drive circuit 200, an inductor L1, an output capacitor C1, and a controller 310. The controller 310 acts as a pulse modulator for generating a pulse signal S.sub.p that is modulated in order to cause an output voltage or an output current of the DC/DC converter 300 to approach a target state. The pulse signal S.sub.p is supplied to the input terminal IN of the gate drive circuit 200.

(40) FIG. 9 is a circuit diagram, partly in block form, of a DC/DC converter 300 according to a modification. According to the modification, the controller 310 and the gate drive circuit 200 illustrated in FIG. 8 are integrated in an IC 400, i.e., a control circuit of the DC/DC converter 300.

(41) In a case where the switching circuit is constructed as a digital control power supply, then the pulse modulator 310 may generate a duty cycle command value instead of the pulse signal S.sub.p, and the dead time controller 210 may generate a high-side pulse signal SH and a low-side pulse signal SL on the basis of the duty cycle command value.

(42) The application of the gate drive circuit 200 is not limited to the step-down converter. FIGS. 10A through 10F are circuit diagrams of DC/DC converters each incorporating the gate drive circuit. The gate drive circuit 200 can be used to drive a pair of transistors A and B of a step-down converter illustrated in FIG. 10A. This application has been described above with reference to FIG. 8.

(43) The gate drive circuit 200 is also applicable to a forward converter illustrated in FIG. 10B. Specifically, as illustrated in FIG. 10B, the gate drive circuit 200 can be used to drive a pair of a high-side transistor B and a low-side transistor A on the primary side.

(44) The gate drive circuit 200 is also applicable to a half-bridge converter illustrated in FIG. 10C. Specifically, as illustrated in FIG. 10C, the gate drive circuit 200 can be used to drive a pair of a high-side transistor B and a low-side transistor A on the primary side.

(45) The gate drive circuit 200 is also applicable to a full-bridge converter illustrated in FIG. 10D. Specifically, as illustrated in FIG. 10D, the gate drive circuit 200 can be used to drive a pair of a high-side transistor B and a low-side transistor A on the primary side and a pair of a high-side transistor D and a low-side transistor C on the primary side.

(46) The gate drive circuit 200 is also applicable to a current-doubler synchronous rectifier illustrated in FIG. 10E. Specifically, as illustrated in FIG. 10E, the gate drive circuit 200 can be used to drive a pair of a high-side transistor B and a low-side transistor A on the primary side.

(47) The gate drive circuit 200 is also applicable to a secondary-side full-bridge synchronous rectifier illustrated in FIG. 10F. Specifically, as illustrated in FIG. 10F, the gate drive circuit 200 can be used to drive a pair of a high-side transistor B and a low-side transistor A on the primary side or a pair of a high-side transistor C and a low-side transistor D on the primary side. Furthermore, the gate drive circuit 200 can be used to drive a pair of a high-side transistor F and a low-side transistor E on the secondary side or a pair of a high-side transistor G and a low-side transistor H on the secondary side.

Embodiment 2

(48) According to Embodiment 1, the gate drive circuit 200 has a function to automatically adjust the dead time. However, the present disclosure is not limited to such a detail. FIG. 11 is a circuit diagram, partly in block form, of a switching circuit 500 according to Embodiment 2 of the present disclosure. The switching circuit 500 includes a gate drive circuit 200R and a controller 600.

(49) The gate drive circuit 200R has input terminals HIN and LIN and drives the high-side transistor MH and the low-side transistor ML on the basis of pulse signals applied respectively to the input terminals HIN and LIN.

(50) The controller 600 includes a pulse modulator 602 and a dead time controller 604.

(51) The pulse modulator 602 generates a pulse signal S.sub.p that is modulated in order to cause a feedback signal S.sub.FB indicative of the state of an apparatus, a circuit, or a system that incorporates the switching circuit 500 to approach a predetermined target state. The dead time controller 604 generates a high-side pulse signal SH and a low-side pulse signal SL on the basis of the pulse signal S.sub.p. The dead time controller 604 controls the lengths of dead times Td during which the high-side transistor MH and the low-side transistor ML are simultaneously turned off on the basis of the voltage V.sub.BS across the bootstrap capacitor CB. The dead time controller 604 is the same as the dead time controller 210 illustrated in FIG. 2.

(52) In a case where the switching circuit is constructed as a digital control power supply, then the pulse modulator 602 may generate a duty cycle command value instead of the pulse signal S.sub.p, and the dead time controller 604 may generate a high-side pulse signal SH and a low-side pulse signal SL on the basis of the duty cycle command value.

(53) FIG. 12 is a circuit diagram, partly in block form, of a DC/DC converter 300A incorporating the switching circuit 500 illustrated in FIG. 11. The DC/DC converter 300A is a step-down, i.e., buck, converter and includes, in addition to the switching circuit 500, an inductor L1 and a capacitor C1.

(54) The application of the switching circuit 500 is not limited to the step-down converter, and may be used in any of the various switching power supplies illustrated in FIGS. 10B through 10F.

(55) FIG. 13 is a circuit diagram, partly in block form, of an insulated power supply 700. The insulated power supply 700 is similar to the forward converter illustrated in FIG. 10B, and includes a controller 710, a gate drive circuit 720 on the primary side, a gate drive circuit 730 on the secondary side, and a coupler 740. The primary side and the secondary side are insulated from each other, with the controller 710 being disposed on the secondary side.

(56) The controller 710 is constructed similarly to the controller 600 illustrated in FIG. 11, and includes a pulse modulator 712 and a dead time controller 714. Those blocks of the controller 710 that are involved in the control of the secondary side are omitted, and may be arranged according to the related art. The pulse modulator 712 generates a pulse signal S.sub.p in order to cause a feedback signal S.sub.FB to approach a target value. The dead time controller 714 generates a high-side pulse signal SH and a low-side pulse signal SL on the basis of the pulsed signal S.sub.p and outputs the high-side pulse signal SH and the low-side pulse signal SL from respective output pins HO1 and LO1. The high-side pulse signal SH and the low-side pulse signal SL are supplied through the coupler 740 to the gate drive circuit 720 on the primary side. The dead time controller 714 is supplied with information regarding a voltage V.sub.BS between VB and VS pins on the primary side.

(57) In a case where the switching circuit is constructed as a digital control power supply, then the pulse modulator 712 may generate a duty cycle command value instead of the pulse signal S.sub.p, and the dead time controller 714 may generate a high-side pulse signal SH and a low-side pulse signal SL on the basis of the duty cycle command value.

(58) Information INFO regarding the voltage V.sub.BS may be generated and transmitted in various ways. For example, the voltage V.sub.BS may be compared in magnitude with the target value V.sub.BS(REF) on the primary side and a digital signal representing the result of comparison may be transmitted from the primary side through a coupler to the secondary side. Alternatively, an analog signal representing an error of the voltage V.sub.BS with respect to the target value V.sub.BS(REF) may be generated on the primary side and may be transmitted from the primary side through a photocoupler to the secondary side. Further alternatively, a digital signal representing an error of the voltage V.sub.BS with respect to the target value V.sub.BS(REF) may be generated on the primary side and may be transmitted from the primary side through a coupler to the secondary side. The dead time controller 714 performs feedback control on the dead times of the high-side pulse signal SH and the low-side pulse signal SL in order to cause the voltage V.sub.BS to approach the target value V.sub.BS(REF) on the basis of the information INFO transmitted from the primary side.

(59) The embodiments of the present disclosure have been described above. However, the embodiments are illustrated by way of example and the components and processes of the embodiments and their combinations may be modified within the scope of the present disclosure as anticipated by those skilled in the art. Some modifications of the embodiments will be described below.

(60) The process of feedback of the dead times is not limited to the sequence according to the flowchart illustrated in FIG. 7. An error of the high-side power supply voltage V.sub.BS with respect to the target value V.sub.BS(REF) may be amplified by an error amplifier, and the lengths of the deal times may be set depending on an output signal from the error amplifier. Alternatively, the high-side power supply voltage V.sub.BS may be converted into a digital signal, and the lengths of the dead times may be feedback-controlled by a proportional-integral (PI) compensator or a proportional-integral-differential (PID) compensator in order to cause an error of the high-side power supply voltage V.sub.BS to approach zero.

(61) The switching circuit is used in various applications including power supplies, motor drive circuits, etc. The present disclosure is applicable to applications other than power supplies.

(62) Although the preferred embodiments of the present disclosure have been described in detail above, it should be understood that the embodiments illustrate principles and applications by way of example and various many changes and modifications may be made therein without departing from the scope of the disclosure as called for in the attached claims.