Nitride crystal, nitride crystal substrate, epilayer-containing nitride crystal substrate, semiconductor device and method of manufacturing the same

Abstract

A nitride crystal is characterized in that, in connection with plane spacing of arbitrary specific parallel crystal lattice planes of the nitride crystal obtained from X-ray diffraction measurement performed with variation of X-ray penetration depth from a surface of the crystal while X-ray diffraction conditions of the specific parallel crystal lattice planes are satisfied, a uniform distortion at a surface layer of the crystal represented by a value of |d.sub.1d.sub.2|/d.sub.2 obtained from the plane spacing d.sub.1 at the X-ray penetration depth of 0.3 m and the plane spacing d.sub.2 at the X-ray penetration depth of 5 m is equal to or lower than 2.110.sup.3. The above configuration provides the nitride crystal having a crystal surface layer that is evaluated directly and reliably without breaking the crystal so that it can be used in a preferred fashion as a substrate for a semiconductor device as well as the nitride crystal substrate, an epilayer-containing nitride crystal substrate, a semiconductor device and a method of manufacturing the same.

Claims

1. An epilayer-containing nitride crystal substrate comprising: one or more semiconductor layer(s) formed by epitaxial growth on at least one of main surface sides of a nitride crystal substrate formed of a nitride crystal, wherein, in connection with plane spacing of arbitrary specific parallel crystal lattice planes of the nitride crystal obtained from X-ray diffraction measurement performed with variation of X-ray penetration depth from a surface of said crystal while X-ray diffraction conditions of said specific parallel crystal lattice planes being satisfied, a uniform distortion at a surface layer of said crystal represented by a value of |d.sub.1d.sub.2|/d.sub.2 obtained from said plane spacing d.sub.1 at said X-ray penetration depth of 0.3 mm and said plane spacing d.sub.2 at the X-ray penetration depth of 5 mm is equal to or lower than 2.110.sup.3.

2. An epilayer-containing nitride crystal substrate comprising: one or more semiconductor layer(s) formed by epitaxial growth on at least one of main surface sides of a nitride crystal substrate formed of a nitride crystal, wherein, on a diffraction intensity profile of arbitrary specific parallel crystal lattice planes of the nitride crystal obtained from X-ray diffraction measurement performed with variation of X-ray penetration depth from a surface of said crystal while X-ray diffraction conditions of said specific parallel crystal lattice planes being satisfied, an irregular distortion at a surface layer of said crystal represented by a value of |v.sub.1v.sub.2| obtained from a half value width v.sub.1 of a diffraction intensity peak at said X-ray penetration depth of 0.3 mm and a half value width v.sub.2 of the diffraction intensity peak at said X-ray penetration depth of 5 mm is equal to or lower than 150 arcsec.

3. An epilayer-containing nitride crystal substrate comprising: one or more semiconductor layer(s) formed by epitaxial growth on at least one of main surface sides of a nitride crystal substrate formed of a nitride crystal, wherein, on a rocking curve measured by varying an X-ray penetration depth from a surface of the nitride crystal in connection with X-ray diffraction of arbitrary specific parallel crystal lattice planes of said crystal, a plane orientation deviation of said specific parallel crystal lattice planes represented by a value of |w.sub.1w.sub.2| obtained from a half value width w.sub.1 of a diffraction intensity peak at said X-ray penetration depth of 0.3 mm and a half value width w.sub.2 of the diffraction intensity peak at said X-ray penetration depth of 5 mm is equal to or lower than 400 arcsec.

4. A method of manufacturing an epilayer-containing nitride crystal substrate according to claim 1, comprising the steps of: selecting, as said nitride crystal substrate, nitride crystal configured such that, in connection with plane spacing of arbitrary specific parallel crystal lattice planes of said crystal obtained from X-ray diffraction measurement performed with variation of X-ray penetration depth from a surface of said crystal while satisfying X-ray diffraction conditions of said specific parallel crystal lattice plane, a uniform distortion at a surface layer of said crystal represented by a value of |d.sub.1d.sub.2|/d.sub.2 obtained from said plane spacing d.sub.1 at said X-ray penetration depth of 0.3 mm and said plane spacing d.sub.2 at the X-ray penetration depth of 5 mm is equal to or lower than 2.110.sup.3; and epitaxially growing one or more semiconductor layer(s) on at least one of main surface sides of said substrate.

5. A method of manufacturing an epilayer-containing nitride crystal substrate according to claim 2, comprising the steps of: selecting, as said nitride crystal substrate, nitride crystal configured such that, on a diffraction intensity profile of arbitrary specific parallel crystal lattice planes of the crystal obtained from X-ray diffraction measurement performed with variation of X-ray penetration depth from a surface of said crystal while X-ray diffraction conditions of said specific parallel crystal lattice planes being satisfied, an irregular distortion at a surface layer of said crystal represented by a value of |v.sub.1v.sub.2| obtained from a half value width v.sub.1 of a diffraction intensity peak at the X-ray penetration depth of 0.3 mm and a half value width v.sub.2 of the diffraction intensity peak at the X-ray penetration depth of 5 mm is equal to or lower than 150 arcsec; and epitaxially growing one or more semiconductor layer(s) on at least one of main surface sides of said substrate.

6. A method of manufacturing an epilayer-containing nitride crystal substrate according to claim 3, comprising the steps of: selecting, as said nitride crystal substrate, nitride crystal configured such that, on a rocking curve measured by varying an X-ray penetration depth from a surface of said nitride crystal in connection with X-ray diffraction of arbitrary specific parallel crystal lattice planes of said crystal, a plane orientation deviation of said specific parallel crystal lattice planes represented by a value of |w.sub.1w.sub.2| obtained from a half value width w.sub.1 of a diffraction intensity peak at said X-ray penetration depth of 0.3 mm and a half value width w.sub.2 of the diffraction intensity peak at said X-ray penetration depth of 5 mm is equal to or lower than 400 arcsec; and epitaxially growing one or more semiconductor layer(s) on at least one of main surface sides of said substrate.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a schematic section showing a state of a crystal in a depth direction from a crystal surface.

(2) FIG. 2 is a schematic view showing measurement axes and measurement angles in an X-ray diffraction method according to the invention.

(3) FIG. 3 schematically illustrates a relationship between a uniform distortion of a crystal lattice of a nitride crystal and plane spacing of specific parallel crystal lattice planes is shown on a diffraction profile in the X-ray diffraction method. At (a), the uniform distortion of the crystal lattice is illustrated. At (b), the plane spacing of the specific parallel crystal lattice plane is shown on the diffraction profile.

(4) FIG. 4 schematically illustrates a relationship between irregular distortion of a crystal lattice of a nitride crystal and a half value width of a diffraction peak on a diffraction profile in the X-ray diffraction method. At (a), the irregular distortion of the crystal lattice is illustrated. At (b), the half value width of the diffraction peak on the diffraction profile is illustrated.

(5) FIG. 5 schematically illustrates a relationship between plane orientation distortion of specific parallel crystal lattice planes of a nitride crystal and a half value width on a rocking curve in the X-ray diffraction method. At (a), the plane orientation deviation of the specific parallel crystal lattice planes is illustrated. At (b), the half value width of the diffraction peak on the rocking curve is illustrated.

(6) FIG. 6 is a schematic section showing an example of a semiconductor device according to the invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

(7) The invention employs an X-ray diffraction method, and thereby can perform direct evaluation of crystallinity at a surface layer of a nitride crystal without breaking the crystal. The evaluation of the crystallinity represents evaluation or determination of an extent or degree to which a distortion of the crystal is present, and more specifically represents evaluation of an extent or degree to which a distortion of a crystal lattice and a plane orientation deviation of the lattice plane are present. The distortion of the crystal lattice can be specifically classified into a uniform distortion caused by a uniformly distorted crystal lattice and an irregular distortion caused by an irregularly distorted crystal lattice. The plane orientation deviation of the crystal lattice planes represent a magnitude by which the plane orientation of the lattice plane of each crystal region deviates from an average orientation of the plane orientation of the lattice planes of the whole crystal lattice.

(8) As shown in FIG. 1, a nitride crystal 1 has a crystal surface layer 1a having a certain depth from a crystal surface 1s, and this crystal surface layer 1a has a uniform distortion, an irregular distortion and/or a plane orientation deviation of a crystal lattice occur in crystal surface layer 1a due to working such as cutting, grinding or polishing. The uniform distortion, irregular distortion and/or plane orientation deviation of the crystal lattice may occur in a surface-neighboring layer 1b neighboring to crystal surface layer 1a (FIG. 1 shows a case where the plane orientation deviation of the crystal lattice is present. Further, it can be considered that a crystal inner layer 1c located inside surface-neighboring layer 1b has an original crystal structure of the crystal. The states and thicknesses of crystal surface layer 1a and surface-neighboring layer 1b depend on the manner and extent of the grinding or polishing in the surface working processing.

(9) In the above structure, the uniform distortion, irregular distortion and/or plane direction deviation of the crystal lattice are evaluated in the depth direction from the surface of the crystal so that the crystallinity of the crystal surface layer can be directly and reliably evaluated.

(10) In the X-ray diffraction measurement for evaluating the crystallinity of the surface layer of the nitride crystal according to the invention, an X-ray penetration depth from the surface of the crystal is changed while X-ray diffraction conditions of arbitrary specific parallel crystal lattice planes of the nitride crystal are satisfied.

(11) The diffraction conditions of the arbitrary specific parallel crystal lattice planes represent conditions under which the arbitrarily specified parallel crystal lattice planes diffracts the X-ray. Assuming that a Bragg angle is , a wavelength of the X-ray is and a plane spacing of the crystal lattice planes is d, the X-ray is diffracted by the crystal lattice plane satisfying the Bragg's condition (2d sin =n, where n is an integer).

(12) The X-ray penetration depth represents a distance that is measured in the depth direction perpendicular to crystal surface 1s, and causes an intensity of the incident X-ray equal to 1/e where e is a base of the natural logarithm. Referring to FIG. 2, an X-ray linear absorption coefficient of crystal 1, an inclination angle of crystal surface 1s, an X-ray incident angle with respect to crystal surface 1s and a Bragg angle in crystal surface is determines X-ray penetration depth T that is expressed by an equation (1). A represents a rotation angle in crystal surface. A axis 21 is present on a plane formed by an incident X-ray 11 and an outgoing X-ray 12, a axis (2 axis) 22 is perpendicular to a plane formed by incident X-ray 11 and outgoing X-ray 12, and a axis 23 is perpendicular to crystal surface 1s.

(13) $\begin{array}{cc}T=\frac{1}{}.Math.\frac{\cos .Math.\sin .Math.\sin \left(2-\right)}{\sin +\sin \left(2-\right)}& \left(1\right)\end{array}$

(14) Therefore, X-ray penetration depth T can be continuously changed by adjusting at least one of , and to satisfy the diffraction conditions for the above specific crystal lattice planes.

(15) For continuously changing X-ray penetration depth T to satisfy the diffraction conditions for a specific crystal lattice plane 1d, it is necessary that specific crystal lattice plane 1d is not parallel to crystal surface 1s. If specific crystal lattice plane 1d is parallel to crystal surface 1s, the angle between crystal lattice plane 1d and incident X-ray 11 becomes equal to angle between crystal surface is and incident X-ray 11 so that the X-ray penetration depth cannot be changed at specific crystal lattice plane 1d.

(16) Based on the following embodiment, description will now be given on the evaluation performed in such a manner that the arbitrary specific parallel crystal lattice planes of the crystal is irradiated with the X-ray while changing the X-ray penetration depth, the uniform distortion of the crystal lattice is evaluated from the change in plane spacing on the diffraction profile relating to this specific parallel crystal lattice planes, the irregular distortion of the crystal lattice is evaluated from the change in half value width of the diffraction peak on the diffraction profile and the plane orientation deviation of the crystal lattice is evaluated from the change in half value width on the rocking curve.

First Embodiment

(17) A nitride crystal of this embodiment is characterized in that, in connection with plane spacing of arbitrary specific parallel crystal lattice planes of the crystal obtained from X-ray diffraction measurement performed with variation of X-ray penetration depth from a surface of the crystal while X-ray diffraction conditions of the specific parallel crystal lattice planes are satisfied, a uniform distortion at a surface layer of the crystal represented by a value of |d.sub.1d.sub.2|/d.sub.2 obtained from a plane spacing d.sub.1 at the X-ray penetration depth of 0.3 m and a plane spacing d.sub.2 at the X-ray penetration depth of 5 m is equal to or lower than 2.110.sup.3.

(18) Referring to FIG. 1, the X-ray penetration depth of 0.3 m corresponds to a distance from the surface of the nitride crystal to an inside of crystal surface layer 1a, and the X-ray penetration depth of 5 m corresponds to a distance from the surface of the nitride crystal to an inside of crystal inner layer 1c. Referring to FIG. 3(a), plane spacing d.sub.2 at the X-ray penetration depth of 5 m can be considered as the plane spacing of the specific parallel crystal lattice planes of the nitride crystal in the original state, but plane spacing d.sub.1 at the X-ray penetration depth of 0.3 m reflects the uniform distortion of the crystal lattice at the crystal surface layer due to an influence (e.g., a tensile stress 30 toward an inside of the crystal lattice plane) of surface working of the crystal, and therefore takes a value different from plane spacing d.sub.2 at the X-ray penetration depth of 5 m.

(19) Referring to FIG. 3(b), plane spacing d.sub.1 at the X-ray penetration depth of 0.3 m and plane spacing d.sub.2 at the X-ray penetration depth of 5 m appear on the diffraction profile relating to the arbitrary specific parallel crystal lattice planes of the crystal in the above case. Therefore, the uniform distortion of the crystal surface layer can be expressed by the value of a ratio |d.sub.1d.sub.2|/d.sub.2 of a difference between d.sub.1 and d.sub.2 with respect to d.sub.2.

(20) In the nitride crystal of this embodiment, the uniform distortion at the surface layer represented by |d.sub.1d.sub.2|/d.sub.2 is equal to or lower than 2.110.sup.3. Owing to the fact that the uniform distortion at the surface layer of the nitride crystal satisfies the relationship of |d.sub.1d.sub.2|/d.sub.22.110.sup.3, a semiconductor layer of good crystallinity can be epitaxially grown on the nitride crystal, and a semiconductor device of good characteristics can be produced.

Second Embodiment

(21) A nitride crystal of this embodiment is characterized in that, on a diffraction intensity profile of arbitrary specific parallel crystal lattice planes of the crystal obtained from X-ray diffraction measurement performed with variation of X-ray penetration depth from a surface of the crystal while X-ray diffraction conditions of the specific parallel crystal lattice planes are satisfied, an irregular distortion at a surface layer of the crystal represented by a value of |v.sub.1v.sub.2| obtained from a half value width v.sub.1 of a diffraction intensity peak at the X-ray penetration depth of 0.3 m and a half value width v.sub.2 of the diffraction intensity peak at the X-ray penetration depth of 5 m is equal to or lower than 150 arcsec.

(22) Referring to FIG. 1, the X-ray penetration depth of 0.3 m corresponds to a distance from the surface of the nitride crystal to an inside of crystal surface layer 1a, and the X-ray penetration depth of 5 m corresponds to a distance from the surface of the nitride crystal to an inside of crystal inner layer 1c. Referring to FIG. 4(a), half value width v.sub.2 of the diffraction peak at the X-ray penetration depth of 5 m can be considered as the half value width of the nitride crystal in the original state, but half value width v.sub.1 of the diffraction peak at the X-ray penetration depth of 0.3 m reflects the irregular distortion of the crystal lattice at the crystal surface layer due to an influence of surface working of the crystal (e.g., different plane spacings d.sub.3, d.sub.4-d.sub.5, d.sub.6 of the respective crystal lattice planes), and therefore takes a value different from half value width v.sub.2 of the diffraction peak at the X-ray penetration depth of 5 m.

(23) Referring to FIG. 4(b), half value width v.sub.1 of the diffraction peak at the X-ray penetration depth of 0.3 m and half value width v.sub.2 of the diffraction peak at the X-ray penetration depth of 5 m appear on the diffraction profile relating to the arbitrary specific parallel crystal lattice planes of the crystal in the above case. Therefore, the irregular distortion of the crystal surface layer can be expressed by the value of |v.sub.1v.sub.2| which is a difference between v.sub.1 and v.sub.2.

(24) In the nitride crystal of this embodiment, the irregular distortion at the surface layer represented by the value of |v.sub.1v.sub.2| is equal to or lower than 150 arcsec. Owing to the fact that the irregular distortion at the surface layer of the nitride crystal satisfies the relationship of |v.sub.1v.sub.2|150 (arcsec), a semiconductor layer of good crystallinity can be epitaxially grown on the nitride crystal, and a semiconductor device of good characteristics can be produced.

Third Embodiment

(25) A nitride crystal of this embodiment is characterized in that, on a rocking curve measured by varying an X-ray penetration depth from a crystal surface in connection with X-ray diffraction of arbitrary specific parallel crystal lattice planes of the crystal, a plane orientation deviation of the specific parallel crystal lattice planes represented by a value of |w.sub.1w.sub.2| obtained from a half value width w.sub.1 of a diffraction intensity peak at the X-ray penetration depth of 0.3 m and a half value width w.sub.2 of the diffraction intensity peak at the X-ray penetration depth of 5 m is equal to or lower than 400 arcsec.

(26) Referring to FIG. 1, the X-ray penetration depth of 0.3 m corresponds to a distance from the surface of the nitride crystal to an inside of crystal surface layer 1a, and the X-ray penetration depth of 5 m corresponds to a distance from the surface of the nitride crystal to an inside of crystal inner layer 1c. Referring to FIG. 5(a), half value width w.sub.2 at the X-ray penetration depth of 5 m can be considered as the half value width of the crystal in the original state, but half value width w.sub.1 at the X-ray penetration depth of 0.3 m reflects the plane orientation deviation of the crystal lattice at the crystal surface layer due to an influence of surface working of the crystal (e.g., different plane orientation of respective specific parallel crystal lattice planes 51d, 52d and 53d of each crystal region), and therefore takes a value different from half value width w.sub.2 at the X-ray penetration depth of 5 m.

(27) Referring to FIG. 5(b), half value width w.sub.1 at the X-ray penetration depth of 0.3 m and half value width w.sub.2 at the X-ray penetration depth of 5 m appear on the rocking curve relating to the arbitrary specific parallel crystal lattice planes of the crystal in the above case. Therefore, the plane direction deviation of the specific parallel crystal lattice planes of the crystal surface layer can be expressed by the value of |w.sub.1w.sub.2| which is a difference between w.sub.1 and w.sub.2.

(28) In the nitride crystal of this embodiment, the plane orientation deviation of the specific parallel crystal lattice planes of the surface layer represented by the value of |w.sub.1w.sub.2| is equal to or lower than 400 arcsec. Owing to the fact that the plane orientation deviation of the specific parallel crystal lattice planes of the surface layer of the nitride crystal satisfies the relationship of |w.sub.2w.sub.2|400 (arcsec), a semiconductor layer of good crystallinity can be epitaxially grown on the nitride crystal, and a semiconductor device of good characteristics can be produced.

(29) The crystallinity evaluated by the crystallinity evaluating methods of the first to third embodiments described above is not restricted to that affected by the surface working already described, and may include a distortion of the crystal and the like that occur when the crystal grows.

(30) In the nitride crystals of the first to third embodiments already described, the surface of the crystal preferably has a surface roughness Ry of 30 nm or lower. Surface roughness Ry is a sum of a height from an average plane of a sampling portion to the highest peak thereof and a depth from the average plane to the lowest bottom, and this sampling portion is extracted from a roughness curved plane as a reference area measuring 10 m per side (i.e., 10 m10 m=100 m.sup.2) in a direction of its average plane. Owing to the fact that the nitride crystal has surface roughness Ry of 30 nm or lower, the semiconductor layer of good crystallinity can be epitaxially grown on the nitride crystal, and the semiconductor device of good characteristics can be produced.

(31) In the nitride crystals of the first to third embodiments already described, the surface of the crystal preferably has a surface roughness Ra of 3 nm or lower. Surface roughness Ra is a value obtained by averaging, with a reference area, a sum of absolute values of deviations from an average plane of a sampling portion to a measurement curved surface, and this sampling portion is extracted from a roughness curved plane as a reference area measuring 10 m per side in a direction of the average plane. Owing to the fact that the nitride crystal has surface roughness Ra of 3 nm or lower, the semiconductor layer of good crystallinity can be epitaxially grown on the nitride crystal, and the semiconductor device of good characteristics can be produced.

(32) In the nitride crystals of the first to third embodiments already described, it is preferable that the surface of the crystal is parallel to a C-plane in a wurtzite structure. The C-plane represents {0001} plane and {000-1} plane. The surface of group nitride crystal is parallel to each of the above planes in the wurtzite structure or is nearly parallel (e.g., at an off angle lower than 0.05 between the surface of the nitride crystal and the C-plane in the wurtzite structure), whereby the semiconductor layer of good crystallinity can be epitaxially grown on the nitride crystal, and the semiconductor device of good characteristics can be produced.

(33) In the nitride crystals of the first to third embodiments already described, it is preferable that the surface of the crystal forms an off angle in a range from 0.05 to 15 with respect to the C-plane in the wurtzite structure. Provision of the off angle of 0.05 or more can reduce defects at the semiconductor layer that is epitaxially grown on the nitride crystal. However, when the off angle exceeds 15, a step or a difference in level is liable to occur. From the viewpoint of this, the preferable off angle is from 0.1 to 10.

Fourth Embodiment

(34) This embodiment is a nitride crystal substrate formed of the nitride crystal of the first to third embodiments already described. One or more semiconductor layer(s) are epitaxially grown on at least one of main surfaces of the nitride crystal substrate of the embodiment to provide an epilayer-containing nitride crystal substrate including the one or more semiconductor layer(s) that are the epitaxial layer(s) also referred to as the epilayer(s). In this case, the semiconductor layer can be epitaxially grown on the nitride crystal substrate when a lattice constant k.sub.0 of the nitride crystal substrate (i.e., the lattice constant in an axis perpendicular to a crystal growth plane (this explanation is also true in the following description of this embodiment)) and a lattice constant k of the semiconductor layer satisfy a relationship of (|kk.sub.0|/k)0.15. It is preferable to satisfy a relationship of (|kk.sub.0|/k)0.05. From the viewpoint of this, the semiconductor layer is preferable a III group nitride layer.

Fifth Embodiment

(35) This embodiment is a semiconductor device including one or more semiconductor layer(s) formed by epitaxial growth on at least one of main surface sides of the nitride crystal substrate of the above fourth embodiment or the above epilayer-containing nitride crystal substrate. In the semiconductor device thus obtained, since at least one of the uniform distortion, the irregular distortion and the plane orientation deviation of the surface layer of the nitride crystal used as the substrate is small, the semiconductor layer formed on at least one of the main surfaces of the nitride crystal substrate or the epilayer-containing nitride crystal substrate has good crystallinity, and good device characteristics can be obtained.

(36) The foregoing matters related to the semiconductor layer of the fourth embodiment can also be applied to the semiconductor layer of this embodiment. More specifically, the semiconductor layer can be epitaxially grown on the nitride crystal substrate when lattice constant k.sub.0 of the nitride crystal substrate (i.e., the lattice constant in an axis perpendicular to the crystal growth plane (this explanation is also true in the following description of this embodiment)) and lattice constant k of the semiconductor layer satisfy the relationship of (|kk.sub.0|/k)0.15. It is preferable to satisfy the relationship of (|kk.sub.0|/k)0.05. From the viewpoint of this, the semiconductor layer is preferable the III group nitride layer.

(37) The semiconductor device of this embodiment may be a light-emitting element such as a light-emitting diode or a laser diode, an electronic element such as a rectifier, a bipolar transistor, a field-effect transistor or a HEMT (High Electron Mobility Transistor), a semiconductor sensor such as a temperature sensor, a pressure sensor, a radiation sensor or a visible-ultraviolet ray detector, or a SAW device (Surface Acoustic Wave device).

Sixth Embodiment

(38) Referring to FIG. 6, a semiconductor device of this embodiment is a semiconductor device including the foregoing nitride crystal substrate or the epilayer-containing nitride crystal substrate as a substrate 610, and includes a light emitting element including a plurality of (i.e., three or more) semiconductor layers 650 formed by the epitaxial growth on one of the main surface sides of the nitride crystal substrate or the epilayer-containing nitride crystal substrate (substrate 610), a first electrode 661 formed on the other main surface side of the nitride crystal substrate or the epilayer-containing nitride crystal substrate (substrate 610), and a second electrode 662 formed on the outermost semiconductor layer of the plurality of semiconductor layers 650. The semiconductor device further includes a conductor 682 bearing the light emitting element. A side of the light emitting element defined by substrate 610 is a light emitting side, and a side defined by the outermost semiconductor layer side is a mount side. The plurality of semiconductor layers 650 include a p-type semiconductor layer 630, an n-type semiconductor layer 620 and a light emitting layer 640 formed between these conductive semiconductor layers. Owing to the above structure, it is possible to form the semiconductor device of which nitride crystal substrate side is the light emitting side.

(39) The semiconductor device of this embodiment has a good property of releasing heat generated by a light emitting layer as compared with a semiconductor device of which semiconductor layer side is the light emitting side. Therefore, even in the operation with a high power, temperature rising of the semiconductor device is suppressed, and light emission at high brightness can be achieved. An insulating substrate such as a sapphire substrate must have a single-side electrode structure in which two kinds of electrodes, i.e., n- and p-electrodes are formed on the semiconductor layer. However, the semiconductor device of this embodiment can have a double-sided electrode structure in which the electrodes are formed on the semiconductor layer and the substrate, respectively, and a major portion of the main surface of the semiconductor device can be used as a light emitting surface. Further, when mounting the semiconductor device, the manufacturing process can be simple, e.g., because wire boding is required only one time. This advantage and the like can also be achieved.

Seventh Embodiment

(40) This embodiment is a method of manufacturing a semiconductor device including a nitride crystal substrate or an epilayer-containing nitride crystal substrate including one or more semiconductor layer(s) formed by epitaxial growth on at least one of main surface sides of the nitride crystal substrate. This method of manufacturing the semiconductor device includes the steps of selecting the nitride crystal of the first embodiment as the nitride crystal substrate, and epitaxially growing the one or more semiconductor layer(s) on at least one of the main surface sides of the substrate.

(41) Since the nitride crystal of the first embodiment selected as the nitride crystal substrate of the semiconductor device of the seventh embodiment has the surface layer of which uniform distortion is small, the semiconductor layer of good crystallinity can be epitaxially grown on the nitride crystal, and the semiconductor device of good characteristics can be formed. The foregoing matters related to the semiconductor layers of the fourth and fifth embodiments can be applied to the semiconductor layer of the seventh embodiment.

Eighth Embodiment

(42) This embodiment is a method of manufacturing a semiconductor device including a nitride crystal substrate or an epilayer-containing nitride crystal substrate including one or more semiconductor layer(s) formed by epitaxial growth on at least one of main surface sides of the nitride crystal substrate. This method of manufacturing the semiconductor device includes the steps of selecting the nitride crystal of the second embodiment as the nitride crystal substrate, and epitaxially growing one or more semiconductor layer(s) on at least one of main surface sides of the substrate.

(43) Since the nitride crystal of the second embodiment selected as the nitride crystal substrate of the semiconductor device of the eighth embodiment has the surface layer of which irregular distortion is small, the semiconductor layer of good crystallinity can be epitaxially grown on the nitride crystal, and the semiconductor device of good characteristics can be formed. The foregoing matters related to the semiconductor layers of the fourth and fifth embodiments can be applied to the semiconductor layer of the eighth embodiment.

Ninth Embodiment

(44) This embodiment is a method of manufacturing a semiconductor device including a nitride crystal substrate or an epilayer-containing nitride crystal substrate including one or more semiconductor layer(s) formed by epitaxial growth on at least one of main surface sides of the nitride crystal substrate. This method of manufacturing the semiconductor device includes the steps of selecting the nitride crystal of the third embodiment as the nitride crystal substrate, and epitaxially growing one or more semiconductor layer(s) on at least one of main surface sides of the substrate.

(45) Since the nitride crystal of the third embodiment selected as the nitride crystal substrate of the semiconductor device of the ninth embodiment includes the surface layer having specific parallel crystal lattice planes of which plane orientation deviation is small, the semiconductor layer of good crystallinity can be epitaxially grown on the nitride crystal, and the semiconductor device of good characteristics can be formed. The foregoing matters related to the semiconductor layers of the fourth and fifth embodiments can be applied to the semiconductor layer of the ninth embodiment.

(46) The nitride crystal can be grown by a vapor phase growth method such as a HYPE (Hydride Vapor Phase Epitaxy) method or a sublimation method, or a liquid phase growth method such as a flux method.

(47) A nitride crystal that will form the nitride crystal substrate of the semiconductor device is cut from the nitride crystal obtained by the foregoing growth method, and surface working such as grinding and polishing is performed for smoothing the surfaces thereof. In the mechanical working such as grinding and mechanical polishing included in the above surface working, hard grains cut into the crystal to remove the material so that work-affected layer (damaged layer) having deteriorated crystallinity is left at the surface of the nitride crystal that will form the nitride crystal substrate. Therefore, the work-affected layer must be reduced for producing the III group nitride semiconductor layer on the substrate smoothed by the mechanical working. The CMP processing is most suitable for reducing the work-affected layer because it can reduce both the work-affected layer and the surface roughness.

(48) It is not necessary to remove completely the work-affected layer at the substrate surface, and the surface quality can be improved by annealing processing before the epitaxial growth. The annealing before the growth causes rearrangement at the crystal surfaces, and allows the epitaxial growth of the semiconductor layer of good crystallinity.

(49) As a preferred example of the surface processing method for improving the crystallinity of the surface layer of the nitride crystal, the CMP surface treatment method will now be described. It is preferable that a value x of pH and a value y (mV) of an oxidation-reduction potential in a slurry solution used in the CMP satisfy both the following equations (2) and (3):
y50x+1000(2)
y50x+1900(3)
In the case of y<50x+1000, a polishing speed becomes low. In the case of y>50x+1900, a polishing pad and a polishing device are subjected to a large corrosion effect so that stable polishing becomes difficult.

(50) From the viewpoint of further improving the polishing speed, it is further preferable to satisfy additionally the following equation (4):
y50x+1300(4)

(51) The slurry of the CMP usually contains an acid such as hydrochloric acid, sulfuric acid or nitric acid, and/or an alkali such as KOH or NaOH that are added thereto. However, the effect of oxidizing the surface of the chemically stable gallium nitride is small when such acid and/or alkali are used alone. Accordingly, it is preferable to increase the oxidation-reduction potential by adding an oxidizer so that the relationships of the foregoing equations (2) and (3), or the foregoing equations (3) and (4) may be satisfied.

(52) The oxidizer added to the slurry of the CMP is not particularly restricted, but is preferably selected from among chlorinated isocyanuric acids such as trichloroisocyanuric acid, chlorinated isocyanurates such as sodium dichloroisocyanurate, permanganates such as potassium permanganate, dichromates such as potassium dichromate, bromates such as potassium bromate, thiosulfates such as sodium thiosulfate, hypochlorous acid, nitrates, hydrogen peroxide solutions and ozone. Each of these oxidizers may be used alone, or two or more of them may be used in combination.

(53) It is preferable that the pH of slurry of the CMP is 6 or lower, or 8 or more. Acidic slurry having a pH of 6 or lower, or basic slurry having a pH of 8 or more is brought into contact with the III group nitride crystal to etch and remove the work-affected layer of the III group nitride crystal so that the polishing speed can be increased. From the viewpoint of this, it is more preferable that the pH of slurry is 4 or lower, or 10 or higher.

(54) The acid and base used for controlling the pH of slurry are not particularly restricted, and may be selected, e.g., from among inorganic acids such as hydrochloric acid, nitric acid, sulfuric acid and phosphoric acid, organic acids such as formic acid, acetic acid, citric acid, malic acid, tartaric acid, succinic acid, phthalic acid and fumaric acid, bases such as KOH, NaOH and NH.sub.4OH and amine, and salts such as sulfate, carbonate and phosphate. Also, the pH can be controlled by addition of the above oxidizer.

(55) The slurry of the CMP preferably contains grains. These grains can increase the polishing speed. The grains contained in the slurry are not particularly restricted, and may be hard grains having a higher hardness than the nitride crystal, soft grains having a lower hardness than the nitride crystal, or grain mixtures of the hard and soft grains.

Comparative Example 1

(56) An n-type MN crystal of 500 m in thickness that was grown by the HYPE method and was doped with Si was used as the nitride crystal, and was mechanically polished as follows. A Ga-side C-plane ((0001) plane) of the n-type GaN crystal having a diameter of 50 mm and a thickness of 500 m was pressed against a surface table of a lapping apparatus while supplying slurry containing diamond grains in a dispersed fashion onto the surface table, and thereby the n-type GaN crystal was mechanically polished. The surface table was a copper or tin surface table. Three kinds of grains having different diameters of 6 m, 3 m and 1 m, respectively, were prepared, and the grain diameters of the grains to be used were lowered stepwise in accordance with progress of the mechanical polishing. However, the polishing pressure in the mechanical polishing was from 100 gf/cm.sup.2 to 500 gf/cm.sup.2, and a rotation speed of the surface table was from 30 rpm to 100 rpm.

(57) Then, measuring processing was effected on the n-type GaN crystal subjected to the mechanical polishing to measure diffraction X-rays from (10-13) planes of the wurtzite structure while changing the X-ray penetration depth from 0.3 m to 5 and thereby to obtain a plane spacing of the (10-13) planes (the specific parallel crystal lattice planes in this measurement) and a half value width of a diffraction intensity peak on a diffraction profile as well as a half value width of a diffraction intensity peak on a rocking curve. A parallel optical system and an X-ray wavelength of CuK.sub.1 were used for the X-ray diffraction measurement. The X-ray penetration depth was controlled by changing at least one of X-ray incident angle to the crystal surface, inclination angle of the crystal surface and rotary angle of within the crystal surface. Surface roughness Ry and surface roughness Ra of this n-type GaN crystal were measured with an AFM (Atomic Force Microscope: DIMENSION N3100 manufactured by VEECO Corp). The result is represented in a table 1.

(58) Referring to FIG. 6, an n-type GaN layer 621 (dopant: Si) of 1 m in thickness forming n-type semiconductor layer 620, an n-type Al.sub.0.1Ga.sub.0.9N layer 622 (dopant: Si) of 150 nm in thickness also forming n-type semiconductor layer 620, light emitting layer 640, a p-type Al.sub.0.2Ga.sub.0.8N layer 631 (dopant: Mg) of 20 nm in thickness forming p-type semiconductor layer 630 and a p-type GaN layer 632 (dopant: Mg) of 150 nm in thickness also forming p-type semiconductor layer 630 were successively formed by a MOCVD method on one of the main surface sides of substrate 610 of the n-type GaN crystal, thereby obtaining epitaxially-grown-layers for a light emitting element. Light emitting layer 640 had a multiple quantum-well structure in which four barrier layers formed of GaN layers each having a thickness of 10 nm and three well layers formed of Ga.sub.0.85In.sub.0.15N layers each having a thickness of 3 nm were layered alternately.

(59) A layered structure formed of a Ti layer of 200 nm in thickness, an Al layer of 1000 nm in thickness, a Ti layer of 200 nm in thickness and an Au layer of 2000 nm in thickness is formed as first electrode 661 on the other main surface side of substrate 610 of the n-type GaN crystal, and was heated in a nitrogen atmosphere to form an n-side electrode of 100 m in diameter. Also, a layered structure formed of an Ni layer of 4 nm in thickness and an Ai layer of 4 nm in thickness was formed as second electrode 662 on p-type GaN layer 632, and was heated in an inert gas atmosphere to form a p-side electrode. A chip measuring 400 m per side was prepared from the above layered structure, and then the above p-side electrode was bonded to conductor 682 with a solder layer 670 made of AuSn. Further, the n-side electrode and a conductor 681 were bonded together with a wire 690 so that a semiconductor device 600 having a structure as the light emitting device was obtained. The semiconductor device thus obtained was arranged in an integrating sphere. Then, a current of 20 mA is supplied to the semiconductor device to emit light, and the output of light gathered by the integrating sphere was measured. However, light emission from the semiconductor device of this comparative example was not confirmed. The result is represented in the table 1.

Examples 1-7

(60) Semiconductor devices were produced under the same conditions as those of the comparative example 1 except for that CMP was performed under the conditions described in the table 1 after the mechanical polishing and before the X-ray diffraction. Light outputs of the produced semiconductor devices were measured similarly to the comparative example 1. The result is represented in the table 1.

(61) TABLE-US-00001 TABLE 1 COMPARATIVE EXAMPLE 1 EXAMPLE 1 EXAMPLE 2 EXAMPLE 3 CMP pH OF SLURRY NO CMP 9.5 2.4 3.5 OXIDATION-REDUCTION 980 1420 1200 POTENTIAL OF SLURRY (mV) OXIDIZER Na-DCIA TCIA TCIA HARD GRAIN Al.sub.2O.sub.3 GRAIN DIAMETER (m) 0.5 SOFT GRAIN SiO.sub.2 SiO.sub.2 MIXTURE VOLUME RATIO ((HARD GRAINS):(SOFT GRAINS)) POLISHING RATE (m/hr) 0.4 0.5 1.1 CHARACTERTICS |d.sub.1 d.sub.2|/d.sub.2 2.3 10.sup.3 0.3 10.sup.3 0.3 10.sup.3 1.0 10.sup.3 |v.sub.1 v.sub.2| (arcsec) 290 60 50 90 |w.sub.1 w.sub.2| (arcsec) 500 130 120 220 SURFACE ROUGHNESS >100 1.8 1.0 4.1 Ry (nm) SURFACE ROUGHNESS >10 0.15 0.09 0.42 Ra (nm) LIGHT OUTPUT (mW) 15.6 16.4 12.3 EXAMPLE 4 EXAMPLE 5 EXAMPLE 6 EXAMPLE 7 CMP pH OF SLURRY 3.5 3.5 3.5 3.0 OXIDATION-REDUCTION 1200 1200 1200 1200 POTENTIAL OF SLURRY (mV) OXIDIZER TCIA TCIA TCIA TCIA HARD GRAIN Al.sub.2O.sub.3 Al.sub.2O.sub.3 Al.sub.2O.sub.3 Cr.sub.2O.sub.3 GRAIN DIAMETER (m) 1.0 2.0 0.5 0.8 SOFT GRAIN SiO.sub.2 SiO.sub.2 MIXTURE VOLUME 10:90 10:90 RATIO ((HARD GRAINS):(SOFT GRAINS)) POLISHING RATE (m/hr) 1.6 1.9 0.8 1.5 CHARACTERTICS |d.sub.1 d.sub.2|/d.sub.2 1.7 10.sup.3 2.1 10.sup.3 0.6 10.sup.3 1.4 10.sup.3 |v.sub.1 v.sub.2| (arcsec) 130 150 80 110 |w.sub.1 w.sub.2| (arcsec) 340 400 190 300 SURFACE ROUGHNESS 5.3 8.9 2.9 4.8 Ry (nm) SURFACE ROUGHNESS 0.51 0.85 0.26 0.45 Ra (nm) LIGHT OUTPUT (mW) 9.8 8.2 13.9 10.7 (NOTE) NA-DCIA: SODIUM DICHLOROISOCYANURATE, TCIA: TRICHLOROISOCYANURIC ACID

Comparative Example 2

(62) An n-type AlN crystal of 400 m in thickness that was grown by the sublimation method and was doped with Si was used as the nitride crystal, and was mechanically polished similarly to the comparative example 1.

(63) Then, measuring processing was effected on the n-type AlN crystal subjected to the mechanical polishing to measure diffraction X-rays from (11-22) planes of the wurtzite structure while changing the X-ray penetration depth from 0.3 m to 5 m, and thereby to obtain a place spacing of the (11-22) planes (specific parallel crystal lattice planes in this measurement) and a half value width of a diffraction intensity peak on a diffraction profile as well as a half value width of the diffraction intensity peak on a rocking curve. A parallel optical system and an X-ray wavelength of CuK.sub.1 were used for the X-ray diffraction measurement. The X-ray penetration depth was controlled by changing at least one of X-ray incident angle to the crystal surface, inclination angle of the crystal surface and rotary angle of within the crystal surface. Surface roughness Ry and surface roughness Ra of this n-type AlN crystal were measured with the AFM. The result is represented in a table 2.

(64) A semiconductor device using the above AlN crystal as a substrate was produced similarly to the comparative example 1. A light output of the semiconductor device thus produced was measured similarly to the comparative example 1. Light emission was not confirmed. The result is represented in the table 2.

Examples 8-10

(65) Semiconductor devices were produced under the same conditions as those of the comparative example 2 except for that CMP was performed under the conditions described in the table 2 after the mechanical polishing and before the X-ray diffraction. The result is represented in the table 2.

(66) TABLE-US-00002 TABLE 2 COMPARATIVE EXAMPLE 2 EXAMPLE 8 EXAMPLE 9 EXAMPLE 10 CMP pH OF SLURRY NO CMP 9.5 2.4 3.5 OXIDATION- 980 1420 1200 REDUCTION POTENTIAL OF SLURRY (mV) OXIDIZER Na-DCIA TCIA TCIA HARD GRAIN Al.sub.2O.sub.3 GRAIN DIAMETER 0.5 (m) SOFT GRAIN SiO.sub.2 SiO.sub.2 MIXTURE VOLUME RATIO ((HARD GRAINS):(SOFT GRAINS)) POLISHING RATE 0.6 0.8 1.4 (m/hr) CHARACTER- | d.sub.1 d.sub.2 |/d.sub.2 2.4 10.sup.3 0.5 10.sup.3 0.4 10.sup.3 1.4 10.sup.3 ISTICS | v.sub.1 v.sub.2 | (arcsec) 310 80 70 110 | w.sub.1 w.sub.2 | (arcsec) 510 140 130 220 SURFACE >100 1.0 1.4 4.5 ROUGHNESS Ry (nm) SURFACE >10 0.09 0.12 0.41 ROUGHNESS Ra (nm) LIGHT OUTPUT 13.9 14.8 10.9 (mW) (NOTE) NA-DCIA: SODIUM DICHLOROISOCYANURATE TCIA: TRICHLOROISOCYANURIC ACID

(67) As is apparent from the foregoing tables 1 and 2, high light outputs were achieved by the LEDs that are the semiconductor devices each selectively employing, as the nitride crystal substrate, the nitride crystal satisfying the conditions that, in the X-ray diffraction measurement performed with variation of X-ray penetration depth from the crystal surface while X-ray diffraction conditions of the arbitrary specific parallel crystal lattice planes of the crystal are satisfied, the uniform distortion |d.sub.1d.sub.2|/d.sub.2 at the surface layer obtained from the plane spacing d.sub.1 of the specific parallel crystal lattice planes at the X-ray penetration depth of 0.3 m and the plane spacing d.sub.2 of the specific parallel crystal lattice planes at the X-ray penetration depth of 5 m is equal to or lower than 2.110.sup.3, the irregular distortion |v.sub.1v.sub.2| at the crystal surface layer obtained from the half value width v.sub.1 of the diffraction intensity peak at the X-ray penetration depth of 0.3 m and the half value width v.sub.2 of the diffraction intensity peak at the X-ray penetration depth of 5 m is equal to or lower than 150 arcsec, or the plane direction deviation |w.sub.1w.sub.2| of the specific parallel crystal lattice plane obtained from the half value width w.sub.1 of the diffraction intensity peak at the X-ray penetration depth of 0.3 m and the half value width w.sub.2 of the diffraction intensity peak at the X-ray penetration depth of 5 m is equal to or lower than 400 arcsec.

(68) Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the spirit and scope of the present invention being limited only by the terms of the appended claims.