SENSOR DEVICE

Abstract

A sensor device includes an A/D converter including an adder that computes a difference between an analog input signal and a predicted value, the adder includes a capacitive adder defined by a series circuit including a capacitive charge output device and a capacitor. A capacitive component in the charge output device defines a portion of the capacitance of the capacitive adder. A digital prediction filter generates the predicted value based on an output from a quantizer. The capacitive adder computes the difference between the analog input signal from the charge output device and the predicted value. The quantizer quantizes and encodes the difference. The A/D converter performs a modulation on the analog input signal which is converted into a digital signal.

Claims

1. A sensor device comprising: an A/D converter including: an adder that computes a difference between an analog input signal and a predicted value; a quantizer that quantizes the difference which is output from the adder, and that converts, for output, the analog input signal into a digital signal; and a digital prediction filter that generates the predicted value from the digital signal which is output from the quantizer, and that outputs the predicted value to the adder; wherein the adder includes a capacitive adder defined by a first series circuit including a capacitive charge output device and a first capacitor; and a connecting point between the capacitive charge output device and the first capacitor is connected to an input of the quantizer.

2. The sensor device according to claim 1, wherein the first capacitor includes a plurality of capacitors connected to each other in parallel; and the digital prediction filter selects voltages applied to the plurality of capacitors, and uses the plurality of capacitors to perform D/A conversion on a voltage value applied to the connecting point, into an analog voltage value corresponding to the predicted value.

3. The sensor device according to claim 2, wherein the voltages applied to the plurality of capacitors are selected such that switching of switches connected to the plurality of capacitors is controlled by providing control signals to the switches, the control signals being signals in which a timing at which a voltage at the connecting point is decreased is provided with a delay from a timing at which the voltage at the connecting point is increased.

4. The sensor device according to claim 1, wherein the capacitive charge output device is connected to the connecting point through a resistor.

5. The sensor device according to claim 1, wherein the capacitive adder includes a loop filter defined by a passive element.

6. The sensor device according to claim 5, wherein the loop filter is a lag-lead filter.

7. The sensor device according to claim 6, wherein the lag-lead filter includes: a first resistor that is connected between the capacitive charge output device and the connecting point; a second resistor that is connected between the connecting point and the first capacitor; the first capacitor that is connected between the second resistor and the digital prediction filter; and a second series circuit that includes a third resistor and a second capacitor and is connected between an input terminal of the quantizer and a reference voltage.

8. The sensor device according to claim 6, wherein the lag-lead filter includes: a first resistor that is connected between the connecting point and the quantizer; the first capacitor that is connected between the connecting point and the digital prediction filter; and a second series circuit that includes the first resistor and the first capacitor and is connected between an input terminal of the quantizer and a reference voltage.

9. The sensor device according to claim 7, wherein the quantizer includes a comparator; and the sensor device includes: the second series circuit that is connected between a first input terminal of two input terminals of the comparator and the reference voltage; and a third series circuit that includes a fourth resistor and third capacitor, the third series circuit being connected between a second input terminal of the two input terminals and a reference voltage, the third series circuit having a same impedance as that of the second series circuit.

10. The sensor device according to claim 9, further comprising switches that connect the two input terminals to the reference voltages.

11. The sensor device according to claim 8, wherein the quantizer includes a comparator; and the sensor device includes: the second series circuit that is connected between a first input terminal of two input terminals of the comparator and the reference voltage; and a third series circuit including a second resistor and a second capacitor, the third series circuit being connected between a second input terminal of the two input terminals and a reference voltage, the third series circuit having an impedance having a same impedance as that of the second series circuit.

12. The sensor device according to claim 11, further comprising switches that connect the two input terminals to the reference voltages.

13. The sensor device according to claim 1, further comprising a switch that provides a short circuit between both terminals of the capacitive charge output device.

14. The sensor device according to claim 1, wherein the capacitive charge output device includes a pyroelectric infrared sensor which produces a charge due to a pyroelectric effect caused by a change in temperature of the sensor device.

15. The sensor device according to claim 1, wherein the capacitive charge output device includes a piezoelectric-ceramics pressure/vibration/impact sensor which produces a charge proportional to a stress when the stress is applied to the sensor device.

16. The sensor device according to claim 1, further comprising: a second series circuit including a resistor and a second capacitor; wherein the second series circuit is connected between the connecting point and a reference voltage.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0029] FIG. 1A is a block circuit diagram illustrating the configuration of a modulator; FIG. 1B is a block circuit diagram illustrating the configuration of a modulator; and FIG. 1C is a block circuit diagram illustrating the configuration of a hybrid modulator using both of a modulator and a modulator.

[0030] FIG. 2 is a circuit diagram illustrating a schematic configuration of a sensor device according to a first preferred embodiment of the present invention.

[0031] FIG. 3 is a circuit diagram illustrating a schematic configuration of a sensor device according to a second preferred embodiment of the present invention.

[0032] FIG. 4A is a circuit diagram illustrating a schematic configuration of a sensor device according to a third preferred embodiment of the present invention; and FIG. 4B is a circuit diagram illustrating a schematic configuration of a sensor device according to a modified example of the third preferred embodiment of the present invention.

[0033] FIG. 5A is a circuit diagram illustrating a schematic configuration of a sensor device according to a fourth preferred embodiment of the present invention; and FIG. 5B is a circuit diagram illustrating a schematic configuration of a sensor device according to a first modified example of the fourth preferred embodiment of the present invention.

[0034] FIG. 6 is a circuit diagram illustrating a schematic configuration of a sensor device according to a second modified example of the fourth preferred embodiment of the present invention.

[0035] FIG. 7 is a circuit diagram illustrating a schematic configuration of a sensor device according to a fifth preferred embodiment of the present invention.

[0036] FIG. 8 is a circuit diagram illustrating a schematic configuration of a sensor device according to a sixth preferred embodiment of the present invention.

[0037] FIG. 9 is a circuit diagram illustrating a schematic configuration of a sensor device according to a seventh preferred embodiment of the present invention.

[0038] FIG. 10A is a circuit diagram illustrating a schematic configuration of a sensor device according to an eighth preferred embodiment of the present invention; FIG. 10B is a circuit diagram illustrating the configuration of a pattern-dependent delay device included in the sensor device illustrated in FIG. 10A; and FIG. 10C is a circuit diagram illustrating the configuration of a delay circuit included in the pattern-dependent delay device illustrated in FIG. 10B.

[0039] FIG. 11A is a timing chart of pulse signals, which are provided to switches, and a voltage, which is input to a quantizer, in each of the sensor devices according to the first to seventh preferred embodiments of the present invention; and FIG. 11B is a timing chart of pulse signals, which are provided to switches, and a voltage, which is input to a quantizer, in the sensor device according to the eighth preferred embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0040] Preferred embodiments of the present invention will be described with reference to the drawings.

[0041] FIG. 2 is a circuit diagram illustrating a schematic configuration of a sensor device 21A according to a first preferred embodiment of the present invention.

[0042] The sensor device 21A includes a capacitive charge output device 22 defining a sensor, and converts, into the digital signal dout, an analog input signal resulting from a charge produced by the charge output device 22. Preferred examples of the capacitive charge output device 22 include a pyroelectric infrared sensor which produces a charge due to a pyroelectric effect caused by a change in the temperature of the device, and a piezoelectric-ceramics pressure/vibration/impact sensor which produces a charge proportional to a stress when the stress is applied to a piezoelectric device.

[0043] A series circuit including the charge output device 22 and a capacitor 23 defines a capacitive adder 24. A connecting point Q between the charge output device 22 and the capacitor 23 is connected to the input of a quantizer 27. The capacitor 23 includes a plurality of capacitors 23a, 23b, . . . , 23n which are connected in parallel. The capacitive adder 24 computes the difference between the analog input signal that is produced by the charge output device 22 and the predicted value that is output from a digital prediction filter 25. That is, in accordance with the charges accumulated in the capacitances of the charge output device 22 and the capacitor 23, the capacitive adder 24 adds the analog-input-signal voltage value, which is produced by the charge output device 22, to the analog voltage value according to the inverted predicted value which is output from the digital prediction filter 25. Thus, the capacitive adder 24 computes the difference between the analog input signal and the predicted value.

[0044] The analog voltage value according to the predicted value is obtained such that the digital prediction filter 25 selects voltages applied to the capacitors 23a, 23b, . . . , 23n and, by using the capacitor 23, the voltage value applied to the connecting point Q is D/A converted into an analog voltage value according to the digital predicted value. Switches 26a, 26b, . . . , 26n are provided between the capacitors 23a, 23b, . . . 23n, respectively, and the digital prediction filter 25. By switching of the switches 26a, 26b, . . . , 26n, the Vrefp voltage or the Vrefn voltage is applied to the terminals of the capacitors 23a, 23b, . . . , 23n, respectively, that are opposite to the connecting-point-Q-side terminals. The Vrefp voltage is preferably set, for example, to about 1 [V], and the Vrefn voltage is preferably set, for example, to about 0 [V]. In addition, the capacitance values of the capacitors 23a, 23b, . . . , 23n are preferably set to about 2.sup.0C [F], about 2.sup.1C [F], about 2.sup.2C [F], . . . , about 2.sup.nC [F], respectively. Therefore, the digital prediction filter 25 controls the switching states of the switches 26a, 26b, . . . , 26n in accordance with the digital predicted value computed by the digital prediction filter 25. Thus, the voltages applied to the capacitors 23a, 23b, . . . , 23n are selected so that the combined voltage value of the capacitors 23a, 23b, . . . , 23n is set to the analog voltage value according to the predicted value.

[0045] The quantizer 27 quantizes and encodes the difference that is output from the capacitive adder 24 every time a sampling clock clk is received, and coverts, for output, the analog input signal to the digital signal dout. The digital prediction filter 25 generates the digital predicted value from the digital signal dout that is output from the quantizer 27, and outputs the digital predicted value to the capacitive adder 24.

[0046] In the sensor device 21A according to the first preferred embodiment as described above, the digital prediction filter 25 generates the predicted value from the output from the quantizer 27, and the capacitive adder 24 computes the difference between the analog input signal produced from the charge output device 22 and the predicted value. The quantizer 27 quantizes and encodes the difference. Therefore, the analog input signal is subjected to a modulation by an A/D converter including the capacitive adder 24, the quantizer 27, and the digital prediction filter 25, and is converted into the digital signal dout.

[0047] In the sensor device 21A according to the present preferred embodiment, the adder which computes the difference between the analog input signal and the predicted value includes the capacitive adder 24 including the series circuit of the capacitive charge output device 22, which is an input signal source, and the capacitor 23. The capacitive component included in the capacitive charge output device 22 itself is used as a portion of the capacitance included in the capacitive adder 24. Therefore, the capacitive charge output device 22 is provided as a portion of the adder which computes the difference between the analog input signal and the predicted value. The output from the capacitive charge output device 22 is used without amplification, and the capacitive adder 24 performs an addition operation. Therefore, it is not necessary to provide an impedance converting circuit which, in the related art, must be provided between the adder provided at the input of the A/D converter and the capacitive charge output device 22 which is an input signal source and which has a high impedance. In addition, it is not necessary to provide an amplifier. Therefore, the sensor device 21A including the A/D converter which performs the modulation has low power consumption and a reduced size.

[0048] In the sensor device 21A according to the present preferred embodiment, the predicted value that is output from the digital prediction filter 25 is converted from a digital value to an analog voltage value by the digital prediction filter 25 selecting, in accordance with the predicted value, the voltages applied to the capacitors 23a, 23b, . . . , 23n, which are included in the capacitive adder 24. Therefore, the capacitive adder 24 may add the analog-signal voltage value, which is output from the capacitive charge output device 22, to the predicted value, which is output from the digital prediction filter 25.

[0049] FIG. 3 is a circuit diagram illustrating a schematic configuration of a sensor device 21B according to a second preferred embodiment of the present invention. In FIG. 3, components identical to or corresponding to those in FIG. 2 are designated with the same reference characters, and will not be described.

[0050] The sensor device 21B according to the second preferred embodiment is different from the sensor device 21A according to the first preferred embodiment only in that the capacitive charge output device 22 is connected to the connecting point Q through a resistor R1.

[0051] In the sensor device 21B according to the second preferred embodiment, when the capacitive charge output device 22 unintentionally produces a large amount of charge, the resistor R1 prevents a large amount of current from flowing into the capacitive adder 24. Therefore, the capacitive adder 24 is protected.

[0052] FIG. 4A is a circuit diagram illustrating a schematic configuration of a sensor device 21C according to a third preferred embodiment of the present invention. In FIG. 4A, components identical to or corresponding to those in FIG. 3 are designated with the same reference characters, and will not be described.

[0053] The sensor device 21C according to the third preferred embodiment is different from the sensor device 21B according to the second preferred embodiment only in that resistors Ra, Rb, . . . , Rn are connected in series to the capacitors 23a, 23b, . . . , 23n, respectively, and that the capacitive adder 24 includes a loop filter preferably defined by passive elements. The resistor R1, the capacitors 23a, 23b, . . . , 23n, and the resistors Ra, Rb, . . . , Rn define a portion of a lag-lead filter which functions as a loop filter. In addition, the resistor R1 defines a portion of a lag-lead filter, and, at the same time, prevents a large amount of current from flowing, similar to the sensor built-in A/D converter 21B according to the second preferred embodiment. Thus, the capacitive adder 24 is protected.

[0054] In the sensor device 21C according to the third preferred embodiment, the capacitive adder 24 including the capacitive charge output device 22 and the capacitor 23 computes the difference between the analog input signal and the predicted value. The difference is integrated by the loop filter, and, similar to a modulator, noise shaping is performed. The quantizer 27 quantizes the integrated difference. Therefore, a hybrid modulation using both of a modulation and a modulation is performed, achieving an improvement in the signal-to-quantization noise ratio (SQNR). The loop filter is preferably defined by passive elements of resistance devices and capacitor devices. Further, the loop filter is integrated with the capacitive adder 24. Therefore, it is not necessary to provide an amplifier which is necessary, in the related art, for the integrator 6 to replicate an input signal (see FIGS. 1A to 1C). Thus, the sensor device 21C including the A/D converter performing a hybrid modulation has low power consumption and a reduced size.

[0055] FIG. 4B is a circuit diagram illustrating a schematic configuration of a sensor device 21C according to a modified example of the third preferred embodiment. In FIG. 4B, components identical to or corresponding to those in FIG. 4A are designated with the same reference characters, and will not be described.

[0056] The sensor device 21C according to the modified example of the third preferred embodiment is different from the sensor device 21C according to the third preferred embodiment only in that the capacitor 23 is connected to the resistor Ra in series. The resistor R1, the capacitors 23a, 23b, . . . , 23n, and the resistor Ra define a portion of a lag-lead filter which functions as a loop filter.

[0057] Also in the sensor device 21C according to the modified example of the third preferred embodiment, the capacitive adder 24 including the capacitive charge output device 22 and the capacitor 23 computes the difference between the analog input signal and the predicted value. The loop filter integrates the difference. Thus, a hybrid modulation using both of a modulation and a modulation is performed. Accordingly, the sensor device 21C provides a similar operational effect to the sensor device 21C according to the third preferred embodiment.

[0058] FIG. 5A is a circuit diagram illustrating a schematic configuration of a sensor device 21D according to a fourth preferred embodiment of the present invention. In FIG. 5A, components identical to or corresponding to those in FIG. 4A are designated with the same reference characters, and will not be described.

[0059] The sensor device 21D according to the fourth preferred embodiment is different from the sensor device 21C according to the third preferred embodiment only in that a series circuit including a resistor R2 and a capacitor 28 is connected to the connecting point Q, and that the series circuit is grounded. The resistor R1, the capacitors 23a, 23b, . . . , 23n, the resistors Ra, Rb, . . . , Rn, and the resistor R2 and the capacitor 28 included in the above-described series circuit define a lag-lead filter.

[0060] In the sensor device 21D according to the fourth preferred embodiment, the lag-lead filter defines and functions as a loop filter. Therefore, the sensor device 21D according to the fourth preferred embodiment is also able to perform a hybrid modulation and improve the signal-to-quantization noise ratio.

[0061] FIG. 5B is a circuit diagram illustrating a schematic configuration of a sensor device 21D according to a modified example of the fourth preferred embodiment. In FIG. 5B, components identical to or corresponding to those in FIG. 5A are designated with the same reference characters, and will not be described.

[0062] The sensor device 21D according to the modified example of the fourth preferred embodiment is different from the sensor device 21D according to the fourth preferred embodiment only in that the resistor Ra is connected to the capacitor 23 in series. The resistor R1, the capacitor 23, the resistor Ra, and the series circuit of the resistor R2 and the capacitor 28 define a lag-lead filter.

[0063] Also in the sensor device 21D according to the modified example of the fourth preferred embodiment, the lag-lead filter defines and functions as a loop filter. Thus, the sensor device 21D according to the modified example provides a similar operational effect to the sensor device 21D according to the fourth preferred embodiment.

[0064] FIG. 6 is a circuit diagram illustrating a schematic configuration of a sensor device 21D according to a second modified example of the fourth preferred embodiment. In FIG. 6, components identical to or corresponding to those in FIG. 5B are designated with the same reference characters, and will not be described.

[0065] The sensor device 21D according to the second modified example of the fourth preferred embodiment is different from the sensor device 21D according to the modified example only in that the resistor R1 connected between the capacitive charge output device 22 and the connecting point Q and the resistor Ra connected between the connecting point Q and the capacitor 23, in the sensor device 21D according to the modified example in FIG. 5B are integrated into a single resistor R3 connected between the connecting point Q and the quantizer 27. The capacitor 23, the resistor R3, and the series circuit of the capacitor 28 and the resistor R2, which is connected between the input terminal of the quantizer 27 and the ground voltage, define a lag-lead filter. Also in the sensor device 21D according to the second modified example of the fourth preferred embodiment, the lag-lead filter defines and functions as a loop filter. Therefore, the sensor device 21D provides a similar operational effect to the sensor device 21D according to the fourth preferred embodiment. Further, the sensor device 21D according to the second modified example of the fourth preferred embodiment achieves a reduction in the number of resistors as compared to the sensor device 21D according to the modified example of the fourth preferred embodiment, resulting in a reduction in the area in which components are mounted.

[0066] FIG. 7 is a circuit diagram illustrating a schematic configuration of a sensor device 21E according to a fifth preferred embodiment of the present invention. In FIG. 7, components identical to or corresponding to those in FIG. 6 are designated with the same reference characters, and will not be described.

[0067] The sensor device 21E according to the fifth preferred embodiment is different from the sensor device 21D according to the second modified example of the fourth preferred embodiment in FIG. 6 only in the following points: a quantizer 27 includes a comparator; the series circuit of the resistor R2 and the capacitor 28 is connected between one of a pair of input terminals of the comparator and the ground voltage that is a reference voltage; and a series circuit of a resistor R4 and a capacitor 30 is connected between the other one of the pair of input terminals and the ground voltage. The series circuit of the resistor R2 and the capacitor 28 and the series circuit of the resistor R4 and the capacitor 30 preferably have the same or substantially the same impedance.

[0068] The sensor device 21E according to the fifth preferred embodiment also provides a similar operational effect to the sensor device 21D according to the second modified example of the fourth preferred embodiment. Further, in the sensor device 21E according to the fifth preferred embodiment, the series circuit of the resistor R2 and the capacitor 28 and the series circuit of the resistor R4 and the capacitor 30, which preferably have the same or substantially the same impedance, are connected in a balanced manner between the ground voltage and the respective two input terminals of the comparator included in the quantizer 27. Therefore, when both of the two input terminals of the quantizer 27 receive the same or substantially the same noise, the noise is able to be removed through a differential operation performed on the pair of input signals by the comparator included in the quantizer 27.

[0069] FIG. 8 is a circuit diagram illustrating a schematic configuration of a sensor device 21F according to a sixth preferred embodiment of the present invention. In FIG. 8, components identical to or corresponding to those in FIG. 7 are designated with the same reference characters, and will not be described.

[0070] The sensor device 21F according to the sixth preferred embodiment is different from the sensor device 21E according to the fifth preferred embodiment in FIG. 7 only in that switches 31 and 32 through which the respective two input terminals of the comparator included in the quantizer 27 are connected to the ground voltage are provided in parallel to the series circuit of the resistor R2 and the capacitor 28 and the series circuit of the resistor R4 and the capacitor 30, respectively.

[0071] The sensor device 21F according to the sixth preferred embodiment also provides a similar operational effect to the sensor device 21E according to the fifth preferred embodiment. Further, in the sensor device 21F according to the sixth preferred embodiment, for example, when a charge exceeding the range in which a circuit included in the A/D converter operates normally flows into the capacitive adder 24, or when use of the sensor device 21F begins, the switches 31 and 32 are conducted so that the respective two input terminals of the quantizer 27 are connected to the ground voltage. Thus, a charge building up in the capacitive adder 24 is able to be discharged through the switches 31 and 32, thus enabling the circuit to be reset.

[0072] In the present preferred embodiment, the switches 31 and 32 are provided in parallel to the series circuit of the resistor R2 and the capacitor 28 and the series circuit of the resistor R4 and the capacitor 30, respectively. Alternatively, the switches 31 and 32 may be provided in parallel to the capacitor 28 and the capacitor 30, respectively. This configuration provides a similar operational effect to the present preferred embodiment.

[0073] FIG. 9 is a circuit diagram illustrating a schematic configuration of a sensor device 21G according to a seventh preferred embodiment of the present invention. In FIG. 9, components identical to or corresponding to those in FIG. 2 are designated with the same reference characters, and will not be described.

[0074] The sensor device 21G according to the seventh preferred embodiment is different from the sensor device 21A according to the first preferred embodiment only in that a switch 29 that provides a short circuit between both the terminals of the capacitive charge output device 22 is provided.

[0075] In the sensor device 21G according to the seventh preferred embodiment, when a large amount of charge builds up in the capacitive charge output device 22, a short circuit between both the terminals of the capacitive charge output device 22 is made using the switch 29. Thus, the capacitive charge output device 22 may be reset at any time. Therefore, the stability of the output of the sensor device 21E is improved. In addition, also in the sensor devices 21B, 21C, 21C, 21D, 21D, 21D, 21E, and 21F according to the second, third, fourth, fifth, and sixth preferred embodiments and their modified examples described above, the switch 29 may preferably be provided between both of the terminals of the capacitive charge output device 22 in the same or similar manner. Thus, a similar operational effect to the sensor device 21G according to the seventh preferred embodiment is provided.

[0076] FIG. 10A is a circuit diagram illustrating a schematic configuration of a sensor device 21H according to an eighth preferred embodiment of the present invention. In FIG. 10A, components identical to or corresponding to those in FIG. 9 are designated with the same reference characters, and will not be described.

[0077] The sensor device 21H according to the eighth preferred embodiment is different from the sensor device 21G according to the seventh preferred embodiment in FIG. 9 only in that a pattern-dependent delay device 33 is provided between the prediction filter 25 and the switches 26a, 26b, . . . , 26n. In the sensor devices 21A to 21G according to the first to seventh preferred embodiments, the prediction filter 25 performs conversion into an analog voltage value in accordance with the predicted value. In the conversion, pulse signals Da, Db, . . . , Dn as illustrated in FIG. 11A are provided as control signals to the switches 26a, 26b, . . . , 26n connected to the capacitors 23a, 23b, . . . , 23n, and switching of the switches 26a, 26b, . . . , 26n is thus controlled. In the case of the high level in the pulse signals Da, Db, . . . , Dn, the voltage at the connecting point Q between the capacitive charge output device 22 and the capacitor 23 increases. In the case of the low level, the voltage at the connecting point Q decreases. The pattern-dependent delay device 33 converts the pulse signals Da, Db, . . . , Dn so that, as illustrated in FIG. 11B, a falling timing Td includes a delay from a rising timing Tu, and provides the resulting signals to the switches 26a, 26b, . . . , 26n. The prediction filter 25 selects the voltages applied to the capacitors 23a, 23b, . . . , 23n in the sensor device 21H according to the eighth preferred embodiment such that the pulse signals Da, Db, . . . , Dn obtained through such conversion are provided to the switches 26a, 26b, . . . , 26n, respectively.

[0078] As illustrated in FIG. 10A, a parasitic diode 37 is preferably attached between both of the terminals of the switch 29. The anode of the parasitic diode 37 is connected to the ground, and the cathode is connected to the connecting point Q. The parasitic diode 37 is parasitic in the forward direction towards the connecting point Q. For example, in the case in which the sensor device 21H is defined by, as an IC (integrated circuit), the circuit portion excluding the capacitive charge output device 22, and where the terminal of the IC which is connected to the connecting point Q is connected to an ESD (Electro Static Discharge) protection device which is not illustrated, a similar parasitic diode 37 may also be attached to the connecting point Q.

[0079] In this case, assume that switching of the switches 26a, 26b, . . . , 26n connected to the capacitors 23a, 23b, . . . , 23n is controlled by providing the switches 26a, 26b, . . . , 26n with the pulse signals Da, Db, . . . , Dn in which the rising timing and the falling timing occur at the same time, as illustrated in FIG. 11A. Depending on the generation timings of the pulse signals Da, Db, . . . , Dn, for example, the falling timing Td of the pulse signal Da may be slightly earlier than the rising timing Tu of the pulse signal Db. A negative glitch N as illustrated in FIG. 11A may occur in the voltage Vx at the connecting point Q. When the negative glitch N occurs and the voltage Vx becomes less than 0 [V] by a large amount, a forward direction voltage is applied to the parasitic diode 37, and the parasitic diode 37 conducts. Thus, the charge accumulated in the capacitive adder 24 is discharged, and an error occurs in the addition operation performed by the capacitive adder 24.

[0080] However, in the configuration of the sensor device 21H according to the eighth preferred embodiment, switching of the switches 26a, 26b, . . . , 26n connected to the capacitors 23a, 23b, . . . , 23n is controlled by providing the switches 26a, 26b, . . . , 26n with the pulse signals Da, Db, . . . , Dn, as control signals, in which the falling timing Td includes a delay from the rising timing Tu, as illustrated in FIG. 11B. Therefore, the falling timing Td of the pulse signal Da occurs after the rising timing Tu of the pulse signal Db, and a glitch at the input of the quantizer 27 is always produced on the positive side, not on the negative side, such as the voltage Vx at the connecting point Q illustrated in FIG. 11B. Therefore, a forward direction voltage is not applied to the parasitic diode 37. Thus, the case in which the parasitic diode 37 conducts and in which the charge accumulated in the capacitive adder 24 is discharged will not occur. As a result, no errors will occur in the addition operation performed by the capacitive adder 24.

[0081] For example, as illustrated in FIG. 10B, the pattern-dependent delay device 33 includes a delay circuit 35 that delays a signal that is to be received by one of the inputs of an OR circuit 34. For example, as illustrated in FIG. 10C, the delay circuit 35 includes an even number of inverters 36 that are connected to each other in series. The pattern-dependent delay device 33 is thus defined. Accordingly, when each of the pulse signals Da, Db, . . . , Dn drops from the high level to the low level, the delay circuit 35 delays the high-level time of the signal received by the input of the OR circuit 34. Thus, the time until the output of the OR circuit 34 drops to the low level is delayed. Therefore, this delay enables generation of the pulse signals Da, Db, . . . , Dn in which the falling timing Td includes a delay from the rising timing Tu, as illustrated in FIG. 11B. In contrast, when each of the pulse signals Da, Db, . . . , Dn rises from the low level to the high level, the delay circuit 35 delays the low-level time of the signal received by the input of the OR circuit 34. However, the signal received by the other input of the OR circuit 34 is not delayed. Therefore, the rising timing of the signal at the output of the OR circuit 34 is not delayed, and the signal changes from the low level to the high level without a delay.

[0082] Also in the sensor devices 21A, 21B, 21C, 21C, 21D, 21D, 21D, 21E, and 21F according to the first, second, third, fourth, fifth, and sixth preferred embodiments and their modified examples described above, the pattern-dependent delay device 33 may preferably be provided between the prediction filter 25 and the switches 26a, 26b, . . . , 26n in a similar manner. Thus, a similar operational effect to the sensor device 21H according to the eighth preferred embodiment is provided.

[0083] The sensor devices 21A to 21H according to the preferred embodiments of the present invention and their modified examples described above are preferably used as a person detecting sensor when a pyroelectric infrared sensor is used as the capacitive charge output device 22, and are preferably used as a pressure/vibration/impact measurement sensor used in various applications in the industrial field when a pressure/vibration/impact sensor is used as the capacitive charge output device 22.

[0084] While preferred embodiments of the present invention have been described above, it is to be understood that variations and modifications will be apparent to those skilled in the art without departing from the scope and spirit of the present invention. The scope of the present invention, therefore, is to be determined solely by the following claims.