METHOD OF VERNIER DIGITAL-TO-ANALOG CONVERSION

Abstract

A digital-to-analog conversion, including: converting signal Y using word X=M+a.sup.−aN having length Ψ=α+β digits, where M is high order digits of a long control word X, a.sup.−aN is low order digits of β long control word X, wherein α≈β; subjecting analog signal Z to three conversions, wherein, in the first conversion, signal Z.sub.1 is proportional to Mα long high order digits of X, and to reference signal Y.sub.1, where Z.sub.1=Y.sub.1×M, in the second and third conversions, signals Z.sub.2 and Z.sub.3 are proportional to Nβ long low order digits of X and to signals Y.sub.1 and Y.sub.2, respectively, where Z.sub.2=Y.sub.1×N, and Z.sub.3=Y.sub.2×N, wherein, before the conversions, a.sup.−aN low order digits of X are multiplied by a.sup.a; and adding Z.sub.1, Z.sub.2, Z.sub.3 to generate output signal Z.sub.0, wherein Y.sub.1 and Y.sub.2 relate by Y.sub.2=Y.sub.1(1±a.sup.−a), wherein a is the base of the numbering system, α is the number of digits, by which a.sup.−aN is shifted.

Claims

1. A method of Vernier digital-to-analog conversion, wherein the method comprises: converting reference signal Y using control word X=M+a.sup.−aN having a length of ψ=α+β digits, wherein M is high order digits of a long control word X, a.sup.−aN is low order digits of β long control word X, wherein α≈β, performing two parallel conversions on an analog signal Z, wherein, in a first conversion, a first output analog signal Z.sub.1 is proportional to the M high order digits of α long control word X, and to a reference signal Y.sub.1, where Z.sub.1=Y.sub.1×M, in a second conversion, a second output analog signal Z.sub.2 is proportional to N low order digits of β long control word X and to a reference signal Y.sub.1, where Z.sub.2=Y.sub.1×N, wherein, prior to the two parallel conversions, digital multiplication of the a.sup.−aN low order digits of the control word X by a.sup.a times is performed; performing a third parallel conversion on the analog signal Z, in which a third output analog signal Z.sub.3 is proportional to N low order digits of β long control word X, and to a reference signal Y.sub.2, where Z.sub.3=Y.sub.2×N, wherein the reference signal Y.sub.1 and the reference signal Y.sub.2 are related through a dependency Y.sub.2=Y.sub.1 (1±a.sup.−a) where, wherein a is a base of a numbering system, and α is a number of digits by which control code a.sup.−aN is shifted; and adding the first output analog signal Z.sub.1, the second output analog signal Z.sub.2, and the third output analog signal Z.sub.3 to generate an analog output signal Z.sub.0.

2. The method of claim 1, wherein in the two parallel conversions of the first analog signal Z.sub.1 and the second output analog signal Z.sub.2 and the parallel conversion of the third output analog signal Z.sub.3, a conversion scale is selected to be the same.

3. The method of claim 1, wherein, when the reference signal Y.sub.2 is generated according to an expression Y.sub.2=Y.sub.1(1+a.sup.−α), the first output analog signal Z.sub.1, the second output analog signal Z.sub.2, and the third output analog signal Z.sub.3 are added to generate the analog output signal Z.sub.0 according to an expression: Z.sub.0=Z.sub.1+Z.sub.3−Z.sub.2.

4. The method of claim 1, wherein when the reference signal Y.sub.2 is generated according to an expression Y.sub.2=Y.sub.1(1−a.sup.−α), the first output analog Z.sub.1, the second output analog signal Z.sub.2, and the third output analog signal Z.sub.3 are added to generate the analog output signal Z.sub.0 according to an expression: Z.sub.0=Z.sub.1+Z.sub.2−Z.sub.3.

Description

DETAILED DESCRIPTION

[0067] Structural scheme of one of the possible embodiments of Vernier digital-to-analog converter (DAC) which implements the claimed method is shown in FIG. 3, which shows:

[0068] Reference signal Y.sub.1 source 6,

[0069] Digital multiplier 7,

[0070] First DAC_8,

[0071] Reference signal Y.sub.2 source 9,

[0072] Second DAC_10,

[0073] Third DAC_11,

[0074] Analog adder 12.

[0075] In the digital multiplier 7, β low order digits of control word a.sup.−αN are subjected to digital multiplication by a.sup.α times (shift by a digits to the left). Output bus of a high order digits of control word M is connected to the respective input control bus of DAC_8, and the other input of the latter being connected to the output of reference signal Y.sub.1 source 6. Output of the DAC_8 is connected to the respective input of analog adder 12, and the other inputs of the latter being connected to the output of DAC_10 and output of DAC_11, while β low order digits of control word N (control word a.sup.−αN, which has been digitally multiplied by a.sup.α times (shift by a digits to the left)) are provided to the input control bus of DAC_10 and DAC_11, the other input of DAC_10 being connected to the output of reference signal Y.sub.1 source 6, and the respective input of DAC_11 being connected to the output of reference signal Y.sub.2 source 9, wherein the dimensional scales (reference signals) Y.sub.1 and Y.sub.2 are related through the following dependency:

Y.sub.2=Y.sub.1(1±a.sup.−α).

[0076] Analog output signal Z.sub.0 is obtained at the output of analog adder 12.

[0077] As a numeric example, an embodiment of Vernier conversion of a decimal number into an abstract analog parameter Z is shown.

[0078] Since the numbering system is decimal, a two-digit digital word X.sub.(10) is partitioned into two one-digit ones, M and N, and reference signals Y will then be: Y.sub.1=1.0; Y.sub.2=1.1×Y.sub.1.

EXAMPLES

[0079] There are two illustrative variants: one for the case of M.sub.1>N and the other one for the case of M.sub.2<N. Let M.sub.1=7 and M.sub.2=3, and N have the values from 0 to 9. The steps of these calculations and conversions are summarized in Table 1 and Table 2 provided below.

TABLE-US-00001 TABLE 1 Y.sub.2 = 1.1 × Y.sub.1 Z.sub.1 = Z.sub.2 = Z.sub.3 = Z.sub.0 = M.sub.1 N Υ.sub.1 × M Y.sub.1 × N Y.sub.2 × N Z.sub.1 − Z.sub.2 + Z.sub.3 7 0 7 0 0.0 7.0 7 1 7 1 1.1 7.1 7 2 7 2 2.2 7.2 7 3 7 3 3.3 7.3 7 4 7 4 4.4 7.4 7 5 7 5 5.5 7.5 7 6 7 6 6.6 7.6 7 7 7 7 7.7 7.7 7 8 7 8 8.8 7.8 7 9 7 9 9.9 7.9

TABLE-US-00002 TABLE 2 Y.sub.2 = 1.1 × Y.sub.1 Z.sub.1 = Z.sub.2 = Z.sub.3 = Z.sub.0 = M.sub.2 N Y.sub.1 × M Y.sub.1 × N Y.sub.2 × N Z.sub.1 − Z.sub.2 + Z.sub.3 3 0 3 0 0.0 3.0 3 1 3 1 1.1 3.1 3 2 3 2 2.2 3.2 3 3 3 3 3.3 3.3 3 4 3 4 4.4 3.4 3 5 3 5 5.5 3.5 3 6 3 6 6.6 3.6 3 7 3 7 7.7 3.7 3 8 3 8 8.8 3.8 3 9 3 9 9.9 3.9

[0080] The only units of the Vernier DAC (FIG. 3), to which strict requirements for precision should apply, are output analog adder 12, reference signal Y.sub.1 source 8, and reference signal Y.sub.2 source 9, wherein their implementation does not involve any inextricable difficulties; moreover, they are common for (high) precision electronics.

[0081] So, e.g., in case of a twenty-digit binary input word (α=β=10) and Y.sub.1=10 V, the necessary relative accuracy of analog adder and source is Y.sub.1 δ.sub.α≤2.sup.−20≈10.sup.−6 (absolute accuracy is 9.5 μV), which is readily implementable using the current microelectronic hardware components.

[0082] In the case of Y.sub.2=0.9×Y.sub.1 and the numeric parameters being the same, the result will be as follows:

TABLE-US-00003 TABLE 3 Y.sub.2 = 0.9 × Y.sub.1 Z.sub.1 = Z.sub.2 = Z.sub.3 = Z.sub.0 = M N Y.sub.1 × M Y.sub.1 × N Y.sub.2 × N Z.sub.1 + Z.sub.2 − Z.sub.3 7 0 7 0 0.0 7.0 7 1 7 1 0.9 7.1 7 2 7 2 1.8 7.2 7 3 7 3 2.7 7.3 7 4 7 4 3.6 7.4 7 5 7 5 4.5 7.5 7 6 7 6 5.4 7.6 7 7 7 7 6.3 7.7 7 8 7 8 7.2 7.8 7 9 7 9 8.1 7.9

TABLE-US-00004 TABLE 4 Y.sub.2 = 0.9 × Y.sub.1 Z.sub.1 = Z.sub.2 = Z.sub.3 = Z.sub.0 = M N Y.sub.1 × M Y.sub.1 × N Y.sub.2 × N Z.sub.1 + Z.sub.2 − Z.sub.3 3 0 3 0 0.0 3.0 3 1 3 1 0.9 3.1 3 2 3 2 1.8 3.2 3 3 3 3 2.7 3.3 3 4 3 4 3.6 3.4 3 5 3 5 4.5 3.5 3 6 3 6 5.4 3.6 3 7 3 7 6.3 3.7 3 8 3 8 7.2 3.8 3 9 3 9 8.1 3.9

[0083] In the claimed conversion method, in the case of any ratio between numbers N and M, no loss of digits occurs while the accuracy of digital-to-analog conversion is increased by ≈a.sup.α-1 times, as the error is significantly reduced and, hence, accuracy of parallel digital-to-analog conversion is increased without stricter requirements for DAC components manufacturing technology.

[0084] Improved conversion accuracy is stipulated by the fact that, in the case of analog addition, other conditions being equal, requirements for the accuracy of adder unit are less strict than the requirements for the accuracy of analog attenuator in the case of analog division of signal Z.

[0085] Besides, accuracy of reference signals (dimensional scales) Y.sub.1, Y.sub.2 and their ratio needs to be provided at one point and under direct current (under constant values of current or voltage), which is significantly simpler than doing it throughout the range of output levels of Z and operational frequencies.

[0086] The following circumstance is repeatedly emphasized: for any method of digital-to-analog conversion (double and greater integration, sigma-delta, pipelined, sequential approximation, Vernier, etc.), requirements for the accuracy of analog components are only defined by the necessary accuracy of conversion.

[0087] Weighted contribution of individual analog elements of the digital-to-analog converter which implements the claimed method into the pool of acceptable errors of the device as a whole depends on its specific circuitry implementation. And, naturally, the known rule applies:

[0088] the stricter the requirements for conversion accuracy, the stricter (at least linearly) the requirements for analog components.

[0089] Requirements for accuracy and stability of reference voltage (current) sources and analog algebraic adders of input/output voltages (currents) do not depend on the chosen conversion method, and their contribution is small.

[0090] The main contribution into the pool of errors is provided by the DAC per se (which is explicitly or implicitly included in the structure of Vernier digital-to-analog conversion) via errors in voltage/current keys and R (C) arrays.

[0091] Use of identical resistors makes it possible to significantly improve the accuracy as compared to an ordinary weighted DAC, since it is comparatively easy to make a set of precision elements with identical parameters. R-2R type DACs enable shifting, but not lifting restrictions concerning the number of digits. By virtue of laser trimming of film resistors arranged on the same substrate of a hybrid microchip, 20-22 bit accuracy of DAC may be achieved.

[0092] For this reason, relaxation of requirements for DACs in the form of reducing the required number of digits Ψ=α+β of control word X while retaining the resulting accuracy of conversion is of such practical importance.

[0093] An example of configuration of the elements in the structural scheme implementing the claimed conversion method is shown.

[0094] DACs 8, 10, and 11 may be configured by the following microchips: double DAC AD5763, single DAC K594PA1, K1108PA1 or similar ones. Reference signal sources 6 and 9 may be configured by microchips LT6657 (precision voltage source) or LT3092 (precision current source).

[0095] To perform digital multiplication by a times of N low order digits of control word X (left shift by α digits), shift register microchips—universal registers KR15331R8 (SN74HC164) may be used.