Storage time control

Abstract

A controller for use in a power converter includes a first terminal to provide a turn on signal to initiate turning on of a power switch and a second terminal to provide a turn off signal to initiate turning off the power switch. A detection circuit is coupled to detect a turn off time delay. The turn off time delay is the duration of time between an initiating of a turn off of the power switch by the turn off signal and an actual turn off of the power switch. A control circuit is coupled to control the turn on signal to regulate the turn off delay time to a target time value. The control circuit controls the turn on signal by controlling an amount of charge delivered to turn on the power switch.

Claims

1. A controller for use in a power converter, the controller comprising: a first terminal to provide a turn on signal to initiate turning on of a power switch; a second terminal to provide a turn off signal to initiate turning off the power switch; a detection circuit coupled to detect a turn off time delay; and a control circuit coupled to control the turn on signal to regulate the turn off delay time to a target time value, wherein the control circuit controls the turn on signal by controlling an amount of charge delivered to turn on the power switch.

2. The controller of claim 1, wherein the control circuit is coupled to control the amount of charged delivered by controlling a voltage source or a current source in response to a comparison between the turn off time delay and the target time value.

3. The controller of claim 1, wherein the control circuit is coupled to vary the target time value in response to one of: an input voltage of the power converter, a temperature of the power converter, a temperature of the power switch, a switching frequency of the power switch, an on-time of the power switch, or an output power of the power converter.

4. The controller of claim 1, wherein the control circuit is coupled to select the target time value to balance an increased input charge amount for a low on-state voltage drop across conduction terminals of the power switch with an energy loss during turn off of the power switch to reduce power loss of the power converter.

5. The controller of claim 1, wherein the control circuit is coupled to control a duration of the turn on signal to regulate the turn off delay time to the target time value.

6. The controller of claim 1, further comprising: a device control signal source, wherein the device control signal source is coupled to provide a control signal to drive the power switch on; a first switch coupled to receive the turn on signal, wherein the turn on signal controls the first switch to couple the device control signal source to a control terminal of the power switch to turn the power switch on; and a second switch coupled to receive the turn off signal, wherein the turn off signal controls the second switch to couple a reference voltage to the control terminal of the power switch to turn the power switch off.

7. The controller of claim 6, wherein the first switch decouples the device control signal source from the control terminal of the power switch and the second switch couples the reference voltage to the control terminal of the power switch to turn the power switch off.

8. The controller of claim 6, wherein the control signal has a first amplitude to turn the power switch on and a second amplitude to maintain the power switch on, wherein the second amplitude is less than the first amplitude.

9. The controller of claim 8, wherein the control circuit is coupled to regulate the second amplitude or a duration which the control signal is substantially equal to the second amplitude to regulate the turn off time delay.

10. The controller of claim 6, wherein the controller further comprises: a third terminal to provide an emitter signal; and a third switch coupled to receive the emitter signal, wherein the emitter signal controls the third switch to couple an emitter terminal of the power switch to the reference voltage.

11. The controller of claim 1, wherein the power switch is a bipolar junction transistor (BJT) or an insulated gate bipolar transistor (IGBT).

12. The controller of claim 1, wherein the detection circuit is coupled to receive a sense signal representative of a base current of a control terminal of the power switch, wherein the detection circuit is coupled to determine an end of the turn off time delay when positive base current is removed or negative base current flows through the control terminal.

13. The controller of claim 1, wherein the detection circuit is coupled to receive a sense signal representative of a collector voltage of the power switch, wherein the detection circuit is coupled to determine an end of the turn off time delay when the collector voltage rises above a threshold.

14. The controller of claim 1, wherein the detection circuit is coupled to receive a sense signal representative of a collector current of the power switch, wherein the detection circuit determines an end of the turn off time delay when the collector current falls below a threshold.

15. The controller of claim 1, wherein the detection circuit is coupled to receive a sense signal representative of a voltage across conduction terminals of the power switch to determine an end of the turn off time delay.

16. The controller of claim 15, wherein the detection circuit further comprises a comparator coupled to receive the sense signal and a sensing reference, wherein the sensing reference is generated from the sense signal and the detection circuit is coupled to determine the end of the turn off time delay when the sense signal reaches the sensing reference.

17. The controller of claim 16, wherein the detection circuit is a peak detector.

18. The controller of claim 16, wherein the detection circuit further comprises a sample and hold circuit, wherein the sensing reference is a sampled and held value of the sense signal.

19. The controller of claim 16, wherein the sensing reference is a low pass filtered and offset version of the sense signal.

20. The controller of claim 16, wherein the sensing reference is a delayed and offset version of the sense signal.

21. The controller of claim 16, wherein the sensing reference is a sampled and offset version of the sense signal.

22. The controller of claim 16, wherein the sensing reference is a high pass filtered and offset version of the sense signal.

23. The controller of claim 16, wherein the sensing reference is a peak detected and offset version of the sense signal.

24. The controller of claim 16, wherein the sensing reference is a decayed peak detection and offset version of the sense signal.

25. The controller of claim 1, wherein the turn off time delay is the duration of time between an initiating of a turn off of the power switch by the turn off signal and an actual turn off of the power switch.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) For a better understanding of the invention and to show how the same may be carried into effect, reference will now be made, by way of example, to the accompanying drawings, in which:

(2) FIG. 1 is a schematic illustration of a first embodiment;

(3) FIG. 2 shows example waveforms of the first embodiment;

(4) FIG. 3 is a schematic illustration of a V.sub.FB signal change detector embodiment;

(5) FIG. 4 illustrates example waveforms for the V.sub.FB signal change detector embodiment;

(6) FIG. 5 shows example waveforms for a knee-point V.sub.FB signal change detector embodiment;

(7) FIG. 6 is a schematic of a S/H V.sub.FB signal change detector embodiment;

(8) FIG. 7 shows example waveforms for a S/H V.sub.FB signal change detector embodiment;

(9) FIG. 8 shows alternative example waveforms;

(10) FIG. 9 is a schematic illustration of an alternative embodiment;

(11) FIG. 10 shows example waveforms illustrating a BJT Base- and Emitter-Switched scheme;

(12) FIG. 11 is a schematic illustration of an alternative embodiment comprising an IGBT;

(13) FIG. 12a shows method steps of an embodiment; FIG. 12b shows a disc for storing computer instructions for implementing at least a part of the FIG. 12a method;

(14) FIG. 13a shows method steps of an embodiment; FIG. 13b shows a disc for storing computer instructions for implementing at least a part of the FIG. 13a method;

(15) FIGS. 14a-d show, respectively, a relatively simple peak-hold detector, a leaky peak detector, a non-linear peak detector, and waveforms of these types of peak detector

(16) FIG. 15 shows an alternative embodiment as a boost converter

(17) FIG. 16a shows an alternative embodiment as a forward converter with half-bridge drive;

(18) FIG. 16b shows example waveforms of a forward converter with half-bridge drive;

(19) FIG. 17 shows a simplified switching circuit relevant to turn-off conditions of a switching transistor in a SMPC

(20) FIG. 18 shows example waveforms of bipolar switching transistor in a SMPC;

(21) FIG. 19 shows example waveforms of indirect sensing of bipolar switching transistor in a SMPC;

(22) FIG. 20a shows a sensing discriminator for turn-off detection using a signal sampling function, and associated waveforms;

(23) FIG. 20b shows a sensing discriminator for turn-off detection using a signal delay function, and associated waveforms;

(24) FIG. 20c shows a sensing discriminator for turn-off detection using a low pass filter, and associated waveforms;

(25) FIG. 20d shows a sensing discriminator for turn-off detection using a high pass filter, and associated waveforms;

(26) FIG. 20e shows a sensing discriminator for turn-off detection using a resettable peak detector function, and associated waveforms;

(27) FIG. 20f shows a sensing discriminator for turn-off detection using a decaying peak detector function, and associated waveforms;

(28) FIG. 21a shows an embodiment of a decaying peak detector with linear decay; and

(29) FIG. 21b shows an embodiment of a decaying peak detector with exponential decay.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

(30) Embodiments provide a number of improvements to bipolar transistor drive for low cost SMPCs. For example, a wide range of transistors may be driven optimally by regulating their turn-off delay time, generally comprising a charge storage time. This is performed in an embodiment using a reliable, low cost approach that requires minimal, preferably no, additional parts for a primary side-sensing flyback converter.

(31) One embodiment is shown in FIG. 1, with example waveforms in FIG. 2. The offline switched mode power converter may be of any type, for example flyback, boost or forward converter, and is shown here as a single-ended flyback design. The inductive component Lx illustrated in FIG. 1 is a coupled inductor having windings W1 (input, primary winding), W3 (output, secondary winding) and further winding W2 (preferably a sensing signal source in the form of, e.g., an auxiliary or sense winding). However alternative inductive components Lx may be employed, depending on the converter type and the nature of the application. For example a forward converter may employ a transformer, and a boost converter may employ an inductor. Input voltage VIN may be a DC voltage or a rectified AC voltage, for example rectified mains.

(32) The primary switch Q.sub.SW is a power switching device in the form of a bipolar transistor, for example a bipolar junction transistor (BJT), connected in the base-switched configuration. A capacitance C.sub.BE is shown between the base and emitter terminals of the BJT Q.sub.SW in dashed lines. This represents the sum of the intrinsic charge storage in the BJT and any additional capacitance provided between these terminals. The base terminal of BJT Q.sub.SW is connected to a control circuit that, in FIG. 1, is in the form of an integrated circuit, IC. Any of switches Q.sub.BA (which may be referred to as a decoupling switch) and Q.sub.BG (which may be referred to as a coupling switch), and current source I.sub.B (this may be considered to be a, preferably controllable, source of a device control signal to the base or gate of the power switching device), may be integrated into the IC or may be discrete components. Any of switches Q.sub.BA and Q.sub.BG, and current source I.sub.B, may be controlled by turn off signal(s) from circuits comprising circuits (Ccts), some or all of which may be integrated into the IC controller. Base current is provided to the BJT Q.sub.SW from current source IB, via switch Q.sub.BA and IC terminal BD. Switch Q.sub.BG may assist in turning off BJT Q.sub.SWpreferably switch Q.sub.BG is controllable to couple the control (base or gate) terminal to a reference voltage such as Gnd. Generally, turning off occurs in the period t.sub.4 to t.sub.5, which may have a reverse current from the control terminal (e.g., base or gate of the power switching device) as shown for IBD in FIG. 2. In a preferred embodiment switch Q.sub.BG is coupled between the base terminal of the BJT and a negative reference voltage. This provides a larger potential difference to increase the rate of removal of charge from the BJT base terminal. However in many SMPCs a negative reference voltage is not conveniently available. Instead, as illustrated in FIG. 1, switch QBG may be coupled between the base terminal of the BJT and a reference low voltage, for example ground (Gnd). By appropriate control of switches Q.sub.BA and Q.sub.BG, and of current source I.sub.B, BJT Q.sub.SW may be controlled to switch power from V.sub.IN through the input winding W1 to a reference voltage, shown as Gnd in FIG. 1.

(33) Preferably, bias power may be provided to the IC in FIG. 1 from auxiliary winding W2, via rectifier D.sub.AUX and IC terminal Aux.

(34) In FIG. 1 the unrectified signal from low voltage auxiliary winding W2 is detected at feedback IC terminal FB (noting that FB may be an input within or to switching control system comprising the Ccts preferably in the form of an IC; the system may further comprise an output internal or external to Ccts, the output line being use to indicate an on time). Alternatively another low voltage primary side winding, such as a sense winding (not shown), may be used instead of auxiliary winding W2. Other components, e.g. resistor(s) and/or a resistive divider, may be connected between W2 and the FB terminal to ensure that the voltage and current amplitudes of the signal at the FB terminal are appropriate. The FB signal may be processed by any suitable circuits within the IC, for example to reverse the polarity of negative-going signals, and/or to adjust the input impedance of the FB terminal, and/or to further adjust the amplitude of FB signals.

(35) The signal at the FB terminal of the IC in FIG. 1 may be used to sense the voltage across the output winding W3 of the coupled inductor Lx, for example as described in U.S. Ser. No. 11/445,473, U.S. Ser. No. 12/405,618 and U.S. Ser. No. 12/752,611 hereby incorporated in their entirety by reference. Such sensing, referred to as primary side sensing, is performed whilst the output winding W3 is conducting current and the primary switch Q.sub.SW is open. However the signal at the FB terminal may also be used to indirectly sense the voltage across the high voltage input winding W1 to which Q.sub.SW is connected. This may advantageously avoid the cost, space, additional sensing input, and/or power dissipation of high voltage parts that are required to directly measure the high voltage across the input winding. An embodiment employs this indirect measurement technique to detect the rise in Q.sub.SW collector voltage as switch Q.sub.SW turns off.

(36) An illustration of operation of such an embodiment is provided in the waveforms of FIG. 2 and refers to features of the schematic illustration of FIG. 1. An on time of the device of FIG. 2 may be represented by, e.g., t.sub.1-t.sub.5 or t.sub.4-t.sub.5.

(37) A switching cycle generally comprises an on period and immediately preceding and following off periods of the power switching device. For example, a first switching cycle may be considered to extend for example from t.sub.1 through t.sub.4 and t.sub.5 and through a period ending with a following t.sub.1 (not shown) of a second switching cycle. Alternatively, a first switching cycle may be considered to extend for example from t.sub.5 through a following t.sub.1 and t.sub.4 (neither shown) and through a period ending with a following t.sub.5 (not shown) of a second switching cycle. More generally, the start and end of a switching cycle may be considered to be when consecutive instances of a turn off signal(s) being applied, or consecutive instances of a turn on signal(s) being applied for turning on the power switching device. Alternatively, the start and end of a switching cycle may be considered to be when consecutive instances of start of flow of one of the control terminal current (e.g., I.sub.BD), conduction terminal (e.g., collector, emitter, source or drain terminal) current or winding current (e.g., I.sub.W1), or a corresponding change in the sensing signal (e.g., V.sub.FB). Alternatively, the start and end of a switching cycle may be considered to be when consecutive instances of end of flow of one of the control terminal current (e.g., I.sub.BD), conduction terminal (e.g., collector, emitter, source or drain terminal) current or winding current (e.g., I.sub.W1), or a corresponding change in the sensing signal (e.g., V.sub.FB).

(38) In FIG. 2, the waveforms Q.sub.BA and Q.sub.BG illustrate the logic states of those switches, with the higher level representing a switch on (closed) state and the lower level representing a switch off (open) state. At time t.sub.1 switch Q.sub.BA is closed, switch Q.sub.BG is opened, and current source I.sub.B is turned on, providing base current I.sub.BD out of IC terminal BD. In this example base current from current source I.sub.B is held at a constant value while switch Q.sub.BA is closed. Turn-on of BJT Q.sub.SW is initiated, causing current I.sub.W1 to begin to flow through primary winding W1 of the coupled inductor to Gnd. In the flyback converter of FIG. 1 the W1 current takes the form of a linear ramp, as shown in the I.sub.W1 waveform of FIG. 2. The sensing signal, in this embodiment feedback signal V.sub.FB, reflects the rapid change in voltage across the primary winding W1, and hence across the collector-emitter terminals of BJT Q.sub.SW.

(39) At time t.sub.4 switch Q.sub.BA is opened, switch Q.sub.BG is closed, and current source I.sub.B is turned off. However stored charge allows BJT Q.sub.SW to continue to conduct winding current I.sub.W1; this stored charge is primarily removed via the base terminal and Q.sub.BG between times t.sub.4 and t.sub.5, as shown by the negative lobe of base current I.sub.BD. Because the saturation of Q.sub.SW has been carefully controlled (see below), this reverse base current flow I.sub.BD is typically short-lived; it is arranged that only a limited stored charge remains at time t.sub.4 and this is quickly removed by the large negative base current. Switch Q.sub.BG provides a low impedance to this reverse base current and asserts a reliable turn-off when BJT Q.sub.SW opens at time t.sub.5. In this example, the turn-off delay time, T.sub.TOD is the period from t.sub.4 to t.sub.5, ending when the BJT Q.sub.SW actually turns off. More generally, the turn-off delay time may in an embodiment be the storage time or may also include the fall time (time taken for the collector current to fall below some threshold). Nevertheless, the events used to define the start and end of this turn-off delay time may be chosen according to the sensed signals available and the particulars of the drive scheme. For example the turn-off delay time may be defined to start when positive base drive current is removed or when negative base current flow begins. Although these two events are essentially simultaneous in the drive scheme illustrated in FIG. 2, they may occur separatelyas discussed below. The start of the turn-off delay time, t.sub.4, may for example therefore be identified with a level change in a signal sent to switches Q.sub.BG or Q.sub.BA, or by directly sensing the onset of reverse base current. The end of the turn-off delay time, t.sub.5, may in general be detected in the crossing of a threshold value by the current through, or voltage upon, any of the BJT terminals. For example t.sub.5 may be detected as a rise in Q.sub.SW collector voltage, a fall in Q.sub.SW collector current or a fall in negative base current I.sub.BD. Preferably the end of the turn-off delay time, t.sub.5, is detected using the feedback signal V.sub.FB.

(40) Measurement of turn-off delay time may be achieved by any appropriate means, for example by charging a timing capacitor, by counting clock pulses or by comparison to a reference time interval (e.g. target time value T.sub.REF).

(41) The duration of the turn-off delay time T.sub.TOD may be controlled to a desired value T.sub.REF: If the turn-off delay time in a switching cycle is measured, the amplitude(s) and/or duration(s) of the base drive current pulses may be altered accordingly in subsequent switching cycle(s). For example, if the measured turn-off delay time T.sub.TOD is shorter than a reference desired time T.sub.REF, it may be increased in a subsequent switching cycle by increasing the amplitude and/or duration of the base current pulse used to cause transistor conduction. This ensures that BJT Q.sub.SW operation is optimal and most efficient in changing load conditions and/or variations in V.sub.IN, and for a wide range of BJTs. In the example of FIG. 2 the T.sub.TOD signal goes high when switch Q.sub.BG is closed at t.sub.4 and goes low when V.sub.FB crosses a threshold voltage V.sub.THRESHOLD at t.sub.5.

(42) Generally speaking, a shorter turn-off delay time may (a) reduce base current requirements and wastage, thereby reducing power dissipation, and/or (b) reduce turn-off time, and/or may reduce turn-off switching losses in the BJT. However, if the target turn-off delay time is too short BJT conduction losses may be increased, as the saturation voltage V.sub.CE rises prior to time t.sub.5. Optimal turn-off delay time depends on particulars of the input voltage, converter and the load. In offline flyback converters of around 5-10 W rated output power, for example, a target turn-off delay time of around 100-250 ns may provide optimum operation. The target and/or measured turn-off delay time may include some means of correcting for delays in the sensing, processing or signal generation functions of the control circuits. Some experimentation in different operating conditions may be required to select the desired target turn-off delay time for optimum results in a particular power converter. Further, improved efficiency may be achieved by adapting the target turn off delay time to the peak collector current e.g., a) shorter (or longer) turn off time when the peak current is high and/or b) longer turn off time when the input voltage is low.

(43) A further advantage of measuring turn-off delay time is that it may allow some fault conditions, for example those causing deep saturation of the BJT, or premature desaturation, to be rapidly detected.

(44) Desaturation Protection

(45) When using a BJT or an IGBT as a switching device it is important to keep the switching device saturated until the turn off signal is applied. If this is not the case (premature desaturation) then the voltage across the switching device will rise. The switching device enters a state of high current and high voltage. The consequence is a rapid increase of power loss in the switching device. This will reduce the efficiency of the SMPC and can lead to the destruction of the switching device because of over-heating.

(46) The rise in the voltage across the switching device triggers turn off detection. A premature desaturation is detected if turn off is detected before the turn off signal is applied.

(47) Premature desaturation will happen if the amount of charge delivered to the control terminal of the switching device is insufficient to support the conduction of switching device. For example this could be the case if a BJT current gain is too low or before the turn off time delay has reached the target time value when the SMPC experiences a load transient.

(48) To protect the switching device the SMPC should immediately apply the turn off signal when premature desaturation is detected. Applying the turn off signal immediately reduces the time the switching device spends in a state of high current and high voltage. This reduces the power loss in the switching device. Alternatively, the control signal (base current, gate voltage) may be increased immediately so the transistor can support the conduction current within the switching cycle.

(49) To protect against premature desaturation in subsequent switching cycles the SMPC could increase the amount of charge delivered to the switching device. Also the current demand per switching cycle could be reduced by changing the operating conditions. For example an increase in the switching frequency or a reduction in the output power reduces the current demand per switching cycle. Then the SMPC can continue operating in normal mode.

(50) In some cases the premature desaturation persists. Then the SMPC can enter a protective mode to further protect the switching device. The protective mode could operate the SMPC at low duty to test if the abnormal conditions have ceased or shutting down the SMPC indefinitely.

(51) Continuing now to describe the figures, when switch Q.sub.SW desaturates near the end of the turn-off delay time, the Q.sub.SW collector-emitter voltage V.sub.CE and hence the feedback signal voltage V.sub.FB rise rapidly. This V.sub.FB transition, and hence the end of the turn-off delay time, can be detected by any appropriate means. For example, the crossing of a suitable threshold value V.sub.THRESHOLD by the feedback signal voltage V.sub.FB may be detected. This may be performed, for example, by a comparator. However due to the characteristics of the coupling of the feedback signal to the IC, the most appropriate threshold voltage may differ according to the particulars of the converter, BJT, base drive scheme, load, and other operating conditions such as (particularly) input voltage. This is because the minimum in V.sub.FB generally depends on at least these variables.

(52) Improved sensing of the end of the turn-off delay time, t.sub.5, can be obtained by detecting a relative change in the feedback signal voltage from its value when the switch is closed (i.e. between t1 and t4 in FIG. 2). This approach may reduce variability compared to a simple voltage threshold technique. A threshold change in the feedback signal voltage may be conveniently detected in a number of ways. For example a decaying peak detector may be used, or a non-linear decaying peak detector, as described in U.S. patent application Ser. No. 12/752,611 hereby incorporated by reference in its entirety. Such arrangements may enable re-use of circuits and components used to indirectly sense the voltage across the output winding W3. Further detail of a non-linear decaying peak detector, so-termed due to an absence of switches, is given in the following.

(53) Referring to the schematic circuit diagram of FIG. 3 showing a detection/detector circuit, this circuit embodiment allows a change in the V.sub.FB signal to be detected but generally avoids the use of any switches or diodes of a conventional decaying peak detector. This is advantageous because such components may introduce noise into the system. However modifications to the circuit, for example in which one or more switches are retained, are possible and may provide some advantages over the circuit illustrated in FIG. 3. As shown in FIG. 3, the circuit may comprise a signal follower comprising for example R1 and C2, and a comparator COMP. Optionally (not shown) there may be provided signal buffering and conditioning between W2 and the point marked V.sub.FB.

(54) The absence of switches and diodes modifies the behaviour of this circuit from that of a linear decaying peak detector. For example, the decay signal Vp can decay faster than a linear decaying peak detector's decaying signal when V.sub.FB is smaller than Vp. This is possible because current can flow through coupling circuitry such as resistor R1 to the auxiliary winding W2 as well as from it. Nonetheless this circuit still retains the main characteristics of a decaying peak. One advantage is that the turn-off point detector recovers faster from large voltage transients, such as that at Q.sub.SW turn-on.

(55) The operation of the non-linear decaying peak detector circuit embodiment can be described as follows. The sensing signal waveform V.sub.FB is acquired from the auxiliary (or other) winding W2, optionally via a potential divider (R.sub.FB2, R.sub.FB1) and/or other intermediate circuits such as clamps, buffers and the like (not shown). Additional intermediate circuits may reverse the polarity of negative-going V.sub.FB signals. V.sub.FB is applied to the non-inverting input of the comparator COMP. Capacitor C2 and current source I2 (preferably a constant current generator) create a decay signal at a node identified by voltage Vp. This decay signal approximates decaying portions of the sensing signal waveform V.sub.FB. Comparator COMP is triggered when the current through resistor R1 is equal to zero. Therefore COMP detects when V.sub.FB becomes smaller than Vp and when V.sub.FB becomes larger than Vp. The relative size of V.sub.FB and Vp is therefore indicated by the value of SLOPE (otherwise referred to as peak), the output of COMP. Thus, in the present embodiment, a change of SLOPE may be considered to be an indication of the end of a turn off time delay.

(56) An interesting property of this circuit embodiment and its analogues is the rate of change of decay signal Vp, which depends on the R.sub.1C.sub.2 time constant. The V.sub.P rate of change is preferably lower than that of sensing signal V.sub.FB, but fast enough for the V.sub.P signal to settle between t.sub.1 and t.sub.4. The point of interest in V.sub.FB is that indicating a threshold change from its value when the switch Q.sub.SW is closed. This is shown in FIG. 4's illustrative circuit waveforms (The precise form of the waveforms of FIG. 4 depend on circuit component values). Note that the polarity of the V.sub.FB signal has been reversed from that in FIG. 2.

(57) As previously explained, the threshold change point occurs when the feedback signal voltage V.sub.FB deviates by an amount V.sub.THRESHOLD from its value when the switch is closed. Towards the end of the switch Q.sub.SW on-time t.sub.4, V.sub.FB is positive and changes slowly in time. Resistor R.sub.1 ensures that there is a potential difference between sensing signal V.sub.FB and decay signal Vp before the switch begins to turn off. The amplitude of sensing signal waveform V.sub.FB begins to decrease rapidly as the turn-off process progresses and, since it falls faster than decay signal Vp, the two signals become equal at a crossing, or threshold change, point. This triggers the comparator COMP, which changes state from High to Low. At this threshold change point the sensing signal V.sub.FB has changed by an amount V.sub.THRESHOLD from its value when the switch was closed (i.e. fully on). This corresponds to a change in the Q.sub.SW collector voltage, which is the quantity that that is being indirectly sensed. Beyond the threshold change point the sensing signal V.sub.FB falls faster than the decay signal Vp and departs from that signal.

(58) Various parameters can be adjusted to ensure accurate and/or robust operation of the circuit. For example the rate of the decay signal V.sub.P can be set by choosing appropriate values of resistor R1 and capacitor C2. As another example, the potential difference between V.sub.FB and V.sub.P can be set by resistor R.sub.1 and current source I.sub.2. A smaller current I.sub.2 produces a smaller potential difference between sensing signal V.sub.FB and decay signal V.sub.P, as shown in FIG. 5. This enables an earlier response to the rapid fall of V.sub.FB when the switch turns off for a given setting of the decay signal V.sub.P, but also increases susceptibility to noise in the sensing signal V.sub.FB.

(59) By adjusting these parameters a suitable value of V.sub.THRESHOLD may be chosen, corresponding to a desired threshold change in the collector voltage of switch Q.sub.SW. The optimum choice of this Q.sub.SW collector voltage change depends on a number of factors, including SMPC type, Q.sub.SW switching mode, etc. As an example, for a flyback converter of around 5 W rated power, a collector voltage change of 20 V in 150 ns may provide reliable performance.

(60) In FIG. 3 components capacitor C2 and current source I2 are shown as having fixed values. A resistor R.sub.2 may be used in parallel to or as a replacement for the current source I.sub.2. Furthermore either or both of C.sub.2 and I.sub.2 (or R.sub.2) may be trimmable after semiconductor processing to provide reduced variation over the manufacturing process. This can provide a more consistent determination of the turn-off point across a wafer of ICs or within, or between, wafer batches.

(61) Implementations of the circuit of FIG. 3 preferably use a decay signal of slower decay than a sensing signal to detect the turn-off point of BJT Q.sub.SW. Embodiments also provide a decaying peak detector with variable decay rate dependent on input signal amplitude. Embodiments may provide efficient use of silicon area and/or compare favourably with those making direct measurement of the Q.sub.SW collector voltage.

(62) An alternative approach, using the same circuit as shown in FIG. 3, is to detect a threshold in the rate-of change (the knee-point) rather than a voltage threshold. Then the size of the R.sub.1 resistor is reduced so the V.sub.P signal closely tracks the V.sub.FB signal. The comparator will detect when the rate of change in V.sub.FB is so large that C.sub.2dV.sub.FB/dt>I.sub.2. The effects of the offset and delay will be of second order to the rate-of-change because the R.sub.1C.sub.2 delay and the R.sub.1I.sub.2 offset are small. This is shown in FIG. 5's illustrative circuit waveforms. However, noise sensitivity may be increased in such an embodiment.

(63) Due to noise and ringing components in the sensing signal V.sub.FB there may be more than one crossing point whilst the switch is on. If all crossing points of the sensing signal V.sub.FB and decay signal Vp during the Q.sub.SW on-time are detected, then the turn-off point may be identified as the last instance of V.sub.FB decaying below the value of Vp prior to the feedback signal falling to zero or some other predefined value. An alternative strategy is to detect the last transition occurring within a pre-determined delay from application of the turn-off signal.

(64) It is possible to combine the peak detector for the W1 transition (switch turn-off) and the W3 transition (end of output winding current flow). It may be preferable to dynamically set different values for R1, C2 and I2 for optimum sensing of the two transitions. Also the polarity may be reversed for the detection points and/or some sort of rectification of the V.sub.FB signal may be provided by the intermediate circuits.

(65) Another embodiment of the t.sub.5 detection can use a sample-and-hold circuit where the sensing signal V.sub.FB is sampled some time after t.sub.1. The sampling time point t.sub.SH is preferably chosen between t.sub.1 and t.sub.4, where the sensing signal V.sub.FB has settled. The t.sub.5 point is detected when the sensing signal V.sub.FB deviates by an amount V.sub.THRESHOLD from its sampled value. It may be better to sample close to the t.sub.4 time so the droop on V.sub.FB is eliminated from the threshold change detection. Otherwise the V.sub.FB droop between t.sub.SH and t.sub.4 must be considered when selecting the V.sub.THRESHOLD value. An embodiment using a sample-and-hold circuit is shown in FIG. 6 having the output SLOPE (otherwise referred to as peak), example waveforms of which are shown in FIG. 7.

(66) Considering peak detection more generally, peak detectors that may be used in an embodiment for improved sensing of the end of the turn-off delay time may be of the types shown in FIG. 14 (wherein the output peak of each peak detector may otherwise be referred to as SLOPE). Specifically, FIG. 14a shows a relatively simple peak detector example, which will hold the peak value indefinitely. The V.sub.P sample voltage must be reset in order to catch smaller peaks later. FIG. 14b shows an example leaky peak detector, wherein the sampled peak value V.sub.P is allowed to leak away to catch smaller peaks later. FIG. 14c shows a non-linear peak detector, which generally catches all peaks, big or small. FIG. 14d shows example waveforms of these types of peak detector for comparison, wherein the peak is detected on the falling edge of the peak signal on the comparator output.

(67) More complex switching schemes may offer improved BJT operation in some applications and for some converter types. Another example scheme is illustrated in the waveforms of FIG. 8, wherein I.sub.BD is a device control signal having a first amplitude between t.sub.1 and t.sub.2 and a second amplitude between t.sub.2 and t.sub.3.

(68) The alternative switching scheme of FIG. 8 is very similar to that of FIG. 2, but some interesting differences are noted in the following. The current source I.sub.B is initially set to a high level until time t.sub.2, ensuring that the BJT Q.sub.SW quickly reaches a desired state of saturation. Preferably, for high frequency switching applications, deep saturation is avoided since it leads to excessive stored charge and a prolonged turn-off time. A preferred approach is to employ quasi-saturation, in which an appropriate balance of on-state and switching losses is reached. The amplitude and/or duration of the initial current level may be fixed or made dependent on some variable or parameter. For example, the amplitude and/or duration of the high initial current level may be modulated according to power on the input or output of the SMPC, e.g., may be modulated by the amplitude of the load current on the converter output, or it may be made dependent on a parameter relating to demand. Additionally or alternatively it may be scaled according to input voltage V.sub.IN. As the required degree of saturation is reached the BJT collector-emitter voltage V.sub.CE quickly attains an acceptably low level. Such a fast turn-on may be useful for example in converter topologies featuring high Q.sub.SW current early in the switch on-time, such as the forward converter or the continuous conduction mode flyback or boost converter.

(69) In this embodiment, from time t.sub.2 until t.sub.3 the current source I.sub.B output is reduced to a lower level, intended to maintain the BJT Q.sub.SW in conduction until the point at which it turns off at t.sub.5, following a turn-off delay time T.sub.TOD equal to T.sub.REF. The amplitude and/or duration of this current level may be made variable. Although illustrated as a single pulse of constant amplitude in FIG. 8, the base drive current produced from time t.sub.2 to t.sub.3 may vary in amplitude and time. For example its amplitude may be made to depend on the BJT emitter or collector current flowing, providing proportional base drive. It may additionally or alternatively comprise any number of pulses which may modulate the Q.sub.SW base current in a PWM or PFM manner. Examples of suitable base drive current schemes are described in, for example, PCT/GB2008/050299 and PCT/GB2008/050300 hereby incorporate by reference in their entirety.

(70) From time t.sub.3 until t.sub.4 the current source I.sub.B is turned off and switch Q.sub.BA is opened. Switch Q.sub.BG may, as shown in FIG. 8, remain open during this period, substantially preventing base current flow. The Q.sub.SW base terminal voltage is determined by the base-emitter junction charge, and is typically around 0.5 V higher than the emitter terminal voltage. In this period, the charge stored on the base sustains transistor conduction; sufficient charge applied to the base in the interval t.sub.1 to t.sub.3 supports the total collector current flow until time t.sub.5. Current I.sub.W1 through winding W1 continues to ramp and transistor conduction maintains BJT collector-emitter voltage V.sub.CE at a low level. The open base period between times t.sub.3 and t.sub.4 may allow charge carriers in the base to recombine and prevent current focussing at the emitter.

(71) At time t.sub.4 switch Q.sub.BG is closed, forcing collector current to flow out primarily through the base terminal of Q.sub.SW to Gnd. Hence in the example switching scheme of FIG. 8, the start of the turn-off delay time has been chosen as the onset of reverse base current, rather than the cessation of forward base current. In the example of FIG. 8 the open base period between times t.sub.3 and t.sub.4 reduces the amount of stored charge compared to that of FIG. 2, hence there is a shorter duration of reverse base current between times t.sub.4 and t.sub.5. This may allow a shorter target turn-off delay time to be employed.

(72) Although the illustration of FIG. 1 shows a base-switched common emitter BJT, principles of the embodiment are applicable to other drive topologies. A preferred solution is illustrated schematically in FIG. 9 comprising a first power transistor in the form of power switching device Q.sub.sw and a second transistor in the form of switch Q.sub.EG. The offline power converter may again be of any type, but a flyback converter has been illustrated to aid comparisons with FIG. 1, FIG. 2 and FIG. 8.

(73) Some or all of switches Q.sub.BA, Q.sub.BG and Q.sub.EG, diode D.sub.EA, and current source I.sub.B, may be integrated into an IC Controller, as illustrated in FIG. 9. This approach may minimise the overall parts count for a power converter. Alternatively some or all of these devices may be discrete components, for example in order to reduce power dissipation in, and/or the die size of, the IC. Alternatively more parts, particularly Q.sub.SW, may be integrated into a single IC. They may be formed in any appropriate manufacturing process. A conduction path in the form of, e.g., the connection between the ED and Aux terminals, may be provided by a controllable switch Q.sub.EA rather than by diode (or switch) D.sub.EA. Switches Q.sub.BA, Q.sub.BG and/or Q.sub.EG (and Q.sub.EA if present) may be controlled by circuits comprising circuits (Ccts), some or all of which may be integrated into the IC controller. Alternatively any or all of the control circuits, including current source I.sub.B, may be embodied as discrete components. FIG. 9 may be described as having a charging circuit comprising at least Q.sub.EG, D.sub.EA (or a switch in place of D.sub.EA) and/or C.sub.AUX, the charging circuit for powering a switching controller such as Ccts, the switching controller for example to control any one or more of the switches shown in FIG. 9 including Qsw, Q.sub.BA, etc., wherein Q.sub.SW and Q.sub.EG form first and second transistors of a switching circuit and a current diversion circuit comprises at least DEA (which may be replaced by a further switch).

(74) The primary switch Q.sub.SW is a bipolar transistor, for example a bipolar junction transistor (BJT), connected in the cascode, or emitter-switched, configuration. Q.sub.EG is a low voltage, high current switch on the IC (or provided discretely), controlling Q.sub.SW emitter current to a reference voltage, here chosen to be 0 V (Gnd). Among the advantages of employing the cascode arrangement are: fast switchingboth on and offdue to Q.sub.EG being a fast, low voltage device; high voltage withstanding capability with an advantageous reverse-bias safe operating area (RBSOA); and/or low no-load power consumption due to the ability to use the gain of Q.sub.SW to pass start-up current. At start-up, a small current from V.sub.IN through start-up resistor R.sub.START causes the Q.sub.SW base voltage to rise, biasing Q.sub.SW to conduct collector-emitter current. This current, which is larger than the base current flowing through R.sub.START by a factor of the Q.sub.SW gain, flows via diode D.sub.EA to the IC's charge reservoir C.sub.AUX (since switches Q.sub.BA, Q.sub.BG and Q.sub.EG are open). R.sub.START may thus be chosen to have a relatively large value, for example around 40 M, allowing power dissipation in R.sub.START to be reduced. Thus, a charge store of an embodiment comprises capacitor C.sub.AUX and/or may be used to provide power to control switching of one or more switching devices such as Q.sub.sw, Q.sub.BA, Q.sub.BG, Q.sub.EG and/or any form of switch used to control I.sub.B.

(75) The base terminal of a BJT in a cascode configuration is, in the prior art, typically biased to a DC voltage to ensure conduction when the emitter switch is closed. The present embodiment instead employs switching of the Q.sub.SW base terminal to more precisely control operation of the BJT: The Q.sub.SW base terminal is connected to a low reference voltage, chosen to be Gnd in FIG. 9, via switch Q.sub.BG. The Q.sub.SW base terminal is also connected to a source of current I.sub.B via switch Q.sub.BA. I.sub.B may be an active current source or simply a resistor connected to a voltage source, such as the Aux rail.

(76) This switched base and emitter approach may retain the reliability advantage of open emitter switching inherent to a cascode arrangement but also limiting the peak voltage excursion of the emitter during turn off. With the emitter terminal open there is substantially no opportunity for current gain in the BJT provided that the peak emitter voltage does not cause any current flow into connected circuits (e.g. D.sub.EA). Without opportunity for emitter current flow, the BJT can withstand higher collector voltages during and immediately following turn-off without adverse breakdown that could degrade power efficiency and reliability. The practical result is that, with appropriate switch control in an embodiment, the BJT's applicable breakdown voltage may be higher in this configuration compared to configurations that are only base-switched. This may add a cost advantage to the base- and emitter-switched arrangement.

(77) By appropriate control of switches Q.sub.EG, Q.sub.BG and Q.sub.BA and of current source I.sub.B a wide range of BJT control techniques may be implemented. The alternative switching scheme of FIG. 8 may be modified for use in the switched base and emitter arrangement of FIG. 9, as illustrated in FIG. 10.

(78) A difference in FIG. 10 compared to FIG. 8 is the addition of the switching waveform Q.sub.EG. In this example switches Q.sub.BA and Q.sub.EG are closed (i.e. turned on) simultaneously at time t.sub.1, providing base current drive I.sub.BD out of IC terminal BD whilst the emitter terminal of Q.sub.SW is connected to Gnd via Q.sub.EG. This closes Q.sub.SW, causing current to flow through winding W1 of coupled inductor Lx to Gnd. Switch Q.sub.EG is opened at time t.sub.4, when switch Q.sub.BG is closed. This provides alternative definitions for the start of the turn-off delay time to those used in the base-switching arrangement of FIG. 1. In general switch Q.sub.EG is controlled in opposite phase to Q.sub.BG, with an exception described in unpublished provisional application U.S. 61/767,023 hereby incorporated by reference in its entirety. Note that between times t.sub.4 and t.sub.5, i.e. during the turn-off delay time, the primary inductor current continues, flowing to ground as reverse base current via the IC terminal BD and switch Q.sub.BG. Hence switch Q.sub.BG must be capable of conducting currents as large as those conducted by switch Q.sub.EG. The larger reverse base current amplitude than that depicted in FIG. 2 or FIG. 8 is due to the emitter-switched approach. This may allow a shorter target turn-off delay time to be employed than for base-only switching, as the stored charge is removed from BJT Q.sub.SW more quickly.

(79) With some modifications the same approach may be taken to switch an insulated gate bipolar transistor (IGBT), as shown in the example of FIG. 11. Modifications in this alternative embodiment generally relate to the voltage-driven nature of the IGBT, in contrast to the current-driven nature of the BJT. Gate drive may be provided from a suitable voltage source, for example the Aux (Auxiliary) rail of the IC. The gate voltage amplitude and/or timing may be modulated in a similar fashion to the base current modulation described in the examples above for BJT drive. The charged IGBT gate-emitter capacitance C.sub.GE, rather than accumulated base charge, may keep the IGBT in conduction when drive is removed from the gate terminal. As with the BJT, bipolar charges (holes and electrons) build up in the IGBT during conduction, and are preferably removed prior to completion of turn-off. Hence regulation of the turn-off delay time may be similarly beneficial to IGBTs. Although illustrated by a gate- and emitter-switched arrangement analogous to that of FIG. 9, this embodiment may equivalently employ a gate switched arrangement.

(80) The embodiment of FIG. 11 may also be used to drive other MOS-gated devices, such as metal-oxide-semiconductor field effect transistors (MOSFETs), despite their unipolar nature. To achieve a target turn off delay with such a device, e.g., IGBT, the gate drive voltage may be modulated to vary the excess stored charge in the switching transistor, considering an IBGT as a MOS switch connecting the base of an internal PNP transistor to 0V (its emitter goes to the winding and the collector goes to 0V). In the on-state, the MOS may form a resistor providing base current from 0V. When the winding current is higher, it causes the voltage of the PNP emitter to rise, taking the base with it, so that more base current is delivered via the MOS resistance. If the MOS resistance is very low then the Vce of the PNP is correspondingly low, but to achieve this there is more excess charge in the PNP transistor, which could cause long turn-off delays and deeper saturation with higher turn-off loss. This may be mitigated by allowing a higher MOS voltage, which would be reflected in higher Vce, requiring less deep saturation. The MOS voltage may be modulated by changing the gate voltage during the on-state. To do this there would be provided a variable gate voltage drive, rather than a variable base current drive.

(81) Regulation of the turn-off delay time for Q.sub.SW may be performed simultaneously with other switch control schemes. For example, wherein the durations of the on and/or off states of a power switch are adjusted in order to regulate the output voltage and/or current of the converter. In this respect the total on time of the primary switch Q.sub.SW, represented by the period t.sub.1 to t.sub.5, may be controlled to implement any pulse width modulation (PWM) and/or pulse frequency modulation (PFM) type switching scheme. In this way the desired converter power transfer may be controlled. This may enable the converter to provide a specified output in the presence of variations in current and/or voltage at the input and/or output terminals. Adding turn-off delay time regulation to such output regulation control may allow power switch operation to be optimised over a wide range of power converter conditions.

(82) Converter Configurations

(83) Switch mode power converters are used to transform power from one voltage to another, optionally with galvanic isolation, regulation and other facilities. Many different configurations are available with which embodiments of the above described techniques may be employed, including, but not limited to: flyback, forward, buck, series-resonant and so forth. In all of these, one or more switching devices are used to chop the incoming power at high frequency, applying the resulting high frequency power to an inductive device to perform the transformation. Common switching devices are MOSFET, bipolar and IGBT transistors. Bipolar transistors (BJTs) are generally lower cost than other types but have more complex drive requirements. Typically it is advantageous to operate SMPCs at higher frequency to reduce overall size of the converter and this requires faster turn-on and turn-off of the switches. Bipolar transistors generally switch more slowly than MOSFETs and this is a drawback that limits their application. By carefully managing the turn-off delay time it is possible to extend the applicable frequency range of bipolar transistors while avoiding excessive power loss in the switching process.

(84) A flyback configuration has been used as an example for the application of turn-off delay time control, but the technique can be readily applied to other configurations. Likewise, base-switched (as in FIG. 1)) or emitter-switched (as in FIG. 9) transistor drive can be used, optionally with galvanic isolation. FIG. 15 shows application of the emitter-switched configuration to a boost converter. Components with the same reference in both of the Figures have similar functions. The significant difference between the boost converter of FIG. 15 and the flyback converter of FIG. 9 is that, in the boost converter, output power is taken from the winding W1 via diode Dout instead of via a separate output winding. A boost converter of this form has similar switching waveforms to a flyback converter and all aspects of turn-off time control are likewise applicable.

(85) FIG. 16a illustrates an alternative application of the technique to an isolated forward converter using a half-bridge switching configuration. Switch transistors Q1 and Q2 apply power from the input voltage to the input winding W1 of the transformer. Output winding W3 delivers power to the output circuit with inductor Lout enabling step-down voltage regulation according to the switching pattern of Q1 and Q2 in known ways. Turn-on and -off of Q1 and Q2 is by drivers DR1 and DR2 via isolating transformers TD1 and TD2, again in known ways. Other methods of applying turn on and turn off signals to the switching transistors are known. Further winding W2 of the transformer provides a sense signal to the control circuits and may optionally also provide power to operate the circuits and drivers as described previously. The control circuits provide Timing and Level control signals to the drivers. The timing signals control the timing of the turn-on and turn-off of the drive current to the switching transistors while the Level signals control the amplitude of at least the turn-on current. Typical waveforms are shown in FIG. 16b. The drivers apply charge to the switching transistors as current Ibq1 and Ibq2 from the isolating driver transformers. Though the waveforms show constant positive current to turn the transistors on, a variety of current waveforms can be used and a two level (initial high followed by reduced current) is advantageous to speed up turn on of the transistors. Each driver is configured to apply negative current to turn off the transistor and there is a delay from the start of this negative current to the time when the collector-emitter voltage of the switch starts to rise. When it rises, the voltage across winding W1 changes accordingly as does the voltage from the sense winding W2. The control circuits process this sense signal and adapt the drive to the transistors, via Level and/or Timing signals to regulate the turn off delay time, Tdoff. Embodiments can operate with fixed level drive, but the amount of turn-on charge delivered to the switching transistors can be varied by changing the timing signals to deliver current to the transistors for varying durations.

(86) A particular issue with half-bridge driver circuits is the critical requirement to avoid overlap of conduction of the two switches. Should this happen, very large currents can flow (shoot-through) which is potentially destructive, as well as reducing efficiency. Fine control of the turn-off delay of a switch allows the control system to turn on the opposing switch earlier than would otherwise be the case. This, in turn, allows higher frequency switching, which enables smaller inductive components, or greater conduction duration as a fraction of the overall switching cycle. Increasing the conduction proportion generally improves efficiency because the current in the switching circuit will be lower for a given power transfer. Though shoot-through is a particular characteristic of half-bridge circuits, the benefits of faster switching allowing higher operating frequency and greater conduction proportion are applicable to all other types of SMPCs.

(87) The configurations of FIG. 15 and FIG. 16a illustrate embodiments with isolated or non-isolated SMPC, single or multiple switching transistors, isolated or non-isolated drive to the switches and single-ended or half-bridge configurations. It will be clear to persons skilled in the art of SMPCs that the turn-off delay control technique may be applied to any of the wide range of SMPC configurations.

(88) Sensing Turn-Off

(89) We now describe some further examples of techniques for detecting turn-off which may be employed to regulate turn-off delay of power switching transistors. This is difficult because of varying converter operating conditions (input voltage, switch characteristics, conduction time etc.). For bipolar transistors (BJT, IGBT), turn off is not a well-defined transition and is further obscured by current flow through the device due to capacitive currents.

(90) SMPCs using bipolar transistors are typically constructed using circuits comprising a power source, the collectoremitter conduction path through the BJT or IGBT switch and some inductive component as shown in FIG. 17. The emitter circuit may include an emitter switch or may be coupled to the supply by some low-resistance path. During the on state of the switch, current builds up and flows around the circuit. As the switch turns off, the voltage across the conduction terminals (collector C and emitter E) rises rapidly due to the effect of established current flow in the inductance. Note that the nature of the inductance varies between converter types. For Flyback, boost and buck converters it is the total component inductance, the voltage only becoming clamped when the rectifier diode starts to conduct power to the load. In forward converters it may be the leakage inductance of the transformer or some inductance in the secondary circuit reflected to the primary. Whatever the nature of the inductance, the current/voltage characteristic of the switch load is inductive at turn off which means the C-E voltage typically rises and inductor current continues to flow. Interruption of current flow is normally caused by turn-off of the switch rather than any effect in the inductive component. Transistor turn-off is progressive, the switch current reduces during the turn off process. Over a short timescale, the inductive load current can be considered constant so the excess current goes into charging circuit capacitances (such as C.sub.BC, C.sub.BE and self capacitance of the windingnot shown) yielding a rate of change of collector voltage.

(91) FIG. 18 illustrates currents and C-E voltage of a typical bipolar switch in a flyback SMPC operating from a high voltage power source, and is not to scale. Other converter types have different patterns of the current flow within the conduction time, but turn-off behaviour is similar. Key points of the C-E voltage are marked: 1. After a turn-on delay, C-E current flow start and causes fall of C-E voltage. Current goes to discharge circuit capacitances and may also build in the inductor circuit (continuous conduction mode flyback/boost, buck converters etc.). 2. During the main conduction time, inductor current typically increases and there is an associated small increase of C-E voltage on-state voltage 3. Turn-off is initiated by reversal of the base current by the control circuit. There is little immediate effect on the C-E voltage but as base charge is removed, the transistor can no longer sustain the whole inductor current at the previous low collector voltage. As the collector voltage rises, the transistor can conduct the current. Consequently the initial rise of C-E voltage is dependent on the Ic/Vce characteristics with reducing base charge. 4. After the C-E voltage rises above a few volts, the transistor can no longer sustain the inductor current at any collector voltage so the excess current goes into circuit capacitances (including the base-collector capacitance), and the C-E voltage rises rapidly 5. When the rectifier of the SMPC comes into conduction, the C-E voltage stops rising (or slows considerably) as inductive current is diverted away from the transistor

(92) This illustrates the progressive nature of turn-off and the actual turn off point can be defined arbitrarily, but is in the region of point 3 in FIG. 18. A system to regulate turn off delay needs to detect a point such as 3.

(93) Direct sensing of the C-E voltage allows comparison to a threshold voltage as described in prior art. However this often requires discrimination of relatively low voltages (a few volts) while sustaining fast transitions to very high switching voltages in the off state (in the context of SMPCs operating from high voltage power sources). This is difficult and expensive to implement. In addition the on-state voltage is unpredictable, being affected by load current, device performance, temperature etc. and this makes choice of threshold voltage difficult.

(94) Indirect sensing via a coupled winding avoids the difficulty of withstanding high voltages and allows lower cost, possibly integrated, circuits to discriminate the turn off point. FIG. 19 illustrates voltage waveforms from a coupled winding. Note that the phase of the winding has been arranged to invert the sensed voltage relative to the C-E voltage and the scale of the sensed voltage depends on the turns ratio of the windings. Zero volt conditions do not coincide because of the nature of inductive coupling and the supply voltage in the switch circuit. In a flyback converter, for example, Vsp=Vht/NtVon. Where Nt is the turns ratio and Von is the on-state C-E voltage. Therefore, Vsp is affected by supply voltage and behaviour of the transistor. Discriminating a turn off point reliably by this method employs comparison of Vsense to some reference or threshold voltage, illustrated as Vth. If Vht and Von vary little then it may be possible to use a fixed threshold (offset) as Vth. However, if either changes substantially then an adaptive reference may be used.

(95) Various methods can be used, as illustrated in FIG. 20.

(96) FIG. 20a (Similar to FIG. 6) shows a method where the sense voltage is sampled at some time during the conduction condition according to a timing signal produced by a control circuit. The sampled voltage is then offset by a fixed amount and used as a reference comparison to the sense signal to determine when the sense voltage has changed by more than the threshold amount.

(97) FIG. 20b uses a time delay (Td) and an offset to create a reference signal, again for comparison to the sense signal, giving an off-detect signal in a similar way

(98) FIG. 20c has a low pass filter in place of the time delay of FIG. 20b. A filter characteristic is chosen to have an appropriate and, approximately, steady group delay (Tgd) across the relevant frequency range (pass and transition band of the filter).

(99) Converse to using a lowpass filter in the reference path it is possible to use a highpass filter as shown in FIG. 20d. A highpass characteristic gives an output sensitive to change of input. A differentiator is a special case where the highpass characteristic rises linearly with frequency. Such a characteristic is not ideal for this application since it becomes excessively sensitive to small, but fast, deviations of the signal. Better is a highpass characteristic with a shelf above some cutoff frequency. With such a filter it may be possible to use a simple fixed threshold to produce a reliable off-detect signal from the highpass output. Alternatively, the threshold may be adapted according to the peak value of the sense signal, derived by other circuits not shown.

(100) Though the amplitude and timing of the sense signal may vary considerably in any SMPC application, the maximum value of the sense signal (assuming polarity is as illustrated) represents a state where the switch is reliably on. Hence a peak detector may be used to capture this value to use, with an offset, as a reference to determine turn off. This is illustrated in FIG. 20e. A peak detector has to be reset otherwise it will hold its output indefinitely so would not respond to subsequent changes in conditions. Reset can be triggered by a signal from a control circuit any time after turn-off has been detected but before the next conduction state of the switch.

(101) It is possible to configure a peak detector to self reset by leaking away the peak value over time. Such a detector can be used in place of the resettable peak detector of FIG. 20e. The arrangement and waveforms are shown in FIG. 20f. Provided the peak detector decays faster than the conditions of the SMPC change (e.g. Vht) then the detector will reliably re-capture the peak of the sense signal on each cycle of the SMPC. Examples of decaying peak detector circuits are shown in FIG. 21. In FIG. 21a, capacitor C holds the peak value set by the amplifier with its negative feedback and the diode. The current sink causes the capacitor voltage to decay at a constant rate whenever the rate of decay of the sense signal is faster than that rate. A resistor is shown in FIG. 21b in place of the current sink of FIG. 21a. This gives an exponential decay and may be equally effective in this application.

(102) Note that in all of the above, the offset may be applied before the comparison to either the sense signal or to the processed signal. Further, the offset may be replaced or supplemented by a scaling function so that the effective offset reduces as Vht (or other switching voltage) reduces.

(103) Advantages, any one or more of which may be achieved by any of the embodiments, are: brings known benefits of storage time/turn-off delay time regulation (e.g. minimal base drive power dissipation for given performance, reliable fast switching, high efficiency, and/or allows wide range of BJTs to be accommodated, etc.), at zero incremental cost for some PSS flyback embodiments due to use of a low voltage coupled winding; reduces or avoids offset problems associated with measuring an absolute voltage as the threshold for end of turn-off delay time, thereby serving a wider range of BJTs, converter types and/or line and load conditions, etc.

(104) No doubt many other effective alternatives will occur to the skilled person. It will be understood that the invention is not limited to the described embodiments and encompasses modifications apparent to those skilled in the art lying within the spirit and scope of the claims appended hereto.