METHOD FOR FORMING AN ISOLATION STRUCTURE HAVING MULTIPLE THICKNESSES TO MITIGATE DAMAGE TO A DISPLAY DEVICE

Abstract

In some embodiments, the present disclosure relates to a method of forming a display device, comprising: forming a first reflector electrode and a second reflector electrode over an interconnect structure, wherein the first reflector electrode is laterally separated from the second reflector electrode; depositing a first isolation layer over the first and second reflector electrodes; forming a first masking layer directly overlying the first reflector electrode; depositing a second isolation layer over the first isolation layer and over the first masking layer; forming a second masking layer over the second isolation layer and directly overlying the second reflector electrode; performing a first removal process to remove portions of the first and second isolation layers that do not directly underlie the first or second masking layers; and performing a second removal process to remove the first and second masking layers.

Claims

1. A method of forming a display device, comprising: forming a first reflector electrode and a second reflector electrode over an interconnect structure, wherein the first reflector electrode is laterally separated from the second reflector electrode; depositing a first isolation layer over the first and second reflector electrodes; forming a first masking layer directly overlying the first reflector electrode, but not the second reflector electrode; depositing a second isolation layer over the first isolation layer and over the first masking layer; forming a second masking layer over the second isolation layer and directly overlying the second reflector electrode, but not the first reflector electrode; performing a first removal process to remove portions of the first and second isolation layers uncovered by the first or second masking layers; and performing a second removal process to remove the first and second masking layers.

2. The method of claim 1, wherein the first removal process comprises dry etching, and wherein the second removal process comprises wet etching.

3. The method of claim 1, wherein the first and second isolation layers are a same material.

4. The method of claim 1, wherein the forming of the first masking layer comprises: depositing a first conformal masking layer over the first isolation layer; depositing a first conformal oxide layer over the first conformal masking layer; patterning the first conformal oxide layer using a dry etchant to form a first oxide layer that directly overlies the first reflector electrode; and patterning the first conformal masking layer using a wet etchant according to the first oxide layer to form the first masking layer.

5. The method of claim 4, wherein after the first removal process, the first oxide layer has a higher average surface roughness than before the first removal process.

6. The method of claim 1, wherein after the second removal process, a first segment of the first isolation layer overlies the first reflector electrode, and a second segment of the first isolation layer overlies the second reflector electrode, wherein the first segment of the first isolation layer is laterally spaced apart from the second segment of the first isolation layer.

7. The method of claim 6, further comprising: forming a first transparent electrode over the first segment of the first isolation layer; forming a second transparent electrode over the second segment of the first isolation layer; forming a first optical emitter structure over the first transparent electrode; and forming a second optical transparent electrode over the second transparent electrode.

8. A method of forming a display device, comprising: forming a first reflector electrode and a second reflector electrode over an interconnect structure, wherein the first reflector electrode is laterally separated from the second reflector electrode; depositing a first isolation layer over the first and second reflector electrodes; forming a first masking layer over the first reflector electrode and over the second reflector electrode, and patterning the first masking layer to directly overlie the first isolation layer and the first reflector electrode but not directly overlie the second reflector electrode; depositing a second isolation layer over the patterned first masking layer and over the second reflector electrode; forming a second masking layer over the second isolation layer, and patterning the second masking layer to directly overlie the second reflector electrode but not directly overlie the first reflector electrode; performing a first removal process to remove portions of the first and second isolation layers that are not covered by the first or second masking layers; and after the first removal process, performing a second removal process to remove the first and second masking layers.

9. The method of claim 8, wherein the performing of the second removal process leaves other portions of the first and second isolation layers that were covered by the first or second masking layers in place.

10. The method of claim 8, further comprising: after the second removal process, forming a first transparent electrode over a remaining portion of the first isolation layer and forming a second transparent electrode over a remaining portion of the second isolation layer.

11. The method of claim 10, further comprising: forming a first optical emitter structure over the first transparent electrode; and forming a second optical emitter structure over the second transparent electrode.

12. The method of claim 8, wherein the first removal process forms trenches that extend downwards to define a first segment of the first isolation layer that is over the first reflector electrode and a second segment of the first isolation layer that is over the second reflector electrode.

13. The method of claim 12, further comprising: forming second dielectric barrier structures in the trenches, the second dielectric barrier structures having a height that extends from an upper surface of the first and second reflector electrodes to over an upper surface of the first and second transparent electrodes.

14. A method of forming a display device, comprising: forming a first reflector electrode and a second reflector electrode over an interconnect structure on a semiconductor substrate, wherein the first reflector electrode is laterally separated from the second reflector electrode; depositing a first isolation layer over the first and second reflector electrodes, the first isolation layer comprising a first dielectric material; forming a first masking layer over the first reflector electrode and over the second reflector electrode, and patterning the first masking layer to directly overlie the first isolation layer and the first reflector electrode but not directly overlie the second reflector electrode; depositing a second isolation layer over the patterned first masking layer and over the second reflector electrode, the second isolation layer comprising a second dielectric material that differs from the first dielectric material; forming a second masking layer over the second isolation layer, and patterning the second masking layer to directly overlie the second reflector electrode but not directly overlie the first reflector electrode; performing a first removal process to remove portions of the first and second isolation layers that are not covered by the first or second masking layers; and after the first removal process, performing a second removal process to remove the first and second masking layers.

15. The method of claim 14, wherein the performing of the second removal process leaves other portions of the first and second isolation layers that were covered by the first or second masking layers in place.

16. The method of claim 14, further comprising: after the second removal process, forming a first transparent electrode over a remaining portion of the first isolation layer and forming a second transparent electrode over a remaining portion of the second isolation layer.

17. The method of claim 16, further comprising: forming a first optical emitter structure over the first transparent electrode; and forming a second optical emitter structure over the second transparent electrode.

18. The method of claim 17, wherein the first optical emitter structure is disposed at a first height over an upper surface of the semiconductor substrate and the second optical emitter structure is disposed at a second height over the upper surface of the semiconductor substrate, the second height being greater than the first height.

19. The method of claim 14, wherein the first removal process forms trenches that extend downwards to define a first segment of the first isolation layer that is over the first reflector electrode and a second segment of the first isolation layer that is over the second reflector electrode.

20. The method of claim 19, further comprising: forming second dielectric barrier structures in the trenches, the second dielectric barrier structures having a height that extends from an upper surface of the first and second reflector electrodes to over an upper surface of the first and second transparent electrodes.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0004] FIG. 1 illustrates a cross-sectional view of some embodiments of a display device having an isolation structure arranged over a reflector electrode structure, where the isolation structure comprises a first portion and further comprises a second portion that is spaced apart from and has a different thickness than the first portion.

[0005] FIG. 2 illustrates a cross-sectional view of some additional embodiments of a display device as in FIG. 1, as well as an example light path through a portion of the isolation structure.

[0006] FIGS. 3 and 4 illustrates cross-sectional views of some additional embodiments of a display device as in FIG. 1, wherein the display device comprises an isolation structure having layers of different materials.

[0007] FIGS. 5-18, 19A-19C, 20, and 21 illustrate cross-sectional views of some embodiments of a method of forming a display device having an isolation structure arranged over a reflector electrode structure, wherein the isolation structure comprises first and second portions spaced apart from one another to mitigate damage to the reflector electrode structure.

[0008] FIG. 22 illustrates a flow diagram of some embodiments of a method corresponding to FIGS. 5-18, 19A-19C, 20, and 21.

DETAILED DESCRIPTION

[0009] The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

[0010] Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

[0011] A display device includes an array of pixel regions, wherein each pixel region comprises a portion of an isolation structure arranged between a reflector electrode and a transparent electrode. A via structure may extend through the isolation structure to electrically couple the reflector electrode to the transparent electrode. An optical emitter structure may be arranged over the transparent electrode. The isolation structure may comprise silicon dioxide and the portion of the isolation structure may have a thickness that corresponds to a certain color. For example, during operation of the display device, an electrical signal (e.g., voltage) may be applied to the transparent electrode from circuitry coupled to the reflector electrode, the via structure, and the transparent electrode. The electrical signal may cause light to be produced at the interface between the optical emitter structure and the transparent electrode (e.g., due to electron-hole recombination). The light may reflect off a top surface of the isolation structure and/or may travel through the isolation structure, reflect off of the reflector electrode, and travel back towards the top surface of the isolation structure. Due to constructive interference of a given wavelength of light at the top surface of the isolation structure, and/or destructive interface of other wavelengths of light at the top surface of the isolation, colored light according to the thickness of the portion of the isolation structure may be emitted from a top surface of the optical emitter structure.

[0012] To form the isolation structure, a first isolation layer may, for example, be formed over a first reflector electrode and a second reflector electrode. The first isolation layer may then be patterned to remove the first isolation layer from the second reflector electrode. A second isolation layer may then be formed over the first isolation layer and the second reflector electrode. However, the patterning of the first isolation layer may damage (e.g., pits, crystal defects, increased surface roughness, etc.) a top surface of the second reflector electrode, and thus, impact the interface between the second isolation layer and the second reflector electrode. For example, an etching process may be used to remove the first isolation layer that covers the second reflector electrode. The etching process may use a dry etchant and damage the top surface of the second reflector electrode by increasing the surface roughness. Because the second reflector electrode receives and reflects light at the top surface of the second reflector, when the top surface is damaged, the reflected light may scatter, which may cause the emitted light to be a different color and/or reduce the intensity of the emitted light, for example. Thus, the aforementioned patterning process may result in an unreliable display device.

[0013] Various embodiments of the present disclosure are directed towards a method of forming an isolation structure comprising a first portion, a second portion, and a third portion that are separated from one another to mitigate damage to the underlying reflector electrode structure of a display device. In some embodiments, a first reflector electrode and a second reflector electrode are formed over an interconnect structure. A first isolation layer is deposited over the first and second reflector electrodes. A first masking layer is formed over the first reflector electrode such that the first masking layer directly overlies the first reflector electrode and does not directly overlie the second reflector electrode. A second isolation layer is deposited over the first isolation layer and over the first masking layer. A second masking layer is then formed over the second reflector electrode such that the second masking layer directly overlies the second reflector electrode and does not directly overlie the first reflector electrode or the first masking layer.

[0014] A first removal process is performed to remove portions of the first and second isolation layers that do not directly underlie the first or second masking layers. The first and second masking layers are hard masks, and thus, during the first removal process, the first and second masking layers protect the underlying first isolation layer, second isolation layer, first reflector electrode, and second reflector electrode from damage caused by the first removal process. For example, in some embodiments, the first removal process utilizes plasma dry etching, and the first and second masking layers block ions from passing through to underlying first and second isolation layers and underlying first and second reflector electrodes. Further, a second removal process is performed to remove the first and second masking layers. The second removal process may be performed by a wet etch to selectively remove the first and second masking layers, while the first and second reflector electrodes are protected by the first and second isolation layers. Thus, because the first and second reflector electrodes are respectively protected during the first and second removal processes to form the isolation structure, damage to the first and second reflector electrodes is mitigated to produce a reliable device.

[0015] FIG. 1 illustrates a cross-sectional view 100 of some embodiments of a display device comprising an isolation structure having first, second, and third portions separated from one another.

[0016] The display device of the cross-sectional view 100 includes a first pixel region 101a, a second pixel region 101b, and a third pixel region 101c. Each of the first, second, and third pixel regions 101a, 101b, 101c are configured to emit a different color of light (e.g., red, green, blue) when subjected to an electrical signal (e.g., voltage), and the color of light depends on the thickness and material of an isolation structure 106. For example, in some embodiments, the first pixel region 101a may comprise a first portion 106a of the isolation structure 106 that has a first thickness t.sub.1; the second pixel region 101b may comprise a second portion 106b of the isolation structure 106 that has a second thickness t.sub.2; and the third pixel region 101c may comprise a third portion 106c of the isolation structure 106 that has a third thickness t.sub.3. In some embodiments, the first, second, and third thicknesses t.sub.1, t.sub.2, t.sub.3 are each different from one another. For example, in some embodiments, the first thickness t.sub.1 may be less than the second and third thicknesses t.sub.2, t.sub.3, and the second thickness t.sub.2 may be less than the third thickness t.sub.3.

[0017] In some embodiments, the first portion 106a, the second portion 106b, and the third portion 106c of the isolation structure 106 may each comprise one or more oxides, such as, for example, silicon dioxide, aluminum oxide, or the like. In other embodiments, the first portion 106a, the second portion 106b, and the third portion 106c of the isolation structure 106 may comprise a nitride (e.g., silicon nitride), or some other material that has optical properties, such that colored light is visible from the surface of the material and the colored light is dependent on the thickness of each portion (106a, 106b, 106c) of the isolation structure 106. For example, the first thickness t.sub.1 may correspond to red light; the second thickness t.sub.2 may correspond to blue light; and the third thickness t.sub.3 may correspond to green light.

[0018] The first portion 106a of the isolation structure 106 may be arranged between a first reflector electrode 102a and a first transparent electrode 112a. The second portion 106b of the isolation structure 106 may be arranged between a second reflector electrode 102b and a second transparent electrode 112b. The third portion 106c of the isolation structure 106 may be arranged between a third reflector electrode 102c and a third transparent electrode 112c. A first optical emitter structure 110a, a second optical emitter structure 110b, and a third optical emitter structure 110c may be arranged over the first transparent electrode 112a, the second transparent electrode 112b, and the third transparent electrode 112c, respectively. In some embodiments, a first via structure 108a, a second via structure 108b, and a third via structure 108 extend through the first portion 106a of the isolation structure 106, the second portion 106b of the isolation structure 106, and the third portion 106c of the isolation structure 106, respectively. The via structures (108a, 108b, 108c) extend from a top surface to a bottom surface of the portions (106a, 106b, 106c) of the isolation structure 106. Thus, the first via structure 108a may electrically couple the first reflector electrode 102a to the first transparent electrode 112a; the second via structure 108b may electrically couple the second reflector electrode 102b to the second transparent electrode 112b; and the third via structure 108c may electrically couple the third reflector electrode 102c to the third transparent electrode 112c.

[0019] In some embodiments, the first, second, and third reflector electrodes 102a, 102b, 102c may be coupled to control circuitry 120. For example, in some embodiments, the first, second, and third reflector electrodes 102a, 102b, 102c are disposed over an interconnect structure 130 comprising a network of interconnect wires 134 and interconnect vias 136 embedded in an interconnect dielectric structure 132. In some embodiments, the interconnect structure 130 is arranged over a substrate 122 and coupled to semiconductor devices 124. In some embodiments, the semiconductor devices 124 may be, for example, metal oxide semiconductor field-effect transistors (MOSFETs) comprising source/drain regions 124a within the substrate 122 and a gate electrode 124b over the substrate 122. The gate electrode 124b may be separated from the substrate 122 by a gate dielectric layer 124c. The control circuitry 120 is configured to selectively supply an electrical signal (e.g., voltage) to each of the first, second, and third pixel regions 101a, 101b, 101c to emit colored light as indicated by digital data. For example, if the electrical signal (e.g., voltage) is supplied to the first reflector electrode 102a from the control circuitry 120, the electrical signal (e.g., voltage) may cause the first optical emitter structure 110a to produce light, and that light may reflect off of top surfaces of the first portion 106a of the isolation structure 106 and/or travel through the first portion 106a of the isolation structure 106, reflect off of the first reflector electrode 102a and exit through the top surfaces of the first portion 106a of the isolation structure 106. Due to constructive and/or destructive interference, colored light dependent on the first thickness t.sub.1 and material of the first portion 106a of the isolation structure 106 is visible.

[0020] In some embodiments, first barrier structures 104 and/or second barrier structures 114 separate the first, second, and third pixel regions 101a-101c. In some embodiments, each of the first, second, and third portions 106a, 106b, 106c of the isolation structure 106 are completely separated from one another by the second barrier structures 114.

[0021] For example, in some embodiments, a first line 150 may be arranged between the first and second portions 106a, 106b of the isolation structure 106 without intersecting the first or second portions 106a, 106b of the isolation structure 106. The first line 150 may continuously extend in a first direction that is normal to an upper surface of the first reflector electrode 102a, and also may be arranged between the first reflector electrode 102a and the second reflector electrode 102b, between the first transparent electrode 112a and the second transparent electrode 112b, and between the first optical emitter structure 110a and the second optical emitter structure 110b. In some embodiments, the first line 150 may intersect the first and second barrier structures 104, 114. Thus, in some embodiments, the second barrier structures 114 directly overlie the first barrier structures 104. Further, a second line 152 that is parallel to the first line 150 and continuously extends in the first direction may be arranged between the second portion 106b of the isolation structure 106 and the third portion 106b of the isolation structure 106 without intersecting the second or third portions 106b, 106c of the isolation structure 106. In some embodiments, each of the first, second, and third portions 106a, 106b, 106c of the isolation structure 106 may be completely separated from one another as a result of protecting the first, second, and third reflector electrodes 102a, 102b, 102c during manufacturing of the isolation structure 106; in some embodiments, the separation amongst the first, second, and third portions 106a, 106b, 106c of the isolation structure 106 also mitigates optical interference between each of the first, second, and third pixel regions 101a, 101b, 101c to provide a reliable display device.

[0022] FIG. 2 illustrates a cross-sectional view 200 of some embodiments of a display device comprising an isolation structure having first, second, and third portions separated from one another and an example light path during operation of the display device.

[0023] The display device in the cross-sectional view 200 includes a first reflector electrode 102a having a first width w.sub.1, a second reflector electrode 102b having a second width w.sub.2, and a third reflector electrode 102c having a third width w.sub.3. In some embodiments, the first width w.sub.1, the second width w.sub.2, and the third width w.sub.3 may be substantially equal to one another, as in FIG. 1, for example, whereas in other embodiments, as in FIG. 2, the first, second, and third widths w.sub.1, w.sub.2, w.sub.3 may be different from one another. For example, in some embodiments, the third width w.sub.3 may be smaller than the second width w.sub.2, and the second width w.sub.2 may be smaller than the first width w.sub.1. In some embodiments, the smallest width (e.g., w.sub.1) corresponds to the pixel region (e.g., 101a) that has the portion (e.g., 106a) of the isolation structure 106 with the smallest thickness (e.g., t.sub.1). Similarly, in some embodiments, the largest width (e.g., w.sub.3) corresponds to the pixel region (e.g., 101a) that has the portion (e.g., 106c) of the isolation structure (e.g., 106) with the largest thickness (e.g., t.sub.3). However, in other embodiments, the widths (e.g., w.sub.1, w.sub.2, w.sub.3) of the reflector electrodes (e.g., 102a, 102b, 102c) in each pixel region (e.g., 101a, 101b, 101c) do not have a correlation with the thicknesses (e.g., t.sub.1, t.sub.2, t.sub.3) of the portions (e.g., 106a, 106b, 106c) of the isolation structure (e.g., 106).

[0024] The cross-sectional view 200 also illustrates an exemplary first light path 202 in the first pixel region 101a and an exemplary second light path 204 in the second pixel region 101b. In some embodiments, light is generated by the first optical emitter structure 110a and the second optical emitter structure 110b due to an electrical signal (e.g., voltage) applied to the first reflector electrode 102a and the second electrode 102b, respectively, by the control circuitry 120. For example, in the cross-sectional view 200, the first pixel region 101a and the second pixel region 101b are “ON” (e.g., light is generated at the first and second optical emitter structures 110a, 110b), whereas the third pixel region 101c is “OFF” (e.g., light is not generated by the third optical emitter structure 110c). In the first pixel region 101a, the exemplary first light path 202 shows how in some embodiments, the generated light at the first optical emitter structure 110a may reflect off of a top surface of the first portion 106a of the isolation structure 106 and/or travel through the first portion 106a of the isolation structure 106, reflect off of the first reflector electrode 102a, and travel back up towards the top surface of the first portion 106a of the isolation structure 106. Due to constructive interference of a first wavelength and/or destructive interference of remaining wavelengths, colored light having the first wavelength that is emitted/visible from a top surface of the first optical emitter structure 110a in the first pixel region 101a. The first wavelength is associated with the first thickness t.sub.1 and material(s) of the first portion 106a of the isolation structure 106 and, in some embodiments, is the only wavelength or the predominant wavelength emitted/visible from the top surface of the first optical emitter structure 110a.

[0025] Similarly, in the second pixel region 101b, the exemplary second light path 204 shows how in some embodiments, the generated light at the second optical emitter structure 110b may reflect off of a top surface of the second portion 106b of the isolation structure 106 and/or travel through the second portion 106b of the isolation structure 106, reflect off of the second reflector electrode 102b, and travel back up towards the top surface of the second portion 106b of the isolation structure 106. Due to constructive of a second wavelength and/or destructive interference of remaining wavelengths, colored light having the second wavelength is emitted/visible from a top surface of the second optical emitter structure 110b in the second pixel region 101b. The second wavelength is associated with the second thickness t.sub.2 and material(s) of the second portion 106b of the isolation structure 106 and, in some embodiments, is the only wavelength or the predominant wavelength emitted/visible from the top surface of the second optical emitter structure 110b. In some embodiments, because the second thickness t.sub.2 of the second portion 106b of the isolation structure 106 is different than the first thickness t.sub.1 of the first portion 106a of the isolation structure 106, the second wavelength will be different from the first wavelength, and thus, the second pixel region 101b emits a different colored light than the first pixel region 101a. Thus, the control circuitry 120 may use digital data to selectively turn “ON” one or more of the pixel regions (e.g., 101a, 101b, 101c) to produce an optical image.

[0026] FIG. 3 illustrates a cross-sectional view 300 of some embodiments of a display device comprising an isolation structure having first, second, and third portions, wherein the second and third portions comprise multiple layers.

[0027] The display device in the cross-sectional view 300 includes: 1) a first portion 106a of an isolation structure 106 comprising a first isolation layer 302; 2) a second portion 106b of the isolation structure 106 comprising a second isolation layer 304 arranged over the first isolation layer 302; and 3) a third portion 106c of the isolation structure 106 comprising the second isolation layer 304 arranged over the first isolation layer 302 and arranged below a third isolation layer 306. The first, second, and third portions 106a, 106b, 106c of the isolation structure 106 are still separated from one another by the second barrier structures 114. In some embodiments, the first, second, and third isolation layers 302, 304, 306 comprise different materials. For example, in some embodiments, the first isolation layer 302 may comprise aluminum oxide; the second isolation layer 302 may comprise silicon dioxide; and the third layer may comprise some other material that has optical properties, such as silicon nitride. In other embodiments, each of the first isolation layer 302, the second isolation layer 304, and the third isolation layer 306 may comprise a same material, such as, for example, silicon dioxide. In such embodiments, the isolation layers (302, 304, 306) may not be distinguishable from one another, and the first, second, and third portions 106a, 106b, 106c of the isolation structure 106 may look like the first, second, and third portions 106a, 106b, 106c of the isolation structure 106 illustrated in the cross-sectional view 100 of FIG. 1.

[0028] In some embodiments, the first thickness t.sub.1 of the first portion 106a of the isolation structure 106 may equal a thickness of the first isolation layer 302. In some embodiments, the first portion 106a of the isolation structure 106 contacts the first reflector electrode 102a at a first interface 308 and contacts the first transparent electrode 112a at a second interface 310. The first thickness t.sub.1 of the first portion 106a of the isolation structure 106 may be measured from the first interface 308 to the second interface 310 in a first direction normal to a top surface of the first reflector electrode 102a. In some embodiments, the second thickness t.sub.2 of the second portion 106b of the isolation structure 106 may equal a sum of the thickness of the first isolation layer 302 and a thickness of the second isolation layer 304. In some embodiments, the second portion 106b of the isolation structure 106 contacts the second reflector electrode 102b at a third interface 312 and contacts the second transparent electrode 112b at a fourth interface 314. The second thickness t.sub.2 of the second portion 106b of the isolation structure 106 may be measured from the third interface 312 to the fourth interface 314 in the first direction. In some embodiments, the third thickness t.sub.3 of the third portion 106c of the isolation structure 106 may equal a sum of the thickness of the first isolation layer 302, the thickness of the second isolation layer 304, and a thickness of a third isolation layer 306. In some embodiments, the third portion 106c of the isolation structure 106 contacts the third reflector electrode 102c at a fifth interface 316 and contacts the third transparent electrode 112c at a sixth interface 318. The third thickness t.sub.3 of the third portion 106c of the isolation structure 106 may be measured from the fifth interface 316 to the sixth interface 318 in the first direction.

[0029] The cross-sectional view 300 of FIG. 3 further illustrates that in some embodiments, the first, second, and third via structures 108a, 108b, 108c may respectively extend completely through the first, second, and third portions 106a, 160b, 106c of the isolation structure 106. In some embodiments, the via structure (108a,108b,108c) comprises a material that completely fill the space between outer sidewalls of each via structures (108a, 108b, 108c). In other embodiments (e.g., FIG. 1), the transparent electrode (112a, 112b, 112c) fills some of the space between the outer sidewalls of the via structure (108a, 108b, 108c). In such embodiments, the electrical connection between the transparent electrode (112, 112b, 112c) and the reflector electrode (102a, 102b, 102c) may be more efficient because the via structure (108a, 108b, 108c) is thinner between the reflector electrode (102a, 102b, 102c) and the transparent electrode (112a, 112b, 112c).

[0030] FIG. 4 illustrates a cross-sectional view 400 of an isolation structure having first, second, and third portions, wherein the third portion of the isolation structure comprises second and third layers comprising a same material.

[0031] The cross-sectional view 400 of FIG. 4 illustrates some embodiments of a display device wherein the portions (106a, 106b, 106c) of the isolation structure (106) may be wider than their respective overlying transparent electrodes (112a, 112b, 112c) and/or optical emitter structures (110a, 110b, 110c).

[0032] Further, the display device in the cross-sectional view 400 includes the first, second, and third portions 106a, 106b, 106c of the isolation structure 106. In some embodiments, the third portion 106c of the isolation structure 106 may comprise the first isolation layer 302, the second isolation layer 304, and the third isolation layer 304. In some embodiments, the first isolation layer 302 may comprise a first material, and the second and third isolation layers 304, 306 may comprise a second material that is different than the first material. For example, in some embodiments, the first material may comprise aluminum oxide, and the second material may comprise silicon dioxide. In some embodiments, the first isolation layer 302 may be thinner than each of second and third isolation layers 304, 306. In such embodiments, the first isolation layer 302 may comprise aluminum oxide, for example, because during deposition, it may be easier to control the thickness of aluminum oxide than silicon dioxide, for example. Because the second and third isolation layers 304, 306 may comprise the same second material, a seventh interface 402 between the second and third isolation layers 304, 306 may not be distinguishable, as illustrated by a dotted line.

[0033] FIGS. 5-18, 19A-19C, 20, and 21 illustrate cross-sectional views 500-1800, 1900A-1900C, 2000, and 2100 of some embodiments of a method of forming an isolation structure over a reflector electrode structure to prevent damage to the reflector electrode structure and to produce a reliable display device. Although FIGS. 5-18, 19A-19C, 20, and 21 are described in relation to a method, it will be appreciated that the structures disclosed in FIGS. 5-18, 19A-19C, 20, and 21 are not limited to such a method, but instead may stand alone as structures independent of the method.

[0034] As shown in the cross-sectional view 500 of FIG. 5, in some embodiments, control circuitry 120 may be formed over a substrate 122. In some embodiments, the control circuitry 120 may comprise an interconnect structure 130 arranged over a substrate 122. The interconnect structure 130 may comprise interconnect wires 134 and interconnect vias 136 embedded in an interconnect dielectric structure 132. In some embodiments, the interconnect wires and vias 134, 136 may comprise copper, tungsten, or the like. The interconnect structure 130 may be coupled to semiconductor devices 124 integrated on the substrate 122. In some embodiments, the semiconductor devices 124 may be or comprise metal oxide semiconductor field-effect transistors (MOSFETs), wherein the MOSFETs comprise source/drain regions 124a in the substrate 122. The semiconductor devices 124 may further comprise a gate electrode 124b arranged over a gate dielectric layer 124c on the substrate 122.

[0035] As shown in the cross-sectional view 600 of FIG. 6, a first dielectric layer 602, a first barrier layer 603, and a second dielectric layer 604 may be formed over the interconnect structure 130. In some embodiments, the first dielectric layer 602, the first barrier layer 603, and the second dielectric layer 604 may comprise a same material. In other embodiments, at least the first barrier layer 603 may comprise a different material than the first and/or second dielectric layers 602, 604. The first barrier layer 603 may comprise a dielectric material that may also act as an etch stop layer to protect the interconnect structure 130. For example, in some embodiments, the first barrier layer 603 may comprise a nitride (e.g., silicon nitride), a carbide (e.g., silicon carbide), or the like. Further, in some embodiments, the first and second dielectric layers 604 may comprise a dielectric material such as, for example, nitride (e.g., silicon nitride, silicon oxynitride), a carbide (e.g., silicon carbide), an oxide (e.g., silicon oxide), borosilicate glass (BSG), undoped silicate glass (USG), phosphoric silicate glass (PSG), borophosphosilicate glass (BPSG), a low-k oxide (e.g., a carbon doped oxide, SiCOH), or the like. In some embodiments, the first and/or second dielectric layers 604 may comprise a same material as the interconnect dielectric structure 132. In some embodiments, the first dielectric layer 602, the first barrier layer 603, and/or the second dielectric layer 604 may each be formed using a deposition process (e.g., physical vapor deposition (PVD), chemical vapor deposition (CVD), PE-CVD, atomic layer deposition (ALD), sputtering, etc.).

[0036] As shown in the cross-sectional view 700 of FIG. 7, portions of the first dielectric layer 602, the second dielectric layer 604, and the first barrier layer (603 of FIG. 6) are removed to define cavities 702 separated by first barrier structures 104. Each cavity 702 may expose a top one of the interconnect vias 136. The cavities 702 may be formed using photolithography and removal (e.g., etching) processes. In some embodiments, each cavity 702 may have equal widths, wherein a first width w.sub.1 is equal to a second width w.sub.2 and a third width w.sub.3. In other embodiments, at least one of the first, second, or third widths w.sub.1, w.sub.2, w.sub.3 is different.

[0037] As shown in the cross-sectional view 800 of FIG. 8, a conductive material 802 may be deposited over the interconnect structure 130, such that the conductive material 802 fills in the cavities (702 of FIG. 7). In some embodiments, the conductive material 802 comprises a metal that is both electrically conductive and optically reflective. For example, in some embodiments, the conductive material 802 may comprise aluminum or aluminum copper. The conductive material 802 may be deposited over the interconnect dielectric structure 132 using a deposition process (e.g., physical vapor deposition (PVD), chemical vapor deposition (CVD), PE-CVD, atomic layer deposition (ALD), sputtering, etc.). In some embodiments, the conductive material 802 overfills the cavities (702 of FIG. 7), such that the conductive material 802 has top surfaces above the second dielectric layer 604.

[0038] As shown in the cross-sectional view 900 of FIG. 9, a planarization process (e.g., chemical mechanical planarization (CMP)) is performed to remove portions of the conductive material (802 of FIG. 8) that are above the second dielectric layer 604, thereby forming a first reflector electrode 102a, a second reflector electrode 102b, and a third reflector electrode 102c. The first reflector electrode 102a may have the first width w.sub.1, the second reflector electrode 102b may have the second width w.sub.2, and the third reflector electrode 102c may have the third width w.sub.3. The first, second, and third reflector electrodes 102a, 102b, 102c may have upper surfaces that are substantially co-planar with one another. Further, the first, second, and third reflector electrodes 102a, 102b, 102c may have upper surfaces that are substantially co-planar with the second dielectric layer 604. In other embodiments, the planarization process may remove the second dielectric layer 604, for example, and thus, the first, second, and third reflector electrodes 102a, 102b, 102c may have upper surfaces that are substantially co-planar with the first barrier structures 104. The first, second, and third reflector electrodes 102a, 102b, 102c may each be coupled to a different one of the semiconductor devices 124, in some embodiments. Further, each of the first, second, and third reflector electrodes 102a, 102b, 102c may be laterally spaced apart from one another and electrically isolated by one another by the first barrier structures 104.

[0039] In some embodiments, after the planarization process, the first reflector electrode 102a may have a first average surface roughness, the second reflector electrode 102b may have a second average surface roughness, and the third reflector electrode 102c may have a third average surface roughness. In some embodiments, the first, second, and third average surface roughness may be substantially equal to one another, as each reflector electrode (102a, 102b, 102c) comprises a same material and is formed simultaneously using a same process method (e.g., deposition of the conductive material 802 of FIG. 8 followed by a planarization process). Because the reflector electrodes (102a, 102b, 102c) have an optical function to reflect light, a low average surface roughness is preferred to mitigate the scattering of light upon reflection. In some embodiments, to measure average surface roughness, a roughness measurement tool (e.g., a profilometer, atomic force microscopy (AFM), etc.) calculates a mean line along a surface and measures the deviation between the height of a peak or valley on the surface from the mean line. After measuring many deviations at many peaks and valleys throughout the surface, the average surface roughness is calculated by taking the mean of the many deviations, where the deviations are absolute values. In other embodiments, the surface roughness is quantified by measuring a total thickness variation (TTV). The TTV of a layer is the difference between the smallest thickness and the largest thickness of the layer. The TTV is measured throughout the length of a layer.

[0040] As shown in the cross-sectional view 1000 of FIG. 10, a first isolation layer 302 may be formed over the first, second, and third reflector electrodes 102a, 102b, 102c. In some embodiments, the first isolation layer 302 may comprise a material that has optical properties such that such that colored light is visible from the surface of the material, and wherein the colored light is dependent on the thickness of the first isolation layer 302. In some embodiments, the first isolation layer 302 may comprise, for example, an oxide, such as aluminum oxide or silicon dioxide. The first isolation layer 302 may have a first thickness t.sub.1, and in some embodiments, the first thickness t.sub.1 may be in a range of between, for example, approximately 200 angstroms and approximately 600 angstroms. In other embodiments, the first thickness t.sub.1 may be in a range of between, for example approximately 49 angstroms and approximately 51 angstroms. In such other embodiments, because the first isolation layer 302 may be thin (e.g., less than 100 angstroms), the first isolation layer 302 may comprise aluminum oxide that is deposited by atomic layer deposition (ALD), which allows for precise control of the first thickness t.sub.1. In some embodiments, the first isolation layer 302 may be formed using a different deposition process than ALD, such as physical vapor deposition (PVD), chemical vapor deposition (CVD), PE-CVD, sputtering. The first isolation layer 302 may directly contact the first, second, and third reflector electrodes 102a, 102b, 102c.

[0041] Further, a first conformal masking layer 1004 may be deposited over the first isolation layer 302. The first conformal masking layer 1004 may comprise, for example, titanium, titanium nitride, tantalum, tantalum nitride, silicon nitride, or the like. Thus, the first conformal masking layer 1004 may be deposited using a deposition process (e.g., physical vapor deposition (PVD), chemical vapor deposition (CVD), PE-CVD, atomic layer deposition (ALD), sputtering, etc.).

[0042] In some embodiments, a first conformal oxide layer 1006 may be formed over the first conformal masking layer 1004. The first conformal oxide layer 1006 may be used to more precisely pattern the first conformal masking layer 1004, as illustrated in FIGS. 11 and 12. However, it will be appreciated that in some embodiments, the first conformal oxide layer 1006 may be omitted. In some embodiments, the first conformal oxide layer 1006 may comprise an oxide material such as, for example, silicon dioxide, silicon oxynitride, aluminum oxide, or the like. The first conformal oxide layer 1006 may, in some embodiments, be formed by using a deposition process (e.g., physical vapor deposition (PVD), chemical vapor deposition (CVD), PE-CVD, atomic layer deposition (ALD), sputtering, etc.).

[0043] As shown in the cross-sectional view 1100 of FIG. 11, the first conformal oxide layer (1006 of FIG. 10) may be selectively patterned to form a first oxide layer 1106 over the first conformal masking layer 1004. The first oxide layer 1106 is formed to directly overlie the first reflector electrode 102a, and without directly overlying the second or third reflector electrodes 102b, 102c. Further, in some embodiments, the first oxide layer 1106 completely overlies the first reflector electrode 102a, and thus, the first oxide layer 1106 may have a width that is about equal to or greater than the first width w.sub.1 of the first reflector electrode 102a.

[0044] In some embodiments, the first oxide layer 1106 may be formed by, for example, a photolithography/etching process or some other suitable process. In some embodiments, a dry etching process may be used to form the first oxide layer 1106, and the first conformal masking layer 1004 may block the passage of ions during the dry etching process, thereby protecting the underlying first isolation layer 302 and first, second, and third reflector electrodes 102a, 102b, 102c from damage due to dry etching.

[0045] As shown in the cross-sectional view 1200 of FIG. 12, portions of the first conformal masking layer (1004) that are uncovered by the first oxide layer 1106 may be removed to form a first masking layer 1204. Thus, in some embodiments, the first oxide layer 1106 acts as a mask to form the first masking layer 1204. In some embodiments, a wet etching process is used to remove portions of the first conformal masking layer (1004). The wet etching process may use a wet etchant comprising, for example, hydrogen peroxide. The wet etchant used in the wet etching process does not remove or affect the first isolation layer 302, the second reflector electrode 102b, and the third reflector electrode 102c. Thus, the first isolation layer 302, the second reflector electrode 102b, and the third reflector electrode 102c may remain substantially unchanged during the formation of the first oxide layer 1106 and of the first masking layer 1204. If dry etching were used, ions from the dry etching may pass through the first isolation layer 302 and impinge on the second reflector electrode 102b and the third reflector electrode 102c. This may lead to damage (e.g., composition defects, structural defects, etc.) to the first isolation layer 302, the second reflector electrode 102b, and the third reflector electrode 102c. Such damage may, in turn, lead to light scattering and hence negatively affect the reliability of the display device. In some embodiments, the first masking layer 1204 may have curved outer sidewalls 1204s as a result of the lateral effect of the wet etching process.

[0046] As shown in the cross-sectional view 1300 of FIG. 13, a second isolation layer 304 may be formed over the first isolation layer 302 and the first masking layer 1204. In some embodiments, the second isolation layer 304 may comprise a same or different material than the first isolation layer 302. In some embodiments, the second isolation layer 304 may comprise, for example, an oxide, such as aluminum oxide or silicon dioxide.

[0047] The second isolation layer 304 may have a fourth thickness t.sub.4, and in some embodiments, the fourth thickness t.sub.4 may be in a range of between, for example, approximately 200 angstroms and approximately 800 angstroms. In some other embodiments, the fourth thickness t.sub.4 may be in a range of between, for example, approximately 800 angstroms and approximately 1000 angstroms. In some embodiments, the fourth thickness t.sub.4 is less than, greater than, or about equal to the first thickness t.sub.1 of the first isolation layer 302. For example, in the cross-sectional view 1300, the fourth thickness t.sub.4 is greater than the first thickness t.sub.1. The second isolation layer 304 may be formed using a deposition process (e.g., physical vapor deposition (PVD), chemical vapor deposition (CVD), PE-CVD, atomic layer deposition (ALD), sputtering, etc.). The second isolation layer 304 may directly contact the first isolation layer 302. In some embodiments, if the first and second isolation layers 302, 304 comprise a same material, an interface between the first and second isolation layers 302, 304 may not be distinguishable.

[0048] As shown in the cross-sectional view 1400 of FIG. 14, a second conformal masking layer 1402 may be formed over the second isolation layer 304. In some embodiments, the second conformal masking layer 1402 may comprise the same material and may be deposited using the same deposition process as the first conformal masking layer (1004 of FIG. 10). Further, in some embodiments, a second conformal oxide layer 1404 may be deposited over the second conformal masking layer 1402. In some embodiments, the second conformal oxide layer 1404 may comprise the same material and may be deposited using the same deposition process as the first conformal oxide layer (1006 of FIG. 10).

[0049] As shown in the cross-sectional view 1500 of FIG. 15, the second conformal oxide layer (1404 of FIG. 14) and the second conformal masking layer (1402 of FIG. 14) may be patterned such that a second masking layer 1502 and a second oxide layer 1504 directly overlie the second reflector electrode 102b without directly overlying the first or third reflector electrodes 102a, 102c. The patterning of the second oxide layer 1504 and the second masking layer 1502 may be conducted using the same or similar steps are presented in FIGS. 11 and 12 regarding the formation of the first oxide layer 1106 arranged over the first masking layer 1204. Further, in some embodiments, the second oxide layer 1504 and the second masking layer 1502 completely overlie the second reflector electrode 102b, and thus, the second oxide layer 1504 and the second masking layer 1502 may each have a width that is about equal to or greater than the second width w.sub.2 of the second reflector electrode 102b. Further, similar to the first isolation layer 302 during the formation of the first masking layer 1204, the second isolation layer 304 remains substantially unchanged during the formation of the second masking layer 1502 because the second masking layer 1502 prevents the passage of ions and is patterned using a wet etching process, in some embodiments.

[0050] As shown in the cross-sectional view 1600 of FIG. 16, a third isolation layer 306 may be formed over the second isolation layer 304 and the second masking layer 1502. In some embodiments, the third isolation layer 306 may comprise a same or different material than the first isolation layer 302 and/or the second isolation layer 304. In some embodiments, the third isolation layer 306 may comprise, for example, an oxide, such as aluminum oxide or silicon dioxide.

[0051] The third isolation layer 306 may have a fifth thickness t.sub.5, and in some embodiments, the fifth thickness t.sub.5 may be in a range of between, for example, approximately 200 angstroms and approximately 1100 angstroms. In some other embodiments, the fifth thickness t.sub.5 may be in a range of between, for example, approximately 1100 angstroms and approximately 1300 angstroms. In some embodiments, the fifth thickness t.sub.5 is less than, greater than, or about equal to the fourth thickness t.sub.4 of the second isolation layer 304. For example, in the cross-sectional view 1600, the fifth thickness t.sub.5 is about equal to the fourth thickness t.sub.4. The third isolation layer 306 may be formed using a deposition process (e.g., physical vapor deposition (PVD), chemical vapor deposition (CVD), PE-CVD, atomic layer deposition (ALD), sputtering, etc.). The third isolation layer 306 may directly contact the second isolation layer 304. In some embodiments, if the second and third isolation layers 304, 306 comprise a same material, an interface between the second and third isolation layers 304, 306 may not be distinguishable.

[0052] As shown in the cross-sectional view 1700 of FIG. 17, a third conformal masking layer 1702 may be formed over the third isolation layer 306. In some embodiments, the third conformal masking layer 1702 may comprise the same material and may be deposited using the same deposition process as the first conformal masking layer (1004 of FIG. 10). Further, in some embodiments, a third conformal oxide layer 1704 may be deposited over the third conformal masking layer 1702. In some embodiments, the third conformal oxide layer 1704 may comprise the same material and may be deposited using the same deposition process as the first conformal oxide layer (1006 of FIG. 10).

[0053] As shown in the cross-sectional view 1800 of FIG. 18, the third conformal oxide layer (1704 of FIG. 17) and the third conformal masking layer (1702 of FIG. 17) may be patterned such that a third masking layer 1802 and a third oxide layer 1804 directly overlie the third reflector electrode 102c without directly overlying the second or third reflector electrodes 102b, 102c. The patterning of the third oxide layer 1804 and the third masking layer 1802 may be conducted using the same or similar steps are presented in FIGS. 11 and 12 regarding the formation of the first oxide layer 1106 arranged over the first masking layer 1204. Further, in some embodiments, the third oxide layer 1804 and the third masking layer 1802 completely overlie the third reflector electrode 102c, and thus, the third oxide layer 1804 and the third masking layer 1802 may each have a width that is about equal to or greater than the third width w.sub.3 of the third reflector electrode 102c. Further, similar to the first isolation layer 302 during the formation of the first masking layer 1204, the third isolation layer 306 remains substantially unchanged during the formation of the third masking layer 1802 because the third masking layer 1802 prevents the passage of ions and is patterned using a wet etching process, in some embodiments.

[0054] As shown in the cross-sectional views 1900A-1900C of FIGS. 19A-19C, a first removal process 1902 is performed to remove portions of the first, second, and third isolation layers 302, 304, 306 uncovered by the first, second, and third masking layers 1204, 1502, 1802. The cross-sectional views 1900A, 1900B, and 1900C of FIGS. 19A, 19B, and 19C illustrate the first removal process 1902 respectively at a first time, a second time, and a third time, where the second time is after the first time and the third time is after the second time.

[0055] During the first time, as illustrated in the cross-sectional view 1900A of FIG. 19A, the third isolation layer 306 that is uncovered by the third masking layer 1802 is removed. In some embodiments, the first removal process 1902 uses a vertical etch. Thus, in some embodiments, the first removal process 1902 is an etching process that utilizes a dry etchant. The dry etchant does not remove the first, second, or third masking layers 1204, 1502, 1802. In some embodiments, the first oxide layer 1106, the second oxide layer 1504, and the third oxide layer 1804 comprise a same material as the first, second, and/or third isolation layers 302, 304, 306. In some embodiments, the first removal process 1902 may partially remove the first, second, and third oxide layers 1106, 1504, 1804 such that after the first removal process 1902, the first, second, and third oxide layers 1106, 1504, 1804 may have a higher average surface roughness than before the first removal process 1902. In other embodiments (not illustrated), the first removal process 1902 may completely remove the first oxide layer 1106, the second oxide layer 1504, and the third oxide layer 1804. Nevertheless, the first, second, and third masking layers 1204, 1502, 1802 cover and protect the underlying first, second, and/or third isolation layers 302, 304, 306 from ions during the dry etch.

[0056] During the second time, as illustrated in the cross-sectional view 1900B of FIG. 19B, the first removal process 1902 begins to remove portions of the second isolation layer 304 uncovered by the second and third masking layers 1502, 1802. In some embodiments, the same dry etchant is used during the first removal process 1902. In other embodiments, such as if the first, second, and/or third isolation layers 302, 304, 306 comprise different materials, different dry etchants may be used to effectively remove each of the first, second, and third isolation layers 302, 304, 306 that are uncovered or that do not directly underlie the first, second, or third masking layers 1204, 1502, 1802. For example, in some embodiments, for an oxide-based first, second and/or third isolation layer 302, 304, 306, a carbon fluoride based dry etchant may be used, whereas in some other embodiments, for a nitride-based first, second, and/or third isolation layer 302, 304, 306, a carbon hydrogen fluoride based dry etchant may be used. It will be appreciated that other dry etchants are also within the scope of the disclosure.

[0057] During the third time, as illustrated in the cross-sectional view 1900C of FIG. 19C, the first removal process 1902 finishes and removes portions of the first, second, and third isolation layers 302, 304, 306 that do not directly underlie the first, second, or third masking layers 1204, 1502, 1802. The first removal process 1902 may stop at the second dielectric layer 604 or at the first barrier structures 104. Because the first, second, and third masking layers 1204, 1502, 1802 completely overlie the first, second, and third reflector electrodes 102a, 102b, 102c, respectively, the first, second, and third reflector electrodes 102a, 102b, 102c do not get damaged by the first removal process 1902 and therefore maintain the first, second, and third average surface roughnesses, respectively. Thus, patterning of the first, second, and third isolation layers 302, 304, 306 does not damage the first, second, and third reflector electrodes 102a, 102b, 102c and optical properties of the first, second, and third reflector electrodes 102a, 102b, 102c are maintained.

[0058] As shown in the cross-sectional view 2000 of FIG. 20, a second removal process may be performed to remove the first, second, and third masking layers (1204, 1502, 1802 of FIG. 19C). Further, in some embodiments, the second removal process also remove the first oxide layer (1106 of FIG. 19C), the second oxide layer (1504 of FIG. 19C), and the third oxide layer (1804 of FIG. 19C). The second removal process, in some embodiments, may comprise, for example, a dry etching process to remove the first oxide layer (1106 of FIG. 19C), the second oxide layer (1504 of FIG. 19C), and the third oxide layer (1804 of FIG. 19C) followed by a wet etching process to remove the first, second, and third masking layers (1204, 1502, 1802 of FIG. 19C). In other embodiments, where the first oxide layer (1106 of FIG. 19C), the second oxide layer (1504 of FIG. 19C), and the third oxide layer (1804 of FIG. 19C) were omitted or where the first oxide layer (1106 of FIG. 19C), the second oxide layer (1504 of FIG. 19C), and the third oxide layer (1804 of FIG. 19C) were removed during the first removal process (1902 of FIGS. 19A, 19B, 19C), for example, the second removal process may only comprise a wet etching process to remove the first, second, and third masking layers (1204, 1502, 1802 of FIG. 19C).

[0059] Wet etching is used in place of dry etching to prevent damage to the first, second, and third isolation layers 302-306 and the first, second, and third reflector electrodes 102a-102c. If dry etchants were employed, ions from the dry etching may pass through the first, second, and third isolation layers 302-306 to upper surfaces respectively of the first, second, and third reflector electrodes 102a-102c. This would damage the crystalline structure of the first, second, and third isolation layers 302-306 and would increase upper surface roughness of the first, second, and third reflector electrodes 102a-102c. The crystalline damage and/or increased surface damage would, in turn, increase light scattering and degrade reliability of the display device.

[0060] The first, second, and third isolation layers 302, 304, 306 form an isolation structure 106 coupled to the control circuitry 120. A first portion 106a of the isolation structure 106 comprises the first isolation layer 302. The first portion 106a of the isolation structure 106 has the first thickness t.sub.1. A second portion 106b of the isolation 106 structure comprises portions respectively of the first isolation layer 302 and the second isolation layer 304 that directly overlie the second reflector electrode 102b. The first isolation layer 302 of the second portion 106b of the isolation structure directly contacts the second reflector electrode 102b. The second portion 106b of the isolation structure 106 has a second thickness t.sub.2 that in some embodiments, is in a range of between, for example, approximately 300 angstroms and approximately 1300 angstroms. The second thickness t.sub.2 is greater than the first thickness t.sub.1, such that an upper surface of the first portion 106a of the isolation structure 106 is below an upper surface of the second portion 106b of the isolation structure 106. The second thickness t.sub.2 is equal a sum of the first thickness t.sub.1 and the fourth thickness t.sub.4. A third portion 106c of the isolation structure 106 directly overlies the third reflector electrode 102c and comprises portions respectively of the first isolation layer 302, the second isolation layer 304, and the third isolation layer 306. The first isolation layer 302 of the third portion 106c of the isolation structure directly contacts the third reflector electrode 102c. The third portion 106c of the isolation structure 106 has a third thickness t.sub.3 that, in some embodiments, is in a range of between, for example, approximately 400 angstroms and approximately 1500 angstroms. The third thickness t.sub.3 is equal to a sum of the first thickness t.sub.1, the second thickness t.sub.2, and the third thickness t.sub.3. The third thickness t.sub.3 may be greater than the second thickness t.sub.2, such that the upper surface of the second portion 106b of the isolation structure 106 is below an upper surface of the third portion 106c of the isolation structure 106. The first, second, and third portions 106a, 106b, 106c of the isolation structure 106 are completely laterally spaced apart from one another, allowing for optical isolation.

[0061] As shown in the cross-sectional view 2100 of FIG. 21, first, second, and third via structures 108a, 108b, 108c are formed over and extending through the first, second, and third portions 106a, 106b, 106c of the interconnect structure, respectively, to contact the first, second, and third reflector electrodes 102a, 102b, 102c, respectively. In some embodiments, the via structures (108a, 108b, 108c) may comprise tantalum, titanium, or some other conductive material.

[0062] Further, in some embodiments, first, second, and third transparent electrodes 112a, 112b, 112c may be formed over the first, second, and third portions 106a, 106b, 106c of the isolation structure 106, respectively. The first transparent electrode 112a may directly contact the first portion 106a of the isolation structure 106. The second transparent electrode 112b may directly contact the second portion 106b of the isolation structure 106. The third transparent electrode 112c may directly contact the third portion 106c of the isolation structure 106. In some embodiments, the transparent electrodes (112a, 112b, 112c) comprise an electrically conductive material that is also optically transparent, such as, for example, indium tin oxide (ITO), fluorine tin oxide (FTO), or the like. In some embodiments, each of the transparent electrodes (112a, 112b, 112c) may have a thickness that is, for example, in a range of between approximately 500 angstroms and approximately 3000 angstroms.

[0063] In some embodiments, a first optical emitter structure 110a, a second optical emitter structure 110b, and a third optical emitter structure 110c may be respectively formed over the first transparent electrode 112a, the second transparent electrode 112b, and the third transparent electrode 112c. In some embodiments, the optical emitter structures (110a, 110b, 110c) may be or comprise an organic light emitting diode (OLED) or some other suitable light generating device. In some embodiments, each of the optical emitter structures (110a, 110b, 110c) may have a thickness in the range of between, for example, approximately 500 angstroms and approximately 3000 angstroms.

[0064] In some embodiments, second barrier structures 114 are formed to separate the transparent electrodes (112a, 112b, 112c) and the optical emitter structures (110a, 110b, 110c) to define a first pixel region 101a, a second pixel region 101b, and a third pixel region 101c. Further, the second barrier structures 114 may completely separate the first, second, and third portions 106a, 106b, 106c of the isolation structure 106. It will be appreciated that the display device may comprise an array of pixel regions, and may comprise more than the first, second, and third pixel regions 101a, 101b, 101c. Some of the second barrier structures 114 may directly overlie the first barrier structures 104, and the second barrier structures 114 may comprise a dielectric material to electrically and optically isolate the pixel regions (101a, 101b, 101c) from one another. For example, the second barrier structures 114 may comprise a nitride (e.g., silicon nitride, silicon oxynitride), an oxide (e.g., silicon oxide), or the like. For example, in some other embodiments, the second barrier structures 114 may comprise a multi-layer film stack of silicon nitride and silicon oxide. Further, in some embodiments, the second barrier structures 114 may comprise a same material as the isolation structure 106, the first barrier structures 104, and/or the interconnect dielectric structure 132. In other embodiments, the second barrier structures 114 may comprise a different material as the isolation structure 106, the first barrier structures 104, and/or the interconnect dielectric structure 132.

[0065] It will be appreciated that the via structures (108a, 108b, 108c), the transparent electrodes (112a, 112b, 112c), the optical emitter structures (110a, 110b, 110c), and the second barrier structures 114 may each be formed through various steps comprising deposition processes (e.g., physical vapor deposition (PVD), chemical vapor deposition (CVD), PE-CVD, atomic layer deposition (ALD), sputtering, etc.), removal processes (e.g., wet etching, dry etching, chemical mechanical planarization (CMP), etc.), and/or patterning processes (e.g., photolithography/etching).

[0066] Thus, the display device comprises control circuitry 120 to selectively operate the first, second, and third pixel regions 101a, 101b, 101c. Because the first, second, and third reflector electrodes 102a, 102b, 102c are protected from the first removal process (1902 of FIGS. 19A, 19B, 19C) by the first, second, and third masking layers 1204, 1502, 1802, respectively, each of the pixel regions (101a, 101b, 101c) may be selectively operated by the control circuitry 120 to reliably emit colored light depending on the thicknesses (t.sub.1, t.sub.2, t.sub.3) and/or materials of each portion (106a, 106b, 106c) of the isolation structure (106).

[0067] FIG. 22 illustrates a flow diagram of some embodiments of a method 2200 corresponding to FIGS. 5-18, 19A-19C, 20, and 21.

[0068] While method 2200 is illustrated and described below as a series of acts or events, it will be appreciated that the illustrated ordering of such acts or events are not to be interpreted in a limiting sense. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein. In addition, not all illustrated acts may be required to implement one or more aspects or embodiments of the description herein. Further, one or more of the acts depicted herein may be carried out in one or more separate acts and/or phases.

[0069] At act 2202, a first reflector electrode and a second reflector electrode are formed over an interconnect structure. FIGS. 7-9 illustrate cross-sectional views 700-900 of some embodiments corresponding to act 2202.

[0070] At act 2204, a first isolation layer is deposited over the first and second reflector electrodes. FIG. 10 illustrates cross-sectional view 1000 of some embodiments corresponding to act 2204.

[0071] At act 2206, a first masking layer is formed over the first reflector electrode such that the first masking layer directly overlies the first reflector electrode but not the second reflector electrode. FIGS. 10-12 illustrate cross-sectional views 1000-1200 of some embodiments corresponding to act 2206.

[0072] At act 2208, a second isolation layer is deposited over the first isolation layer and over the first masking layer. FIG. 13 illustrates cross-sectional view 1300 of some embodiments corresponding to act 2208.

[0073] At act 2210, a second masking layer is formed over the second isolation layer such that the second masking layer directly overlies the second reflector electrode but not the first reflector electrode. FIGS. 14 and 15 illustrate cross-sectional views 1400 and 1500, respectively, of some embodiments corresponding to act 1910.

[0074] At act 2212, a first removal process is performed to remove portions of the first and second isolation layers that do not directly underlie the first or second masking layers. FIGS. 19A, 19B, and 19C illustrate cross-sectional views 1900A, 1900B, and 1900C, respectively, of some embodiments corresponding to act 2212.

[0075] At act 2214, a second removal process is performed to remove the first and second masking layers. FIG. 20 illustrates cross-sectional view 2000 of some embodiments corresponding to act 2214.

[0076] Therefore, the present disclosure relates to a method of forming an isolation structure that prevents damage to upper surfaces of an underlying reflector electrode structure to improve reliability of a display device.

[0077] Accordingly, in some embodiments, the present disclosure relates to a display device comprising: a first reflector electrode; a second reflector electrode that is separated from the first reflector electrode; an isolation structure overlying the first and second reflector electrodes, the isolation structure comprising: a first portion that overlies the first reflector electrode and has a first thickness, and a second portion that overlies the second reflector electrode, has a second thickness greater than the first thickness, and is separated from the first portion of the isolation structure; and a first optical emitter structure and a second optical emitter structure respectively overlying the first and second portions of the isolation structure.

[0078] In other embodiments, the present disclosure relates to a display device comprising: a first reflector electrode and a second reflector electrode over an interconnect structure; a first isolation layer comprising a pair of segments that are spaced from each other and that respectively overlie the first and second reflector electrodes; a second isolation layer overlying the first isolation layer and the second reflector electrode, but not the first reflector electrode; a first optical emitter structure overlying the first isolation layer and the first reflector electrode and a second optical emitter structure overlying the second isolation layer and the second reflector electrode; and a first conductive structure and a second conductive structure respectively extending from the first reflector electrode to the first optical emitter structure and from the second reflector electrode to the second optical emitter structure, wherein the first conductive structure extends through the first isolation layer, and wherein the second conductive structure extends through the first and second isolation layers.

[0079] In yet other embodiments, the present disclosure relates to a method of forming a display device, comprising: forming a first reflector electrode and a second reflector electrode over an interconnect structure, wherein the first reflector electrode is laterally separated from the second reflector electrode; depositing a first isolation layer over the first and second reflector electrodes; forming a first masking layer directly overlying the first reflector electrode; depositing a second isolation layer over the first isolation layer and over the first masking layer; forming a second masking layer over the second isolation layer and directly overlying the second reflector electrode; performing a first removal process to remove portions of the first and second isolation layers that do not directly underlie the first or second masking layers; and performing a second removal process to remove the first and second masking layers.

[0080] The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.