Method for Independent Real and Reactive Power Flow Control Using Locally Available Parameters

Abstract

A method for independent real and reactive power flow control without sensing receiving end voltage in a power flow controller (PFC) includes calculating a first reference phase angle, calculating a first reference voltage, modifying the first reference phase angle calculated using a first phasor modifier, calculating a first reference current for a first terminal, calculating a second reference phase angle for current through the first terminal, calculating a second reference voltage across a second CMI by subtracting voltages at the first terminal and a second terminal, and controlling the first CMI and the second CMI for controlling the power flow through the PFC.

Claims

1. A method for independent real and reactive power flow control without sensing voltages in a power flow controller (PFC) provided between a first terminal and a second terminal of a transmission line, said method comprising the steps of: connecting a first cascaded multilevel inverter (CMI) for the PFC between the second terminal and a reference potential and a second CMI for the PFC in series between the first terminal and the second terminal; calculating a first reference phase angle based on a difference between a reference active power and a sensed active power being delivered from the second terminal to a receiving end; calculating a first reference voltage based on a difference between a reference reactive power and a sensed reactive power being delivered from the second terminal to the receiving end; modifying the first reference phase angle calculated using a first phasor modifier in order to provide for a power loss encountered due to operation of the first CMI and the second CMI; calculating a first reference current for the first terminal based on a difference between the reference active power and the sensed active power being delivered from the first terminal; calculating a second reference phase angle for current through the first terminal in order to ensure that an average active power and an average reactive power into and out of the first CMI and the second CMI is zero; calculating a second reference voltage across the second CMI by subtracting voltages at the first terminal and the second terminal; and controlling the first CMI using the calculated first reference voltage and controlling the second CMI using the calculated second reference voltage for controlling the power flow through the PFC.

2. A method as set forth in claim 1 including the step of providing a first reference phase angle calculator and calculating the first reference phase angle with the first reference phase angle calculator.

3. A method as set forth in claim 2 including the step of providing a second reference phase angle calculator and calculating the second reference phase angle with the second reference phase angle calculator.

4. A method as set forth in claim 1 including the step of providing a first sensed power calculator and calculating a first sensed power with the first sensed power calculator.

5. A method as set forth in claim 4 including the step of providing a second sensed power calculator and calculating a second sensed power with the second sensed power calculator.

6. A method as set forth in claim 1 including the step of providing a first reference voltage calculator and calculating a first reference voltage with the first reference voltage calculator.

7. A method as set forth in claim 6 including the step of providing a second reference voltage calculator and calculating a second reference voltage with the second reference voltage calculator.

8. A method as set forth in claim 1 including the steps of providing a first feed forward calculator and calculating a first steady state voltage reference with the first feed forward calculator.

9. A method as set forth in claim 8 including the steps of providing a second feed forward calculator and calculating a second steady state voltage reference with the second feed forward calculator.

10. A method as set forth in claim 1 including the steps of providing a synchronization module and synchronizing individual gate signals with a reference signal with the synchronization module.

11. A method as set forth in claim 10 including the steps of providing a gate signal generation module and generating gate pulses from the gate signals with the gate signal generation module.

12. A method as set forth in claim 1 wherein the PFC is a unified transformer-less power flow controller.

13. A method for independent real and reactive power flow control without sensing voltages in a unified transformer-less power flow controller (PFC) provided between a first terminal and a second terminal of a transmission line, said method comprising the steps of: connecting a first cascaded multilevel inverter (CMI) for the PFC between the second terminal and a reference potential and a second CMI for the PFC in series between the first terminal and the second terminal; calculating a first reference phase angle based on a difference between a reference active power and a sensed active power being delivered from the second terminal to a receiving end; calculating a first reference voltage based on a difference between a reference reactive power and a sensed reactive power being delivered from the second terminal to the receiving end; modifying the first reference phase angle calculated using a first phasor modifier in order to provide for a power loss encountered due to operation of the first CMI and the second CMI; calculating a first reference current for the first terminal based on a difference between the reference active power and the sensed active power being delivered from the first terminal; calculating a second reference phase angle for current through the first terminal in order to ensure that an average active power and an average reactive power into and out of the first CMI and the second CMI is zero; calculating a second reference voltage across the second CMI by subtracting voltages at the first terminal and the second terminal; providing a gate signal generation module and generating gate pulses from gate signals with the gate signal generation module; providing a synchronization module and synchronizing individual gate signals with a reference signal with the synchronization module; and controlling the first CMI using the calculated first reference voltage and controlling the second CMI using the calculated second reference voltage for controlling the power flow through the PFC.

14. A method as set forth in claim 13 including the step of providing a first reference phase angle calculator and calculating the first reference phase angle with the first reference phase angle calculator.

15. A method as set forth in claim 14 including the step of providing a second reference phase angle calculator and calculating the second reference phase angle with the second reference phase angle calculator.

16. A method as set forth in claim 13 including the step of providing a first sensed power calculator and calculating a first sensed power with the first sensed power calculator.

17. A method as set forth in claim 16 including the step of providing a second sensed power calculator and calculating a second sensed power with the second sensed power calculator.

18. A method as set forth in claim 13 including the step of providing a first reference voltage calculator and calculating the first reference voltage with the first reference voltage calculator.

19. A method as set forth in claim 18 including the step of providing a second reference voltage calculator and calculating the second reference voltage with the second reference voltage calculator.

20. A method as set forth in claim 13 including the steps of providing a first feed forward calculator and calculating a first steady state voltage reference with the first feed forward calculator.

21. A method as set forth in claim 20 including the steps of providing a second feed forward calculator and calculating a second steady state voltage reference with the second feed forward calculator.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0018] FIG. 1A is a schematic single-line diagram of a transmission line according to the principles of the prior art.

[0019] FIG. 1B is a schematic single-line diagram of an example of a unified power flow controller (UPFC) according to the principles of the prior art used with the transmission line of FIG. 1A.

[0020] FIG. 2 is a schematic of a single phase equivalent circuit of the transformer-less UPFC of FIG. 1B.

[0021] FIG. 3 is a diagrammatic view of a phase diagram representing the functioning of the single phase equivalent circuit of FIG. 2.

[0022] FIG. 4A is a diagrammatic view of an overall block diagram of a control module to control CMI-1, showing all the relevant blocks used in the transformer-less UPFC of FIG. 1B.

[0023] FIG. 4B is a diagrammatic view of an overall block diagram for providing gating signals CMI-2.

DESCRIPTION OF THE PREFERRED EMBODIMENT(S)

[0024] A transformer-less unified power flow controller according to the prior art includes cascade multilevel inverters (CMIs) configured such that transformers may be eliminated entirely. They may be referred to more broadly as power control devices. These power control devices may be used as energy routers and may be easily integrated over existing transmission lines to maximize energy transmission. For example only, the power control devices can be used to regulate and control power flow over AC transmission lines or distribution lines. It should be appreciated that, in a mesh AC network, transformer-less UPFCs can be used to prevent loops of power, which decrease efficiency and can result in detrimental feedback loops. It should also be appreciated that power control devices may include or be configured other than as a transformer-less unified power flow controller.

[0025] Referring to FIG. 1A, examples of UPFC placement along a power line are presented. As illustrated, a power line 200 is connected between a sending end 204 and a receiving end 208. The power line 200 has an intrinsic impedance, which is represented graphically as an inductor. Along the transmission line 200 are pairs of points a1/a2 212, b1/b2 216, and c1/c2 220. The transformer-less unified power flow controllers may be connected between terminals a1 and a2 212, between terminals b1 and b2 216, and/or between terminals d and c2 220.

[0026] Referring to FIG. 1B, an example implementation of a transformer-less unified power flow controller 228 is shown. As illustrated, first and second terminals of the UPFC 228 are labeled 1 and 2, respectively. For example, the UPFC 228 of FIG. 1B may be connected between points al and a2 212 of FIG. 1A, where al corresponds to terminal 1 of FIG. 1B and a2 corresponds to terminal 2 of FIG. 1B. In various implementations, the UPFC 228 may be reversible, such that al will correspond to terminal 2 of FIG. 1B, while a2 corresponds to terminal 1 of FIG. 1B. The UPFC 228 of FIG. 1B may be bidirectional such that either configuration can be used. The UPFC 228 is formed by a first cascaded multilevel inverter (CMI) 230 connected between terminal 2 and a reference potential, such as ground, and a second CMI 234 connected in series between terminal 1 and terminal 2. Each of the CMIs 230 and 234 can be formed using a series of bridge modules. For example only, the first CMI 230 can be formed from a series chain of bridge modules M1 238-1, M2 238-2, . . . Mn 238-n (collectively, bridge modules 238). Similarly, the second CMI 234 may be formed from M bridge modules M1 242-1, M2 242-2, . . . Mn 242-n (collectively, bridge modules 242).

[0027] The bridge modules 242 used in the second CMI 234 may be different than some or all of the bridge modules 238 used in the first CMI 230. In addition, the number of bridge modules 242 in the second CMI 234 may be different than the number of bridge modules 238 in the first CMI 230. It should be appreciated that the bridge modules for a single CMI may all be of one type or may be of different types. It should also be appreciated that the first CMI 230, second CMI 234, and bridge modules 238 and 242 are similar to those disclosed in PCT International Publication No. WO 2013/12660, the disclosure of which in its entirety is hereby incorporated by reference.

[0028] Referring to FIG. 2, a single phase equivalent circuit of the transformer-less UPFC 228 of FIG. 1B is shown. The equivalent circuit has been obtained by considering the CMIs 230 and 234 as equivalent variable AC voltage sources. The resistance of transmission lines has been neglected in the entire analysis. The glossary used in FIG. 2 is as follows:

[0029] V.sub.So represents the original sending end voltage;

[0030] V.sub.s represents the magnitude of shunt inverter voltage. This is also the effective sending end voltage;

[0031] V.sub.c represents the magnitude of series inverter voltage;

[0032] V.sub.R represents the magnitude of receiving end voltage;

[0033] .sub.s1 .sub.o1 .sub.S and .sub.R represent the phase angles of their respective voltages;

[0034] X.sub.S and X.sub.R represent the lumped sending end and receiving end impedance, respectively;

[0035] i.sub.C represents the instantaneous current through series inverter or second CMI 234; and

[0036] i.sub.S represents the instantaneous current through shunt inverter or first CMI 230 and i.sub.R represents instantaneous receiving end current.

[0037] Let P* and Q* be the required real and reactive power to be dispatched from the modified sending end (V.sub.s). The aim of the control is to vary voltage magnitudes V.sub.c1 V.sub.S and angles .sub.c1 .sub.s in order to control P* and Q*. This is subject to the following constraints:

[0038] voltage sources represented as phasors, {right arrow over (V)}.sub.s and {right arrow over (V)}.sub.c, can only supply or absorb reactive power;

[0039] control must not involve sensing of receiving end voltage as it may be far away from the point of installation; and

[0040] the controller must be immune against variation of line impedances and sending and receiving end voltages.

[0041] It should be appreciated that the circuit of FIG. 2 is similar to that disclosed in the published article by Gunasekaran, D.; Shao Zhang; Shuitao Yang; Fang Zheng Peng, Independent real and reactive power flow control without sensing receiving end voltage in transformer-less unified power flow controller, Energy Conversion Congress and Exposition (ECCE), 2014 IEEE, vol. 978-1-4799-5776-7, no. 14, pp. 730-735, 18 Sep. 2014, the disclosure of which is in its entirety hereby incorporated by reference.

[0042] Referring to FIG. 3, a phasor diagram representing the functioning and a valid operating point is shown for the transformer-less UPFC 228 of FIG. 1B or the single phase equivalent circuit of FIG. 2. The voltage drop across X.sub.S is neglected in the phasor diagram.

[0043] FIG.4A illustrates the overall block diagram that controls the first CMI (CMI-1) 230. FIG. 4B illustrates the overall block diagram that provides gating signals to the second CMI (CMI-2) 234. Referring to FIG. 4A, based on the above discussion, the desired ideal control block diagram is shown. The reference active power, P* is compared against the sensed active Power, P.sub.sense which is determined using block 252. Block 253 senses the active power flowing out of terminal 2. The difference between the reference active power and the sensed active power is the input to block 252 which calculates one of the components of reference phase angle. The sum of outputs from blocks 250 through 252 provide the reference phase angle, *.sub.Vs for CMI-1. The reference reactive power, Q* is compared against the sensed reactive power, Q.sub.sense which is calculated using block 256. The output of the difference between Q* and Q.sub.sense serves as input to block 255 that generates one component of the voltage magnitude reference, V*.sub.s. The feed-forward component of the reference voltage magnitude V.sub.sff is generated using block 254. The reference phase *.sub.Vs and reference voltage magnitude, V*.sub.s are then sent to block 258 which generates the gate pulses for CMI-1. The grid synchronization signals are sent from the synchronization module 258.

[0044] FIG. 4B illustrates the overall control block diagram that leads to the gate pulses being provided for CMI-2. The reference active power P* is the same as the reference active power being dispatched from terminal 2. This is compared against the sensed active power, P.sub.s1. The difference between P* and P.sub.s1 is fed to block 259 which calculates one component of the reference current magnitude, I*.sub.c. The feed-forward component of is calculated using block 258. The reference current magnitude, I*.sub.c is compared against the sensed current I.sub.c and the difference between the two parameters is sent as one of the inputs to block 265. Block 261 receives reference current magnitude I*.sub.c, sensed current phasor, {right arrow over (I.sub.R)} and sensed voltage phasor, {right arrow over (V)}.sub.S as inputs in order to determine its output. Block 263 takes the difference between that output and the sensed current phase,I.sub.c, as the input and determines the reference current phase I*.sub.c. This reference is then modified by means of block 264 in order to account for power loss encountered during the operation of CMI-2.

[0045] The reference current magnitude and reference phase are provided as inputs to block 265 that generates an input to block 266. The output of block 266 provides reference voltage phasor, {right arrow over (V*.sub.c)}, to the gate signal generation module 267. This block provides the gate pulses to CMI-2 using the signals from the grid synchronization module 258.

Reference Phase Calculator 1 (252)

[0046] The reference phase calculator 1, block 252 calculates the reference phase for the voltage phasor to be generated by CMI-1. The reference power to be dispatched from terminal 2 is given as P*. The sensed active power flowing out or into terminal 2 to or from the power line is termed as P.sub.sense. From the basic power system equations, an expression linking phase angle and power flow can easily be derived. An example implementation of the block 252 is using a Proportional plus integral controller. The other example implementations may consist of proportional plus resonant controllers or any other implementation as demanded by the required dynamic response.

Sensed Power Calculator 1 (253)

[0047] The voltage phasor at terminal 2, {right arrow over (V.sub.S)} is sensed along with the current phasor through the power line, {right arrow over (I.sub.R)}. In one example implementation, the polar expression, P.sub.sense=Re({right arrow over (V.sub.s)}.{right arrow over (I*.sub.R)}) can be solved in order to determine the sensed active power flowing into or out of terminal 2, where {right arrow over (I*.sub.R))} represents the conjugate of current phasor, {right arrow over (I.sub.R)}.

Feed-Forward Calculator 1 (251)

[0048] The aim of block 251 is to provide a pre-calculated steady state phase angle V.sub.sff based on nominal values for receiving end and sending end voltages and impedances. This block may or may not be a part of the overall system. It should be appreciated that the overall block diagram can also be designed to function without the need for feed-forward block 251 without changing the rest of the blocks.

Phase Modifier 1 (250)

[0049] The role of block 250 is to provide a corrective term to the phase reference generated by blocks 251 and 252. An example implementation involves sensing the average DC voltage of all the CMI modules of CMI-1, V.sub.DC1 and comparing it with a nominal reference, V*.sub.DC1. The output of block 250 provides the correction term to the phase angle reference, *.sub.Vs. This is to account for the real power loss encountered due to operation of the CMI. It should be appreciated that these are typically the conduction and switching losses of the device, but, it can be designed to involve other losses in the system.

Reference voltage calculator 1 (255)

[0050] The reference voltage calculator 1, block 255 calculates the reference voltage magnitude for the voltage phasor to be generated by CMI-1. The reference reactive power to be dispatched from terminal 2 is given as Q*. The sensed reactive power flowing out of terminal 2 onto the power line is termed as Q.sub.sense. From the basic power system equations, a relation between Q.sub.sense and voltage magnitude can easily be derived. The aim of block 255 is to provide an output that drives the input to zero. At steady state, Q.sub.sense must equal Q*. An example implementation of the block 252 is using a Proportional plus integral controller. The usage of this block is optional if tight reactive power control is not necessary. This may be the case in an example of the power control device interconnecting two strong synchronous grids.

[0051] The voltage phasor at terminal 2, {right arrow over (V.sub.S)} is sensed along with the current phasor through the power line, 4. In one example implementation, the polar expression, Q.sub.sense=Im({right arrow over (V.sub.s)}* {right arrow over (I*.sub.R)}) can be solved in order to determine the reactive power flowing out or into terminal 2 from the power line. Where Q.sub.sense=Im({right arrow over (V.sub.s)}* {right arrow over (I*.sub.R)}) represents the conjugate of the phasor, {right arrow over (I.sub.R)}.

Feed-Forward Calculator 2 (254)

[0052] The aim of block 254 is to provide a pre-calculated steady state voltage magnitude reference, V.sub.sff based on nominal values for receiving end and sending end voltages and impedances. In an example implementation, block 254 can be designed by using the DQ transformation equations based on nominal values for the impedance and end voltages in the system.

[0053] For reference only, the equations containing feed-forward terms for {right arrow over (V.sub.S)} in D-Q domain, V.sub.sd,V.sub.sq are described below:

[00001]$Q^{*}.Math..Math..Math.L_{R-}.Math.{\left\{\frac{P^{*}.Math..Math..Math.L_R}{V_{\mathrm{Rd}}}\right\}}^2+\frac{P^{*}.Math..Math..Math.L_R.Math.V_{\mathrm{Rq}}}{V_{\mathrm{Rd}}}-V_{\mathrm{sd}}^2.Math.\left\{1+\frac{V_{\mathrm{Rq}}^2}{V_{\mathrm{Rd}}^2}\right\}-V_{\mathrm{sd}}.Math.\left\{\frac{2.Math.P^{*}.Math..Math..Math.L_R.Math.V_{\mathrm{Rq}}}{V_{\mathrm{Rd}}^2}-\frac{V_{\mathrm{Rq}}^2}{V_{\mathrm{Rd}}^2}-V_{\mathrm{Rd}}\right\}=0$$.Math.V_{\mathrm{Sq}}=\frac{P^{*}.Math..Math..Math.L_R+V_{\mathrm{Sd}}.Math.V_{\mathrm{Rq}}}{V_{\mathrm{Rd}}}$

[0054] For example only, the feed-forward values may be stored for different cases of reference active and reactive power by means of a lookup table in a digital signal processor within the control module.

Gate Signal Generation Module 1 (257)

[0055] Block 257 receives the reference voltage magnitude, V*.sub.s and the reference phase, *.sub.Vs as inputs. The grid synchronization signals are also provided as input. In an example implementation, block 257 may use a method such as Fundamental frequency modulation, Pulse width modulation or other such methods to convert the reference values into gate pulses.

Synchronization Module (258)

[0056] Block 258 provides input to the Gate signal generation modules 1 and 2. This input provides the information needed to synchronize the individual gate signals with a reference signal. This reference signal may be any accessible voltage on the power line that is not generated by the power control device. In an example implementation of this block, a phase locked loop may be tied to the voltage at terminal 1, given by {right arrow over (V.sub.1)}.

Reference Current Calculator 1 (259)

[0057] The reference active power to be dispatched from second terminal of the power control device also serves as the reference active power for active power flowing from the first terminal 1. This is in accordance with the fact that CMI-1 and CMI-2 individually do not consume or deliver any active power. The input to block 259 is the difference between the reference active power, P* and the sensed active power flowing through terminal 1, P.sub.s1. An example implementation of block 259 would include proportional and integral controllers or other commonly existing methods such as proportional and resonant controllers that force the input to close to zero. It should be appreciated that, at steady state, once the reference current is established, the power being drawn or delivered to the sending end is constant.

Sensed Power Calculator 3 (260)

[0058] Block 260 computes the Active power being drawn from terminal 1. P.sub.s1 represents the calculated active power. In an example implementation, P.sub.s1 may be calculated by solving for the expression below:

P.sub.s1=Re{{right arrow over (V.sub.1)}.{right arrow over (I.sub.c.sup.+)}}

[0059] where, {right arrow over (V.sub.1)} represents the voltage phasor at terminal 1 and {right arrow over (I.sub.c.sup.+)} represents the polar conjugate of the current phasor, I.sub.c.

Current Control Module 2 (261)

[0060] The input to block 261 is the reference current magnitude through terminal 1, I*.sub.c, current phasor through the power line, {right arrow over (I.sub.R)} and Voltage phasor at terminal 2, {right arrow over (V)}.sub.s. Based on these inputs, block 260 determines the required phase angle of the current through terminal 1. The output from block 261 contributes to the eventual reference current phase angle that ensures that current phasor through CMI-1, {right arrow over (I.sub.s)} is orthogonal to the voltage phasor, {right arrow over (V)}.sub.s. The steps involved in an example implementation are described below. Based on the information from {right arrow over (I.sub.R)} and {right arrow over (V.sub.S)}, the direction of {right arrow over (I.sub.S)} can be predicted using the following constraints:

{right arrow over (I.sub.R)}={right arrow over (I.sub.C)}+{right arrow over (I.sub.s)}and {right arrow over (V.sub.S)}.{right arrow over (I.sub.s)}=0;

[0061] Magnitude of current through terminal 1, I.sub.c is being controlled by blocks 258, 259 and 262. Using sensed current, I.sub.c, the phase of current through terminal 1 represented by I.sub.c is solved using the above constraints. For example only, these equations can be solved on a real time basis using a digital signal processor located in the control module.

Feed-Forward calculator 3 (258)

[0062] Block 258 generates the steady current magnitude, I.sub.cff that is added to the output generated by block 259 in order to generate the reference current magnitude I*.sub.c. For an example implementation, block 258 may consist of lookup tables for different nominal voltages and reference power levels.

Reference Phase Calculator 2 (263)

[0063] The input to block 263 is the difference between the output generated by block 261 and the measured phase of the current through terminal 1, I.sub.c. The role of block 263 is to reduce the error in input to close to zero. For an example implementation, block 263 may consist of Proportional and integral controllers or other forms of controllers such as proportional and resonant controllers.

Phase Modifier 2 (264)

[0064] Block 264 modifies the phase reference generated by block 263. V.sub.DC2 is an input that conveys information about some aspect of the DC link voltages of the M cascaded modules of CMI-2. V*.sub.DC2 provides a reference for the same. The output of block 264 generates a small change in the reference phase in order to account for the loss encountered in the devices due to the operation of the multiple modules in CMI-2. For an example implementation, the average DC voltage across all M modules of one phase of CMI-2 is used as the feedback. The nominal DC link voltage serves as the reference.

Reference Voltage Calculator 2 (265)

[0065] Block 265 receives the reference current magnitude and reference current phase information from blocks 262 and 263 respectively. The reference current calculator 2 provides an output signal that when vectorally added to phasors, {right arrow over (V)}.sub.1 and {right arrow over (V)}.sub.S provides the input to block 266. Thus, block 265 converts the current reference information to an equivalent voltage output. The output of block 265 compensates for any change in impedance of the sending end, any change in the sending end voltage and/or provide fast dynamic response to the overall system. An example implementation for block 265 may consist of a virtual impedance function that converts the current input to a voltage output. It may also involve frame transformation equations or co-ordinate transformation equations in order to provide a phasor voltage output.

Reference Voltage Calculator 3 (266)

[0066] Block 266 generates the reference voltage phasor for CMI-2. This block calculates the reference voltage phasor that needs to be developed across CMI-2. This is provided as a reference, {right arrow over (V*.sub.c)} to block 267. In and example implementation, block 266 may contain a variable gain, frame transformation equations and co-ordinate transformation equations to provide the output in a form understandable by the gate signal generation module 2.

Gate Signal Generation Module 2

[0067] This block receives the reference voltage phasor for CMI-2, {right arrow over (V*.sub.c)}. The grid synchronization signals are also provided as input. The output provides the gate pulses that drive the individual semiconductor devices in the CMI modules of CMI-2.

[0068] In an example implementation, this block may use a method such as Fundamental frequency modulation, Pulse width modulation or other such methods to convert the reference values into gate pulses.

[0069] The present invention has been described in an illustrative manner. It is to be understood that the terminology, which has been used, is intended to be in the nature of words of description rather than of limitation.

[0070] Many modifications and variations of the present invention are possible in light of the above teachings. Therefore, the present invention may be practiced other than as specifically described.