METAL-SEMICONDUCTOR-METAL TWO-DIMENSIONAL ELECTRON GAS VARACTOR AND METHOD OF MANUFACTURING THE SAME

Abstract

Disclosed are a metal-semiconductor-metal two-dimensional electron gas varactor (MSM-2DEG) and a method of manufacturing the same. There is provided an MSM-2DEG varactor having an asymmetric structure, which includes a first gate formed on a semiconductor layer, and a second gate spaced apart at a predetermined distance from the first gate and formed on the semiconductor layer, wherein the first gate and the second gate are different in shape and gate length.

Claims

1. A metal-semiconductor-metal two-dimensional electron gas (MSM-2DEG) varactor comprising: a first gate which is formed on a semiconductor layer; and a second gate which is spaced apart at a predetermined distance from the first gate and formed on the semiconductor layer, the first gate and the second gate being different in shape and gate length.

2. The MSM-2DEG varactor according to claim 1, wherein the first gate comprises a rectangular gate having a micron-scale gate length, and the second gate comprises a T-shaped gate having a nano-scale gate length.

3. The MSM-2DEG varactor according to claim 2, wherein the second gate comprises an upper end portion having a length which ranges from 300 nm to 1 m.

4. The MSM-2DEG varactor according to claim 2, wherein the second gate has a gate length which ranges from 50 nm to 500 nm.

5. The MSM-2DEG varactor according to claim 2, wherein the first gate and the second gate have a micron-scale gate width.

6. The MSM-2DEG varactor according to claim 1, wherein the first gate is configured to form an anode, and the second gate is configured to form a cathode.

7. The MSM-2DEG varactor according to claim 1, further comprising: a third gate which is formed on the semiconductor layer and symmetrical to the first gate with respect to the second gate.

8. The MSM-2DEG varactor according to claim 7, wherein the third gate has the same shape and the same gate length as those of the first gate.

9. The MSM-2DEG varactor according to claim 7, wherein the first gate and the third gate are configured to form anodes, and the second gate is configured to form a cathode.

10. A method of manufacturing an MSM-2DEG varactor, the method comprising: (A) forming a semiconductor layer on a growth substrate; (B) forming a first gate on the formed semiconductor layer; and (C) forming a second gate to be spaced apart from the first gate on the formed semiconductor layer, the first gate and the second gate being different in shape and gate length.

11. The method according to claim 10, wherein the first gate comprises a rectangular gate having a micron-scale gate length, and the second gate comprises a T-shaped gate having a nano-scale gate length.

12. The method according to claim 10, wherein the (B) comprises forming a third gate to be spaced apart from the first gate, together with the first gate, on the formed semiconductor layer, the first gate and the third gate are symmetrical to each other with respect to the second gate, and the third gate is different in shape and gate length from the second gate.

13. The method according to claim 12, wherein the third gate has the same shape and the same gate length as those of the first gate.

14. A method of manufacturing an MSM-2DEG varactor, the method comprising: (A) forming a semiconductor layer on a growth substrate; (B) forming a first gate on the formed semiconductor layer; and (C) forming a second gate and a third gate to be spaced apart from the first gate and symmetrical to each other with respect to the first gate on the formed semiconductor layer, the second gate and the third gate being different in shape and gate length from the first gate.

15. The method according to claim 14, wherein the third gate has the same shape and the same gate length as those of the second gate.

16. The method according to claim 14, wherein the first gate comprises a T-shaped gate having a nano-scale gate length, and the second gate comprises a rectangular gate having a micron-scale gate length.

17. The method according to claim 16, further comprising, in between the (B) and the (C), depositing a dielectric on a surface of the semiconductor layer; and etching the deposited dielectric to form the second gate and the third gate, wherein the dielectric deposited at lower opposite sides of the first gate is not etched in the etching of the deposited dielectric.

18. The method according to claim 17, wherein the (C) comprises forming the second gate and the third gate by a self-alignment process.

19. The method according to claim 10, wherein the (A) comprises: forming an electron cloud layer by growing a predetermined material; and etching opposite end portions of the electron cloud layer as much as a predetermined length by a mesa-etching method.

20. The method according to claim 14, wherein the (A) comprises: forming an electron cloud layer by growing a predetermined material; and etching opposite end portions of the electron cloud layer as much as a predetermined length by a mesa-etching method.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The above and other objects, features and advantages of the present disclosure will become more apparent to those of ordinary skill in the art by describing exemplary embodiments thereof in detail with reference to the accompanying drawings, in which:

[0032] FIG. 1 is a diagram of showing a metal-semiconductor-metal two-dimensional electron gas (MSM-2DEG) varactor according to one embodiment of the present disclosure;

[0033] FIG. 2 is a cross-sectional view of showing the MSM-2DEG varactor according to one embodiment of the present disclosure;

[0034] FIG. 3 is a plan view of showing the MSM-2DEG varactor according to one embodiment of the present disclosure;

[0035] FIG. 4 is a graph of showing a capacitance switching rate versus a cutoff frequency in the MSM-2DEG varactor according to one embodiment of the present disclosure as compared with the related art;

[0036] FIG. 5 is a graph of showing capacitance versus voltage in the MSM-2DEG varactor according to one embodiment of the present disclosure as compared with the related art;

[0037] FIG. 6 is a table of showing electric characteristics in the MSM-2DEG varactor according to one embodiment of the present disclosure as compared with the related art;

[0038] FIG. 7 is a flowchart of showing a method of manufacturing the MSM-2DEG varactor according to one embodiment of the present disclosure;

[0039] FIG. 8 is a flowchart of showing a method of manufacturing the MSM-2DEG varactor according to one embodiment of the present disclosure;

[0040] FIG. 9 is a flowchart of showing a method of manufacturing the MSM-2DEG varactor according to one embodiment of the present disclosure;

[0041] FIG. 10 is a schematic diagram corresponding to the flowchart of FIG. 9; and

[0042] FIG. 11 is a schematic diagram corresponding to the flowchart of FIG. 10.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

[0043] In this specification, terms first and/or second, etc. are only used to distinguish one element from another. In other words, the elements are not limited by these terms.

[0044] In this specification, terms include used for the elements, features and operations specify the presence of the elements, features and operations, and do not preclude the presence of one or more other elements, features, operations and their equivalents.

[0045] In this specification, the singular forms are intended to include the plural forms as well, unless the context clearly indicates otherwise. That is, the elements or the like stated in this specification may mean the presence or addition of one or more other elements.

[0046] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by a person having an ordinary skill in the artthose skilled in the artto which the present disclosure belongs.

[0047] It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined here.

[0048] Below, embodiments of the present disclosure will be described in detail with reference to FIGS. 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, and 11. However, it will be understood by those skilled in the art that the descriptions given in this specification with reference to the accompanying drawings are for illustrative purposes only since the present disclosure extends beyond these limited embodiments.

[0049] First, limitations in the related art will be described.

[0050] A conventional MSM-2DEG varactor includes a semiconductor layer, and two gates each having a nano-scale gate length. In this case, the gate may have one of a T shape or a rectangular shape. That is, the conventional MSM-2DEG varactor has a symmetric structure. In this case, the related art employs a method of decreasing the gate length in order to increase a cutoff frequency. According to this approach, a capacitance switching rate is lowered when the gate length is shorter than a predetermined length (100 nm), and it is thus difficult to raise the cutoff frequency in a terahertz domain up to a certain value or higher due to increase in metal-semiconductor interfacial resistance.

[0051] Next, with reference to FIGS. 1, 2, and 3, the MSM-2DEG varactor according to one embodiment of the present disclosure will be described.

[0052] FIG. 1 is a diagram of showing an MSM-2DEG varactor according to one embodiment of the present disclosure.

[0053] Referring to FIG. 1, the MSM-2DEG varactor according to this embodiment of the present disclosure may include a semiconductor layer 10, a first gate 20, and a second gate 30. The first gate 20 and the second gate 30 may be formed on the semiconductor layer 10. The first gate 20 and the second gate 30 may be different in shape. There may be a difference between a gate length R1 of the first gate 20 and a gate length T of the second gate 30. According to this embodiment, the MSM-2DEG varactor may have an asymmetric structure.

[0054] The first gate 20 may form an anode, and the second gate 30 may form a cathode. To minimize the gate resistance of the anode, the first gate 20 may have a rectangular shape and may have a micron-scale gate length R1. To minimize the gate resistance of the cathode, the second gate 30 may have a T shape and may have a nano-scale gate length T.

[0055] The semiconductor layer 10 may include a substrate, a nucleation layer, a buffer layer, a barrier layer, and a cap layer. The semiconductor layer 10 may have a heterostructure. The semiconductor layer 10 may include a material having a two-dimensional electron cloud layer. The semiconductor layer 10 may include GaN, GaAs, InP, etc. Preferably, the buffer layer may include GaN, and the barrier layer may be a Schottky barrier layer having a thickness of 22 nm and including Al.sub.0.24Ga.sub.0.76N. Preferably, the cap layer may have a thickness of 3 nm and include GaN.

[0056] FIG. 2 is a cross-sectional view of showing an MSM-2DEG varactor according to still another embodiment of the present disclosure, and FIG. 3 is a plan view of showing the MSM-2DEG varactor according to still another embodiment of the present disclosure.

[0057] Referring to FIG. 2 and FIG. 3, the MSM-2DEG varactor according to one embodiment of the present disclosure may include the semiconductor layer 10, the first gate 20, the second gate 30, and a third gate 40. The first gate 20, the second gate 30 and the third gate 40 may be formed on the semiconductor layer 10. The first gate 20 and the second gate 30 may be different in shape. There may be a difference between the gate length R1 of the first gate 20 and the gate length T of the second gate 30.

[0058] The third gate 40 may be formed on the semiconductor layer 10 and symmetrical to the first gate 20 with respect to the second gate 30. The third gate 40 may have the same shape as that of the first gate 20. A gate length R3 of the third gate 40 may be equal to the gate length R1 of the first gate 20. The MSM-2DEG varactor according to one embodiment of the present disclosure may have a balanced structure.

[0059] The first gate 20 and the third gate 40 may form the anodes, and the second gate 30 may form the cathode. To minimize the gate resistance of the anode, the first gate 20 may have a rectangular shape and may have a micron-scale gate length R1. To minimize the gate resistance of the cathode, the second gate 30 may have a T shape and may have a nano-scale gate length T.

[0060] It is preferable that a spacing distance D be made as short as possible as long as DC open state is maintained. Preferably, a length H of an upper end portion of the second gate 30 may range from 300 nm to 1 m. Preferably, the gate length T of the second gate 30 may range from 50 nm to 500 nm. Preferably, a gate height M1 of the first gate 20 and a gate height M3 of the third gate 40 may be equal to or greater than 300 nm. A gate width W may preferably have a micron-scale value, and may more preferably range from 15 m to 150 m to enhance the cutoff frequency.

[0061] Next, the effects of the MSM-2DEG varactor according to one embodiment of the present disclosure will be described with reference to FIGS. 4, 5, and 6.

[0062] FIG. 4 is a graph of showing a capacitance switching rate versus a cutoff frequency in the MSM-2DEG varactor according to one embodiment of the present disclosure as compared with the related art, FIG. 5 is a graph of showing capacitance versus voltage in the MSM-2DEG varactor according to one embodiment of the present disclosure as compared with the related art, and FIG. 6 is a table of showing electric characteristics in the MSM-2DEG varactor according to one embodiment of the present disclosure as compared with the related art.

[0063] Referring to FIG. 5, the MSM-2DEG varactor having the asymmetric structure or the balanced structure according to one embodiment of the present disclosure has higher capacitance at a zero bias voltage than the conventional MSM-2DEG varactor having the symmetric structure.

[0064] In the conventional MSM-2DEG varactor having the symmetric structure, the maximum capacitance at the zero bias voltage is determined based on two Schottky capacitances associated with series-connected two gates.

[0065] On the other hand, in the MSM-2DEG varactor having the asymmetric structure or the balanced structure, the maximum capacitance at the zero bias voltage is determined by one second gate 30, the Schottky capacitance of the second gate 30 is much smaller than the Schottky capacitance of the first gate 20.

[0066] Referring to FIG. 4 and FIG. 6, the cutoff frequency is defined as

[00001]$f_0=\frac{1}{2.Math..Math..Math.R_0.Math.C_0}.$

Further, Figure Of Merit (FOM) is defined as

[00002]$f_0\frac{c_{\max }}{c_{\min }}.$

This value refers to the cutoff frequency when the capacitance switching rate is 1, and means the maximum value of the cutoff frequency to be effectively raised by a certain technique for raising the cutoff frequency of the MSM-2DEG varactor.

[0067] In the conventional MSM-2DEG varactor having the symmetrical structure, FOM has a value of 1.900.07 [THz].

[0068] On the other hand, the MSM-2DEG varactor having the asymmetric structure or the balanced structure according to one embodiment of the present disclosure have the FOM values of 2.900.13 [THz] and 4.060.20 [THz], respectively. That is, according to the present disclosure, there are advantages of providing the MSM-2DEG varactor, which has a higher cutoff frequency in a terahertz domain than the conventional one while having a significant capacitance switching rate.

[0069] Next, referring to FIGS. 7, 8, 9, 10, and 11, a method of manufacturing the MSM-2DEG varactor according to one embodiment of the present disclosure will be described.

[0070] FIG. 7 is a flowchart of showing a method of manufacturing the MSM-2DEG varactor according to one embodiment of the present disclosure.

[0071] Referring to FIG. 7, the method of manufacturing the MSM-2DEG varactor according to this embodiment includes operations of forming the semiconductor layer 10 on a growth substrate 50 (S10), forming the first gate 20 on the formed semiconductor layer 10 (S20), and forming the second gate 30 to be spaced apart from the first gate 20 on the semiconductor layer 10 (S30).

[0072] By the manufacturing method according to the present embodiment, the MSM-2DEG varactor may have the asymmetric structure.

[0073] FIG. 8 is a flowchart of showing a method of manufacturing the MSM-2DEG varactor according to another embodiment of the present disclosure, and FIG. 10 is a schematic diagram corresponding to the flowchart of FIG. 9.

[0074] Referring to FIG. 8 and FIG. 10, the method of manufacturing the MSM-2DEG varactor according to this embodiment includes operations of forming the semiconductor layer 10 on the growth substrate 50 (S10), forming the first gate 20 and the third gate 40 as the first and second gates on the formed semiconductor layer 10 (S20), and forming the second gate 30 as the third gate to be spaced apart from the first gate 20 and the third gate 40 on the formed semiconductor layer 10 (S40). In this case, the first gate 20 and the third gate 40 may be symmetrical to each other with respect to the second gate 30.

[0075] By the manufacturing method according to the present embodiment, the MSM-2DEG varactor may have the balanced structure.

[0076] FIG. 9 is a flowchart of showing a method of manufacturing the MSM-2DEG varactor according to still another embodiment of the present disclosure, and FIG. 11 is a schematic diagram corresponding to the flowchart of FIG. 10.

[0077] Referring to FIG. 9 and FIG. 11, the method of manufacturing the MSM-2DEG varactor according to this embodiment includes operations of forming the semiconductor layer 10 on the growth substrate 50 (S10), forming the second gate 30 as the first gate on the formed semiconductor layer 10 (S50), depositing a dielectric 60 on a surface of the semiconductor layer 10 (S60), etching the deposited dielectric 60 in order to prepare a place where the first gate 20 and the third gate 40 will be formed (S70), and forming the first gate 20 and the third gate 40 as the second and third gates to be spaced part from the second gate 30 and symmetrical to each other with respect to the second gate 30 by a predetermined process on the semiconductor layer 10 (S80). In this case, the predetermined process may be a self-alignment process.

[0078] If the first gate 20 and the third gate 40 are formed by the self-alignment process, the spacing distance D may be further reduced as long as the DC open is maintained, thereby improving the performance of the manufactured MSM-2DEG varactor.

[0079] The method of etching the deposited dielectric 60 may be achieved by dry etching.

[0080] The first gate 20 and the third gate 40 may be different in shape from the second gate 30.

[0081] Further, the MSM-2DEG varactor manufactured by the method according to this embodiment may have the balanced structure.

[0082] The second gate 30 may be a gate having a T shape. In this case, the second gate 30 may be formed before the first gate 20 and the third gate 40 in order to use the self-alignment process.

[0083] Further, in this case, the dielectrics deposited at the lower opposite sides of the T-shaped gate may not be etched while the deposited dielectric 60 is etched.

[0084] In the manufacturing methods according to the foregoing embodiments, the operation S10 of forming the semiconductor layer 10 on the growth substrate 50 may include forming an electron cloud layer by growing a predetermined material on the growth substrate 50, and etching the opposite ends of the electron cloud layer as much as a predetermined length by a mesa-etching method. The predetermined material may be a material having a two-dimensional electron cloud layer.

[0085] The predetermined length may be a length suitable for forming the first gate 20 and the second gate 30 on a surface of the non-etched electron cloud layer. Alternatively, the predetermined length may be a length suitable for forming the first gate 20, the second gate 30, and the third gate 40 on the surface of the non-etched electron cloud layer.

[0086] In the MSM-2DEG varactor according to one embodiment of the present disclosure, the T-shaped gate having a nano-scale gate length and the rectangular gate having a micron-scale gate length are used to form the MSM-2DEG varactor, and therefore the cutoff frequency thereof can be raised higher than that of the related art, thereby having effects of performing the capacitor switching by using the MSM-2DEG varactor in a higher terahertz frequency domain.

[0087] Further, in the method of manufacturing the MSM-2DEG varactor according to another embodiment of the present disclosure, the spacing distance between the gates becomes narrower by the self-alignment process, thereby having effects of manufacturing the MSM-2DEG varactor having a higher cutoff frequency.

[0088] Although some exemplary embodiments of the present disclosure are described, changes, substitutes and equivalents can be made without departing from the scope of the present disclosure.

[0089] Further, it will be appreciated that there are many alternatives to the embodiments of the MSM-2DEG varactor according to the present disclosure. Accordingly, the appended claims should be construed as involving all the changes, substitutes and equivalents which belong to the spirit and scope of the present disclosure.