OSCILLATOR CIRCUITS

Abstract

A method of operating an oscillator circuit comprising a resonator is provided. The method comprises maintaining a resonance of the resonator by a) connecting the resonator to an input voltage (V.sub.buf) for a first pulse period to charge the resonator only partially towards the input voltage (V.sub.buf); b) connecting the resonator to a second, lower, voltage for a second pulse period to discharge the resonator at least partially; and repeating steps a) and b) at a rate corresponding to the resonance of the resonator and with a phase corresponding to the resonance of the resonator, so as to maintain the resonance of the resonator.

Claims

1. A method of operating an oscillator circuit comprising a resonator, the method comprising maintaining a resonance of the resonator by: a) connecting the resonator to an input voltage for a first pulse period to charge the resonator only partially towards the input voltage; b) connecting the resonator to a second, lower, voltage for a second pulse period to discharge the resonator at least partially; and repeating steps a) and b) at a rate corresponding to the resonance of the resonator and with a phase corresponding to the resonance of the resonator, so as to maintain the resonance of the resonator.

2. The method as claimed in claim 1, wherein the resonator comprises a piezoelectric material.

3. The method as claimed in claim 1, comprising charging the resonator in the first pulse period to less than 80% of the input voltage.

4. The method as claimed in claim 1, wherein the input voltage comprises a buffer voltage provided by a buffer circuit.

5. The method as claimed in claim 4, wherein the buffer voltage comprises a reference voltage generated by a reference voltage portion of the buffer circuit, or an offset version of a reference voltage generated by a reference voltage portion of the buffer circuit.

6. The method as claimed in claim 5, wherein the reference voltage is lower than a supply voltage of the oscillator circuit.

7. The method as claimed in claim 5, wherein the reference voltage portion comprises an adjustable bias resistor arranged to offset the reference voltage.

8. The method as claimed in claim 5, wherein the buffer circuit comprises a buffer portion comprising a source follower transistor that has its gate terminal connected to the reference voltage or an offset version of the reference voltage, and its drain terminal connected to a supply voltage of the oscillator circuit.

9. The method as claimed in claim 8, wherein one or more component transistors of the voltage reference portion and the buffer portion of the buffer circuit are matched.

10. The method as claimed in claim 1, comprising connecting a buffer capacitor to the resonator during the first pulse period.

11. The method as claimed in claim 10, comprising recharging the buffer capacitor between the first pulse periods.

12. The method as claimed in claim 1, comprising timing the first and second pulse periods using a timing circuit, the timing circuit comprising a feedback loop arranged to synchronise the first and second pulse periods with the resonance of the resonator.

13. The method as claimed in claim 12, wherein the timing circuit comprises a phase locked loop or a delay locked loop.

14. The method as claimed in claim 1, comprising providing an initial resonance signal to start oscillations of the oscillator circuit from an initial zero oscillation state.

15. An oscillator circuit comprising a resonator, wherein the oscillator circuit is arranged to maintain a resonance of the resonator by: a) connecting the resonator to an input voltage for a first pulse period to charge the resonator only partially towards the input voltage; b) connecting the resonator to a second, lower, voltage for a second pulse period to discharge the resonator at least partially; and repeating steps a) and b) at a rate corresponding to the resonance of the resonator and with a phase corresponding to the resonance of the resonator, so as to maintain the resonance of the resonator.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0037] One or more non-limiting examples will now be described, by way of example only, and with reference to the accompanying figures in which:

[0038] FIG. 1 is a schematic diagram of a pulse injection crystal oscillator circuit according to the prior art;

[0039] FIG. 2 is a timing diagram illustrating the operation of the pulse injection crystal oscillator circuit shown in FIG. 1;

[0040] FIG. 3 is a schematic diagram of a pulse injection crystal oscillator circuit according to an embodiment of the invention;

[0041] FIG. 4 is a timing diagram illustrating the operation of the pulse injection crystal oscillator circuit shown in FIG. 3;

[0042] FIG. 5 is a schematic diagram of a pulse injection crystal oscillator circuit according to another embodiment of the invention;

[0043] FIG. 6 is a timing diagram illustrating the operation of the pulse injection crystal oscillator circuit shown in FIG. 5; and

[0044] FIG. 7 is a schematic diagram of the buffer circuit of the pulse injection crystal oscillator circuit shown in FIG. 5.

DETAILED DESCRIPTION

[0045] FIG. 3 shows a pulse injection crystal oscillator circuit 102 that comprises a piezoelectric crystal resonator 104, a buffer circuit 107, and a timing circuit 110.

[0046] The operation of the pulse injection crystal oscillator circuit 102 will now be described with reference to the timing diagram shown in FIG. 4. In use, the timing circuit 110 alternately connects the crystal resonator 104 to the buffer circuit 107 using a high switch 109 and to a ground rail 108 using a low switch 111, at a rate that corresponds to a resonance of the crystal resonator 104, and with a phase corresponding to the resonance of the resonator.

[0047] As shown in FIG. 4, the voltage of the crystal oscillator 104, measured at node X.sub.0 oscillates at the frequency of the resonance of the crystal resonator 104. The timing circuit 110 is locked to the resonance of the crystal resonator 104 (e.g. using a phase locked loop).

[0048] At a first time t.sub.1, the timing circuit 110 connects the crystal resonator 104 to a buffer voltage V.sub.BUF generated by the buffer circuit 107 for a first pulse period 112. During the first pulse period 112, the current provided by the buffer circuit 107 charges the crystal resonator 104 partially, but not completely, towards the buffer voltage V.sub.BUF (e.g. to between 35% and 62% of V.sub.BUF). Because the crystal resonator 104 is only partially charged towards the buffer voltage V.sub.BUF, the charging current provided by the buffer circuit 107 can be relatively small.

[0049] At a second time t.sub.2, which is half of the resonant period of the crystal resonator 104 after t.sub.1, the timing circuit 110 connects the crystal resonator 104 to the ground rail 108 for a second pulse period 114. This quickly discharges the crystal resonator 104. Whilst in the example shown in FIG. 4 the crystal resonator 104 is completely discharged in the second pulse period 114, this is not essential. FIG. 4 shows the first and second pulse periods 112, 114 as equal, but again this is not essential. For instance, the second pulse period 114 may be shorter than the first pulse period 112.

[0050] The duration of the first pulse period 112, and the current bandwidth of the buffer circuit 107 are chosen to ensure that the charge delivered to the crystal resonator 104 is sufficient to keep the oscillation going, whilst minimising the physical size of the buffer 107 and the overall power consumption of the oscillator circuit 102.

[0051] The output X.sub.i of the crystal resonator 104 is connected to the timing circuit 110, which controls the process to repeat at a rate corresponding to the resonance of the crystal resonator 104 and phase-locked with the resonance of the crystal resonator 104 (i.e. with the first pules period 112 occurring at or close to the peak of the oscillation waveform, and the second pulse period 114 occurring at or close to the bottom of the oscillation waveform). This maintains the oscillation indefinitely. In this example the first and second pulse periods 112, 114 repeat at a rate slightly above the inherent resonant frequency of the crystal resonator 104. The timing circuit 110 may, for instance, comprise a phase locked loop (PLL).

[0052] Another embodiment of the pulse injection crystal oscillator circuit 102 is shown in FIG. 5. In this embodiment the pulse injection crystal oscillator circuit 102 additionally comprises a buffer capacitor 116. Although it is shown separately in FIG. 5, the buffer capacitor 116 may be considered to form part of the buffer circuit 107.

[0053] The operation of the pulse injection crystal oscillator circuit 102 shown in FIG. 5 will now be described with reference to the timing diagram shown in FIG. 6.

[0054] As with the previous embodiment, the voltage of the crystal oscillator 104, measured at node X.sub.0 oscillates at the frequency of the resonance of the crystal resonator 104. The timing circuit 110 is locked to the resonance of the crystal resonator 104 (e.g. because it comprises a phase locked loop).

[0055] At a first time t.sub.1, the timing circuit 110 closes the high switch 109 to connect the crystal resonator 104 to a buffer voltage V.sub.BUF generated by the buffer circuit 107 for a first pulse period 112. Charge stored in the buffer capacitor 116 is quickly delivered to the crystal resonator 104, which quickly raises the voltage at node X.sub.0 partially towards the buffer voltage V.sub.BUF. FIG. 6 shows that after this initial rise the buffer circuit 107 continues to charge the crystal resonator 104 towards the buffer voltage at a slower rate. At the end of the first pulse period 112 the timing circuit 110 opens the high switch 109 to disconnect the crystal resonator 104 from the buffer voltage V.sub.BUF, and the buffer circuit 107 begins to gradually recharge the buffer capacitor 116 back to the buffer voltage V.sub.BUF.

[0056] At a second time t.sub.2, which is half of the resonant period of the crystal resonator 104 after t.sub.1, the timing circuit 110 closes the low switch 111 to connect the crystal resonator 104 to the ground rail 108 for a second pulse period 114. This quickly discharges the crystal resonator 104. Whilst in the example shown in FIG. 4 the crystal resonator 104 is completely discharged in the second pulse period 114, this is not essential. FIG. 4 shows the first and second pulse periods 112, 114 as equal, but again this is not essential. For instance, the second pulse period 114 may be shorter than the first pulse period 112.

[0057] In this embodiment, the use of the buffer capacitor 116 allows charge to be quickly delivered to the crystal resonator 104 in the first pulse period 112. Although this is not shown in FIG. 6, this may allow the duration of the first pulse period 112 to be reduced compared to the embodiment described with reference to FIG. 4. This can further reduce the overall power use of the oscillator circuit 102.

[0058] Furthermore, the peak current delivery required of the buffer circuit 107 can be further reduced in this embodiment because it does useful work charging the buffer capacitor 116 throughout the entire resonant cycle before the first pulse period 112 occurs again. FIG. 6 shows how the buffer circuit 107 gradually recharges the buffer capacitor 116. This may allow the physical size and cost of the buffer circuit 107 to be even further reduced.

[0059] FIG. 7 shows a detailed schematic diagram of the buffer circuit 107. The buffer circuit 107 comprises an input voltage rail 158 (which is at voltage V.sub.DD) and a ground rail 108 (at voltage V.sub.SS). The buffer circuit 107 comprises three portions: a current/voltage reference portion 152, a buffer portion 154 and a switching portion 156. Some or all of the portions 152, 154, 156 may be physically separate (e.g. all the portions of the buffer circuit 107 may not be located on a single integrated circuit).

[0060] The current/voltage reference portion 152 comprises a startup circuit 162, transistors M.sub.1-M.sub.4, a reference resistor 166 (with resistance R.sub.REF), and a trim resistor 168 (with resistance R.sub.TRIM). The current/voltage reference portion 152 is configured as a beta-multiplier circuit.

[0061] The buffer portion 154 comprises a source follower transistor M.sub.5 and a biasing transistor M.sub.6.

[0062] The switching portion 156 comprises the high switch 109, which comprises a first switching transistor M.sub.7 arranged to connect the crystal resonator 104 to the buffer voltage V.sub.BUF, and the low switch 111, which comprises a second switching transistor M.sub.8 arranged to connect the crystal resonator 104 to the ground rail 108.

[0063] The buffer circuit 107 further comprises the buffer capacitor 116, connected between the source of the first switching transistor M.sub.7 (i.e. the output of the buffer portion 154) and the ground rail 108. The first and second switching transistors M.sub.7, M.sub.8 are controlled by pulses from the timing circuit 110.

[0064] In use, the current/voltage reference portion 152 generates a reference voltage V.sub.REF. The bias current generated by the current/voltage reference portion is set by the relative sizing of the transistors M.sub.3-4 and the resistance R.sub.REF of the reference resistor 166. By choosing the size of the transistors M1-4 and resistor 166 correctly, the reference voltage V.sub.REF may be made to be temperature independent The startup circuit 162 ensures that the current/voltage reference portion produces the reference voltage V.sub.REF rather than an alternative steady-state where zero current flows.

[0065] In use, the buffer portion 154 operates as a voltage buffer. By matching the transistors M.sub.3 and M.sub.4 of the current/voltage reference portion 152 with the source follower transistor M.sub.5 and the biasing transistor M.sub.6 respectively, V.sub.REF is copied to V.sub.BUF, offset by the voltage drop across R.sub.TRIM.

[0066] The configuration of the buffer circuit 107 ensures that V.sub.BUF is generated with acceptable PVT robustness (i.e. the buffer voltage is largely independent of variations in the manufacturing process, the supply voltage V.sub.SS and the temperature). By configuring the buffer portion 154 as a source follower connected directly to the voltage supply rail 158, it can supply more current than its DC bias when V.sub.BUF drops (i.e. acting as an AB-like amplifier), meaning that the bias current consumed by the buffer can be further reduced. In one example in which the oscillator circuit 102 oscillates at approximately 32 kHz, the bias current in each branch of the buffer circuit 107 is about 2.5 nA, meaning that the whole circuit uses only 7.5 nA of bias current.

[0067] While the invention has been described in detail in connection with only a limited number of embodiments, it should be readily understood that the invention is not limited to such disclosed embodiments. Rather, the invention can be modified to incorporate any number of variations, alterations, substitutions or equivalent arrangements not heretofore described, but which are commensurate with the scope of the invention. Additionally, while various embodiments of the invention have been described, it is to be understood that aspects of the invention may include only some of the described embodiments. Accordingly, the invention is not to be seen as limited by the foregoing description, but is only limited by the scope of the appended claims.