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WIDE BANDWIDTH ENVELOPE TRACKING INTEGRATED CIRCUIT

20220360227 · 2022-11-10

    Inventors

    Cpc classification

    International classification

    Abstract

    An envelope tracking (ET) integrated circuit (ETIC) is provided. The ETIC is configured to generate an ET voltage for amplifying a radio frequency (RF) signal modulated for communication in multiple time intervals. In embodiments disclosed herein, the ETIC is self-contained to generate an ET target voltage based on a power envelope of the RF signal and to generate the ET voltage based on the ET target voltage. Given that the RF signal may be modulated at a very high modulation bandwidth, the ETIC can be configured to modify the ET target voltage in each of the time intervals to thereby cause the ET voltage to be adapted on a per time interval basis. As a result, the ET voltage can better track the power envelope of the RF signal in each of the time intervals to help improve operating efficiency of a power amplifier apparatus that employs the ETIC.

    Claims

    1. An envelope tracking (ET) integrated circuit (ETIC) comprising: an ET voltage circuit configured to generate an ET voltage based on an ET target voltage for amplifying a radio frequency (RF) signal modulated for transmission in a plurality of time intervals; a target voltage generation circuit configured to generate the ET target voltage based on a power envelope of the RF signal; and a target voltage processing circuit configured to: receive the ET voltage from the target voltage generation circuit; modify the ET target voltage in each of the plurality of time intervals to generate a modified ET target voltage in response to the RF signal being modulated in a modulation bandwidth higher than or equal to a bandwidth threshold; and provide the modified ET target voltage to the ET voltage circuit as the ET target voltage to thereby cause the ET voltage circuit to generate the ET voltage based on the modified ET target voltage.

    2. The ETIC of claim 1, wherein the target voltage processing circuit is further configured to pass the ET voltage directly to the ET voltage circuit in response to the modulation bandwidth being lower than the bandwidth threshold.

    3. The ETIC of claim 1, wherein each of the plurality of time intervals has a duration of an orthogonal frequency division multiplexing (OFDM) symbol.

    4. The ETIC of claim 1, wherein the target voltage processing circuit is further configured to determine the modulation bandwidth based on a bandwidth indication signal.

    5. The ETIC of claim 1, wherein the target voltage generation circuit comprises: an amplitude detector circuit configured to determine a time-variant amplitude of the RF signal; and an analog lookup table (LUT) circuit configured to generate the ET target voltage based on the detected time-variant amplitude.

    6. The ETIC of claim 1, wherein the ET voltage circuit comprises: a voltage amplifier configured to: generate an initial ET voltage based on the modified ET target voltage when the modulation bandwidth is higher than or equal to the bandwidth threshold; and generate the initial ET voltage based on the ET target voltage when the modulation bandwidth is lower than the bandwidth threshold; and an offset capacitor configured to raise the initial ET voltage by an offset voltage to thereby generate the ET voltage.

    7. The ETIC of claim 6, further comprising a switcher circuit configured to modulate the offset voltage based on a battery voltage and the ET target voltage.

    8. The ETIC of claim 7, wherein the switcher circuit comprises: a multi-level charge pump (MCP) configured to generate a low-frequency voltage as a function of the battery voltage in accordance with a duty cycle determined based on the ET target voltage; and a power inductor configured to induce a low-frequency current to charge the offset capacitor to the offset voltage.

    9. The ETIC of claim 1, wherein the target voltage processing circuit comprises a control circuit configured to: determine the modulation bandwidth; cause the target voltage processing circuit to modify the ET target voltage in each of the plurality of time intervals to generate the modified ET target voltage in response to the modulation bandwidth being higher than or equal to the bandwidth threshold; and cause the target voltage processing circuit not to modify the ET target voltage in response to the modulation bandwidth being lower than the bandwidth threshold.

    10. The ETIC of claim 9, wherein the target voltage processing circuit further comprises a voltage modifier circuit configured to modify the ET target voltage in each of the plurality of time intervals to generate the modified ET target voltage.

    11. The ETIC of claim 10, wherein, in each of the plurality of time intervals, the voltage modifier circuit is further configured to: increase the modified ET target voltage at each peak of the ET target voltage; and maintain the modified ET target voltage of each peak of the ET target voltage.

    12. The ETIC of claim 11, wherein, in each of the plurality of time intervals, the voltage modifier circuit is further configured to decay the modified ET target voltage from a peak level of the modified ET target voltage in an immediately preceding one of the plurality of time intervals.

    13. The ETIC of claim 11, wherein the voltage modifier circuit is further configured to decay the modified ET target voltage at a start of each of the plurality of time intervals.

    14. The ETIC of claim 12, wherein, in each of the plurality of time intervals, the voltage modifier circuit is further configured to decay the modified ET target voltage until the modified ET target voltage intersects with the ET target voltage.

    15. The ETIC of claim 12, wherein, in each of the plurality of time intervals, the voltage modifier circuit is further configured to decay the modified ET target voltage to a predefined minimum level in each of the plurality of time intervals independent of the ET target voltage.

    16. A power amplifier apparatus comprising: an envelope tracking (ET) integrated circuit (ETIC) comprising: an ET voltage circuit configured to generate an ET voltage based on an ET target voltage for amplifying a radio frequency (RF) signal modulated for transmission in a plurality of time intervals; a target voltage generation circuit configured to generate the ET target voltage based on a power envelope of the RF signal; and a target voltage processing circuit configured to: receive the ET voltage from the target voltage generation circuit; modify the ET target voltage in each of the plurality of time intervals to generate a modified ET target voltage in response to the RF signal being modulated in a modulation bandwidth higher than or equal to a bandwidth threshold; and provide the modified ET target voltage to the ET voltage circuit as the ET target voltage to thereby cause the ET voltage circuit to generate the ET voltage based on the modified ET target voltage; and at least one high-bandwidth power amplifier circuit configured to amplify the RF signal modulated in the modulation bandwidth higher than or equal to the bandwidth threshold.

    17. The power amplifier apparatus of claim 16, further comprising a transceiver circuit configured to generate the RF signal in the modulation bandwidth higher than or equal to the bandwidth threshold.

    18. The power amplifier apparatus of claim 16, further comprising at least one low-bandwidth power amplifier circuit configured to amplify the RF signal modulated in the modulation bandwidth lower than the bandwidth threshold, wherein the target voltage processing circuit is further configured to pass the ET voltage directly to the ET voltage circuit in response to the modulation bandwidth being lower than the bandwidth threshold.

    19. The power amplifier apparatus of claim 18, wherein the transceiver circuit is configured to generate the RF signal in the modulation bandwidth lower than the bandwidth threshold.

    20. The power amplifier apparatus of claim 19, wherein the transceiver circuit is further configured to provide a bandwidth indication signal to indicate the modulation bandwidth to the target voltage processing circuit.

    Description

    BRIEF DESCRIPTION OF THE DRAWING FIGURES

    [0013] The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure.

    [0014] FIG. 1 is a schematic diagram of an exemplary envelope tracking (ET) integrated circuit (ETIC) provided in a power amplifier apparatus and configured according to embodiments of the present disclosure to generate an ET voltage for amplifying a radio frequency (RF) signal modulated for transmission in a multiple time intervals;

    [0015] FIG. 2 is a schematic diagram of the ETIC in FIG. 1 configured according to an embodiment of the present disclosure to generate the ET voltage across a wide modulation bandwidth; and

    [0016] FIGS. 3 and 4 are diagrams providing exemplary illustrations of embodiments that may be implemented by the ETIC 10 in FIGS. 1 and 2 to modify the ET target voltage in each of the multiple time intervals.

    DETAILED DESCRIPTION

    [0017] The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

    [0018] It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

    [0019] It will be understood that when an element such as a layer, region, or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being “over” or extending “over” another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly over” or extending “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.

    [0020] Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.

    [0021] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and/or “including” when used herein specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

    [0022] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

    [0023] Embodiments of the disclosure relate to an envelope tracking (ET) integrated circuit (ETIC). The ETIC is configured to generate an ET voltage for amplifying a radio frequency (RF) signal modulated for communication in multiple time intervals. In embodiments disclosed herein, the ETIC is self-contained to generate an ET target voltage based on a power envelope of the RF signal and to generate the ET voltage based on the ET target voltage. Given that the RF signal may be modulated at a very high modulation bandwidth (e.g., 200 MHz), the ETIC can be configured to modify the ET target voltage in each of the time intervals to thereby cause the ET voltage to be adapted on a per time interval basis. As a result, the ET voltage can better track the power envelope of the RF signal in each of the time intervals to help improve operating efficiency of a power amplifier apparatus that employs the ETIC.

    [0024] In this regard, FIG. 1 is a schematic diagram of an exemplary ETIC 10 provided in a power amplifier apparatus 12 and configured according to embodiments of the present disclosure to generate an ET voltage V.sub.CC for amplifying an RF signal 14 modulated for transmission in multiple time intervals 16(1)-16(N). Herein, a modulation bandwidth is referred to as a higher (or wide) modulation bandwidth when the modulation bandwidth is higher than or equal to a bandwidth threshold (e.g., 200 MHz), or a lower (or narrow) modulation bandwidth when the modulation bandwidth is lower than the bandwidth threshold. In a non-limiting example, each of the time intervals 16(1)-16(N) has a duration of an orthogonal frequency division multiplexing (OFDM) symbol, which is inversely related to the modulation bandwidth of the RF signal 14.

    [0025] In an embodiment, the power amplifier apparatus 12 includes a transceiver circuit 18 that is configured to generate and modulate the RF signal 14 in the time intervals 16(1)-16(N) based on any subcarrier spacing (SCS) configuration as listed in Table 1 above. In this regard, the RF signal 14 can be so generated to have the higher modulation bandwidth or the lower modulation bandwidth.

    [0026] The transceiver circuit 18 is configured to provide the RF signal 14 to the ETIC and a signal processing circuit 20. In a non-limiting example, the transceiver circuit 18 can provide the RF signal 14 to the ETIC 10 and the signal processing circuit 20 in an intermediate frequency (IF).

    [0027] The signal processing circuit 20 may be configured to upconvert the RF signal 14 from the IF to an appropriate carrier frequency. In an embodiment, the signal processing circuit 20 provides the RF signal 14 to at least one high-bandwidth power amplifier circuit 22H (denoted as “HBW PA”) when the RF signal 14 is modulated in the higher modulation bandwidth, and to at least one low-bandwidth power amplifier circuit 22L (denoted as “LBW PA”) when the RF signal 14 is modulated in the lower modulation bandwidth. In this regard, in a non-limiting example, only one of the high-bandwidth power amplifier circuit 22H and the low-bandwidth power amplifier circuit 22L can be active at a given time, depending on the modulation bandwidth of the RF signal 14.

    [0028] The ETIC 10 includes a pair of voltage outputs VOUT.sub.A and VOUT.sub.B that are coupled to the high-bandwidth power amplifier circuit 22H and the low-bandwidth power amplifier circuit 22L, respectively. In embodiments disclosed herein, the ETIC 10 is configured to provide the ET voltage V.sub.CC to the voltage output VOUT.sub.A when the RF signal 14 is modulated in the higher modulation bandwidth, and to the voltage output VOUT.sub.B when the RF signal 14 is modulated in the lower modulation bandwidth. In a non-limiting example, the transceiver circuit 18 can provide a bandwidth indication signal 24 to thereby indicate to the ETIC 10 the modulation bandwidth of the RF signal 14.

    [0029] The ETIC 10 is configured to generate the ET voltage V.sub.CC based on a power envelope 26 associated with the RF signal 14. Notably, the power envelope 26 can vary (rise or fall) rapidly during each of the time intervals 16(1)-16(N). On the other hand, the high-bandwidth power amplifier circuit 22H and the low-bandwidth power amplifier circuit 22L are each operating as a current source to the ETIC 10. As a result, any misalignment between the ET voltage V.sub.CC and the power envelope 26 will not only reduce operation efficiency and/or linearity of the high-bandwidth power amplifier circuit 22H and the low-bandwidth power amplifier circuit 22L, but also cause some degree of distortion (e.g., amplitude clipping) to the RF signal 14. Moreover, the degree of distortion caused by the high-bandwidth power amplifier circuit 22H can be far more severe due to the higher modulation bandwidth of the RF signal 14.

    [0030] As such, it is desirable to make sure the ETIC 10 can adapt the ET voltage V.sub.CC during each of the time intervals 16(1)-16(N) when the RF signal 14 is modulated in the higher modulation bandwidth. In contrast, since the distortion may be less severe when the RF signal 14 is modulated in the lower modulation bandwidth, it is also desirable that the ETIC 10 does not adapt the ET voltage V.sub.CC during each of the time intervals 16(1)-16(N) to help reduce computational complexity of the ETIC 10. Moreover, it is desirable for the ETIC 10 to generate the ET voltage V.sub.CC for the lower modulation bandwidth and the higher modulation bandwidth based on a same hardware architecture.

    [0031] In this regard, FIG. 2 is a schematic diagram of the ETIC 10 in FIG. 1 configured according to an embodiment of the present disclosure to generate the ET voltage V.sub.CC across a wide modulation bandwidth. Common elements between FIGS. 1 and 2 are shown therein with common element numbers and will not be re-described herein.

    [0032] In an embodiment, the ETIC 10 is self-contained to include a target voltage generation circuit 28, a target voltage processing circuit 30, and an ET voltage circuit 32. The target voltage generation circuit 28 is configured to generate an ET target voltage V.sub.TGT based on the power envelope 26 associated with the RF signal 14. The target voltage processing circuit 30 is configured to modify the ET target voltage V.sub.TGT in each of the time intervals 16(1)-16(N) to generate a modified ET target voltage V.sub.TGT-SST. More specifically, the target voltage processing circuit 30 is configured to modify the ET target voltage V.sub.TGT and provide the modified ET target voltage V.sub.TGT-SST to the ET voltage circuit 32 only when the RF signal 14 is modulated in the higher modulation bandwidth. In case the RF signal 14 is modulated in the lower modulation bandwidth, the target voltage processing circuit 30 will simply output the ET target voltage V.sub.TGT to the ET voltage circuit 32. As a result, the ET voltage circuit 32 can generate the ET voltage V.sub.CC based on the modified ET target voltage V.sub.TGT-SST when the RF signal 14 is modulated in the higher modulation bandwidth or based on the ET target voltage V.sub.TGT when the RF signal 14 is modulated in the lower modulation bandwidth. As a result, the ET voltage V.sub.CC can better track the power envelope 26 of the RF signal 14 across the wide modulation bandwidth to help improve operating efficiency and linearity of the high-bandwidth power amplifier circuit 22H and the low-bandwidth power amplifier circuit 22L, and to reduce distortion to the RF signal 14.

    [0033] In an embodiment, the target voltage generation circuit 28 includes an amplitude detector circuit 34 and an analog lookup table (LUT) circuit 36. The amplitude detector circuit 34 is configured to determine a time-variant amplitude 38 based on the power envelope 26 of the RF signal 14. The analog LUT circuit 36 is configured to generate the ET target voltage V.sub.TGT based on the time-variant amplitude 38. In a non-limiting example, the analog LUT circuit 36 can include an analog LUT (not shown) that correlates the time-variant amplitude 38 with the ET target voltage V.sub.TGT. Accordingly, the analog LUT circuit 36 is configured to generate the ET target voltage V.sub.TGT based on the correlation established in the analog LUT.

    [0034] In an embodiment, the ET voltage circuit 32 includes a voltage amplifier 40 and an offset capacitor C.sub.OFF. The voltage amplifier 40 is configured to generate an initial ET voltage V.sub.AMP based on the modified ET voltage V.sub.TGT-SST when the RF signal 14 is modulated in the higher modulation bandwidth. In contrast, when the RF signal 14 is modulated in the lower modulation bandwidth, the voltage amplifier 40 is configured to generate the initial ET voltage V.sub.AMP based on the modified ET voltage V.sub.TGT. The offset capacitor C.sub.OFF is configured to raise the initial ET voltage V.sub.AMP by an offset voltage V.sub.OFF to thereby generate the ET voltage V.sub.CC (V.sub.CC=V.sub.AMP+V.sub.OFF). Notably, by providing the offset capacitor C.sub.OFF to raise the initial ET voltage V.sub.AMP, the voltage amplifier 40 can generate the initial ET voltage V.sub.AMP at a lower level than the ET voltage V.sub.CC, thus helping to improve headroom and efficiency of the voltage amplifier 40.

    [0035] In an embodiment, the ETIC 10 includes a switcher circuit 42 configured to modulate the offset voltage V.sub.OFF based on a battery voltage V.sub.BAT and the ET target voltage V.sub.TGT. In a non-limiting example, the switcher circuit 42 can include a multi-level charge pump (MCP) 44 and a power inductor 46. The MCP 44 is configured to generate a low-frequency voltage VDC as a function of the battery voltage V.sub.BAT and in accordance with a duty cycle. In a non-limiting example, the MCP 44 can generate the low-frequency voltage VDC at 0×V.sub.BAT (0 V), 1×V.sub.BAT, or 2×V.sub.BAT based on the duty cycle. For example, if the battery voltage V.sub.BAT is 5 V and the duty cycle is 30% at 0×V.sub.BAT (0 V), 30% at 1×V.sub.BAT, and 40% at 2×V.sub.BAT, the MCP 44 will then generate the low-frequency voltage VDC at 5.5 V (0x30%+5x30%+10x40%). The power inductor 46 is configured to induce a low-frequency current IDC to charge the offset capacitor C.sub.OFF to the offset voltage V.sub.OFF. In the embodiment disclosed herein, the duty cycle can be determined based on the ET target voltage V.sub.TGT. Accordingly, the offset voltage V.sub.OFF can be modulated based on the ET target voltage V.sub.TGT and therefore the ET voltage V.sub.CC.

    [0036] In an embodiment, the ET voltage circuit 32 includes a bypass switch S.sub.BPS coupled to an output node 48 of the voltage amplifier 40 and a ground (GND). The bypass switch S.sub.BPS is closed to thereby allow the low-frequency current IDC to charge the offset capacitor C.sub.OFF toward the offset voltage V.sub.OFF and opened when the offset voltage V.sub.OFF is reached.

    [0037] The ET voltage circuit 32 can also include a feedback circuit 50 (denoted as “FB”). The feedback circuit 50 can be configured to provide a feedback of the ET voltage V.sub.CC to the voltage amplifier 40 to thereby make the ET voltage circuit 32 a closed-loop ET voltage circuit.

    [0038] In an embodiment, the target voltage processing circuit 30 includes a control circuit 52 and a voltage modifier circuit 54. The control circuit 52 may be configured to determine the modulation bandwidth of the RF signal 14 based on, for example, the bandwidth indication signal 24. Accordingly, the control circuit 52 may determine the duty cycle for the MCP 44 based on the determined modulation bandwidth and/or the feedback of the ET voltage V.sub.CC.

    [0039] The control circuit 52 can be further configured to cause the target voltage processing circuit 30 to modify the ET target voltage V.sub.TGT in each of the time intervals 16(1)-16(N) to generate the modified ET target voltage V.sub.TGT-SST in response to the modulation bandwidth being higher than or equal to the bandwidth threshold. The control circuit 52 can also be configured to cause the target voltage processing circuit 30 not to modify the ET target voltage V.sub.TGT in response to the modulation bandwidth being lower than the bandwidth threshold.

    [0040] In a non-limiting example, the target voltage processing circuit 30 can include a target voltage output switch SW (e.g., a single-pole double-throw switch). In response to determining whether the modulation bandwidth is higher than or equal to the bandwidth threshold, the control circuit 52 can activate the voltage modifier circuit 54 to generate the modified ET target voltage V.sub.TGT-SST and couple the target voltage output switch SW to node A to thereby provide the modified ET target voltage V.sub.TGT-SST to the ET voltage circuit 32. In contrast, in response to determining that the modulation bandwidth is lower than the bandwidth threshold, the control circuit 52 can deactivate the voltage modifier circuit 54 and couple the target voltage output switch SW to node B to thereby provide the ET target voltage V.sub.TGT to the ET voltage circuit 32.

    [0041] In an embodiment, the ETIC 10 may also include an equalizer circuit 56 (denoted as “EQ”). The equalizer circuit 56 can be configured to equalize the modified ET target voltage V.sub.TGT-SST or the ET target voltage V.sub.TGT based on a transfer function (e.g., a second-order complex-zero transfer function) to help offset a trace inductance that can exist between the voltage output VOUT.sub.A and the high-bandwidth power amplifier circuit 22H and the voltage output VOUT.sub.B and the low-bandwidth power amplifier circuit 22L.

    [0042] The ETIC 10 may also include a switch circuit 58. The switch circuit 58 can be controlled, for example by the control circuit 52, to couple the ET voltage V.sub.CC to the voltage output VOUT.sub.A when the RF signal 14 is modulated in the higher modulation bandwidth or to the voltage output VOUT.sub.B when the RF signal 14 is modulated in the lower modulation bandwidth.

    [0043] The voltage modifier circuit 54 can be configured to modify the ET target voltage V.sub.TGT in each of the time intervals 16(1)-16(N) in accordance with any embodiments as discussed next in FIGS. 3 and 4. In examples discussed herein, the time intervals 16(1)-16(N) are assumed to correspond to an OFDM symbol. Specifically, FIGS. 3 and 4 each illustrate three consecutive OFDM symbols S.sub.N−1, S.sub.N, and S.sub.N+1, which can correspond to any three consecutive ones of the time intervals 16(1)-16(N).

    [0044] FIGS. 3 and 4 are diagrams providing exemplary illustrations of embodiments that may be implemented by the voltage modifier circuit 54 in the ETIC 10 in FIGS. 1 and 2 to modify the ET target voltage in each of the time intervals 16(1)-16(N). In the embodiment, in each of the OFDM symbols S.sub.N−1, S.sub.N, and S.sub.N+1, the voltage modifier circuit 54 is configured to increase the modified ET target voltage V.sub.TGT-SST at each peak of the ET target voltage V.sub.TGT. For example, in the OFDM symbol S.sub.N−1, the ET target voltage V.sub.TGT reaches multiple peaks at times T.sub.0, T.sub.1, T.sub.2, and T.sub.3, respectively. Accordingly, the voltage modifier circuit 54 increases the modified ET target voltage V.sub.TGT-SST at times T.sub.0, T.sub.1, T.sub.2, and T.sub.3, respectively. In a non-limiting example, the voltage modifier circuit 54 can be configured to increase the modified ET target voltage V.sub.TGT-SST along a rising edge of the ET target voltage V.sub.TGT at times T.sub.0, T.sub.1, T.sub.2, and T.sub.3. In contrast, when the ET target voltage V.sub.TGT is off the peaks (e.g., decreases) between times T.sub.0-T.sub.1, T.sub.1-T.sub.2, and T.sub.2-T.sub.3, the voltage modifier circuit 54 will maintain the modified ET target voltage V.sub.TGT-SST, as opposed to decreasing the modified ET target voltage V.sub.TGT-SST along with the decrease of the ET target voltage V.sub.TGT.

    [0045] To prevent the modified ET target voltage V.sub.TGT-SST from continuing to going up, the voltage modifier circuit 54 can be configured to decay the modified ET target voltage V.sub.TGT-SST from a peak level of the modified ET target voltage V.sub.TGT-SST set in an immediately preceding one of the OFDM symbols S.sub.N−1, S.sub.N, and S.sub.N+1. For example, the voltage modifier circuit 54 can be configured to decay the modified ET target voltage V.sub.TGT-SST in the OFDM symbol S.sub.N from the peak level set during the OFDM symbol S.sub.N−1, to decay the modified ET target voltage V.sub.TGT-SST in the OFDM symbol S.sub.N+1 from the peak level set during the OFDM symbol S.sub.N, and so on. In an embodiment, the voltage modifier circuit 54 can decay the modified ET target voltage V.sub.TGT-SST at a start of each of the OFDM symbols S.sub.N−1, S.sub.N, and S.sub.N+1.

    [0046] In an embodiment, as shown in FIG. 3, the voltage modifier circuit 54 can decay the modified ET target voltage V.sub.TGT-SST until the modified ET target voltage V.sub.TGT-SST intersects the ET target voltage V.sub.TGT. More specifically, the modified ET target voltage V.sub.TGT-SST should intersect the ET target voltage V.sub.TGT at a level (e.g., at times T.sub.4 and T.sub.5) that is lower than the peak level of the modified ET target voltage V.sub.TGT-SST in the immediately preceding one of the OFDM symbols S.sub.N−1, S.sub.N, and S.sub.N+1.

    [0047] In another embodiment, as shown in FIG. 4, the voltage modifier circuit 54 can decay the modified ET target voltage V.sub.TGT-SST to a predefined minimum level V.sub.TGT-SST-MIN in each of the OFDM symbols S.sub.N−1, S.sub.N, and S.sub.N+1 independent of the ET target voltage V.sub.TGT. For example, the modified ET target voltage V.sub.TGT-SST is decayed until intersecting with the predefined minimum level V.sub.TGT-SST-MIN at times T.sub.4 and T.sub.5.

    [0048] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.