Silicon integrated, out-of-plane heat flux thermoelectric generator

Abstract

An enhanced electrical yield is achieved with an integrated thermoelectric generator (iTEG) of out-of-plane heat flux configuration on a substrate wafer having hill-top junction metal contacts and valley-bottom junction metal contacts joining juxtaposed ends of segments, alternately p-doped and n-doped, of defined thin film lines of segments of a polycrystalline semiconductor, extending over inclined opposite flanks of hills of a material of lower thermal conductivity than the thermal conductivity of the thermoelectrically active polycrystalline semiconductor, by keeping void the valleys spaces (V) among the hills and delimited at the top by a planar electrically non conductive cover with metal bond pads defined over the coupling surface, adapted to bond with respective hill-top junction metal contacts. The junction metal contacts have a cross sectional profile of low aspect ratio, with two arms or wings overlapping the juxtaposed end portions of the segments. Preferably the inner void is evacuated upon packaging the iTEG.

Claims

1. An integrated thermoelectric generator of out-of-plane heat flux configuration, comprising: a substrate wafer, a layer of a single material deposited on said substrate wafer, forming hills and valleys all made of said single material, thin film lines of segments of a polycrystalline semiconductor, alternately p-doped and n-doped, entirely defined on and extending on inclined opposite flanks of said hills of said layer made of said single material; said material having a lower thermal conductivity than the thermal conductivity of said polycrystalline semiconductor, hill-top junction metal contacts and valley-bottom junction metal contacts, deposited on and joining juxtaposed ends of segments, alternately p-doped and n-doped, of said defined thin film lines of segments of a polycrystalline semiconductor, wherein all said valleys among said hills are void spaces (V) delimited from above by a planar electrically non-conductive cover having metal bond pads, defined over a coupling surface of the planar cover, bonded with said respective hill-top junction metal contacts, wherein said single material, of which all hills and said valleys of said layer are made, is selected from the group consisting of silicon oxide, silicon nitride, deposited oxides of enhanced resistance to heat conduction, nanomesh structures of phononic material, and superlattices of nanoscale thin film silicon, wherein said hill top junction metal contacts have a cross sectional profile with two arms or wings overlapping juxtaposed end portions of a p-doped and of an n-doped segment, respectively, of a defined line (L) of segments of polycrystalline semiconductor.

2. The thermoelectric generator of claim 1, wherein side gaps between the substrate wafer and said planar cover are occluded so as to permanently seal said void spaces (V).

3. The thermoelectric generator of claim 1, wherein side gaps between the substrate wafer and said planar cover are occluded so as said void spaces (V) are permanently sealed under vacuum.

4. The thermoelectric generator of claim 1, wherein said planar cover is a wafer similar to the substrate wafer, and has a dielectric film over the coupling surface that electrically insulates from one another said metal bond pads defined thereon.

5. The thermoelectric generator of claim 4, wherein said substrate wafer or said cover wafer are thinned or ultra-thinned silicon wafers.

6. The thermoelectric generator of claim 5, wherein said planar cover is a silicon wafer similar to the substrate wafer.

7. The thermoelectric generator of claim 5, wherein the substrate silicon wafer and the planar cover silicon wafer are micro-machined wafers bonded together.

8. The thermoelectric generator of claim 1, wherein said metal contacts are of aluminum, copper, silver or alloys thereof.

9. The thermoelectric generator of claim 1, wherein electrical contact of said overlapping metal contact arms with the polycrystalline semiconductor thin film takes place via an interfacing multi-layer comprising a film of a silicide selected from the group consisting of TiSi.sub.2, WSi.sub.2, MoSi.sub.2, PtSi.sub.2 and CoSi.sub.2.

10. The thermoelectric generator of claim 1, wherein electrical contact of said overlapping metal contact arms with the polycrystalline semiconductor thin film takes place via an interfacing multi-layer comprising an intermediate film of a refractory metal selected from the group consisting of W, Ti, Ta and a film of titanium nitride in contact with the metal.

11. The thermoelectric generator of claim 1, wherein said hills are regularly spaced along parallel lines orthogonal to said lines of segments of polycrystalline semiconductor and have a truncated rectangular pyramid shape or a trapezoidal cross section along one axis and straight sides or flanks orthogonal to it.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a cross sectional view of the elementary cell of an integrated Z-device according to a basic embodiment of this disclosure.

(2) FIG. 2 is a fragmentary, three dimensional cross sectional view showing two lines of elementary cells of the integrated Z-device structure.

(3) FIG. 3 shows a possible layout of parallel conductive lines of elementary cells constituting an integrated TEG module of a string of a number of cells in electrical series with connection pads to circuit.

(4) FIG. 4 is a three dimensional view of an arrangement of the conductive parts of the integrated cells in series showing the flow path of electrical current generated by the integrated TEG device under a temperature difference between hot hill top metal junctions and cold valley bottom metal junctions.

DETAILED DESCRIPTION OF EMBODIMENTS

(5) With reference to FIG. 1 and FIG. 2, a silicon wafer 1 is used as substrate for fabricating thereon the novel Z-device structure of an integrated TEG of out-of-plane (orthogonal) heat flux type.

(6) Commercially available silicon wafers of any size and having a thickness generally not exceeding 675 micrometers (?m) may be used.

(7) A dielectric base layer 2 of substantially uniform thickness that may be generally comprised between 1 nanometer (nm) and 1 micrometer (?m), preferably of about 10 nm, provides a necessary bottom electrical insulation without introducing a significant thermal resistance.

(8) According to well established techniques of micro-machining processing, arrangement of spaced hills 3 of a relatively low thermal conductivity material such as, for example, of thick oxide, thermally grown or deposited over unmasked areas of a firstly grown base layer 2, up to a height that generally may be comprised between 0.1 and 50 ?m. The typical inclined flanks of hills 3 define valleys there between, the substantially planar bottom of which generally may have a width comprised between 0.1 and 100 ?m, most preferably between 0.2 and 50 ?m, similarly to the width of the top of the hills 3.

(9) Alternatively, the hills 3 may be defined starting from a layer of deposited oxide or other material such as silicon nitride, through a succession of masking and etching steps, under controlled isotropic etching conditions, in order to slant the walls of the progressively etched valleys toward a substantially flat bottom by an angle of inclination from the base plane that preferably is comprised between 45 and 85 degrees.

(10) LPCVD silicon oxide, deposited with varying amounts of phosphorous and/or hydrogen impurities and specific processing and post processing conditions promoting structural disorder (re: Y. S. Ju and K. E. Goodson,Process-dependent thermal transport properties of silicon-dioxide films deposited using low-pressure chemical vapor deposition, AIP Journal of Applied Physics, Volume 85, Number 10, 7130-7134) is also an effective material with which hills 3 of enhanced resistance to heat conduction may be formed over the oxidized surface of the substrate wafer 1.

(11) Yet another alternative material with which hills 3 of enhanced resistance to heat conduction with two suitably inclined opposite sides may be formed over an oxidized surface of a substrate wafer is the family of nanomesh structures of phononic silicon (re:Reduction of thermal conductivity in phononic nanomesh structures by Jen-Kan Yu, S. Mitrovic, D. Tham, J. Varghese and J. R. Heath, Nature Nanotechnology, Vol. 5, October 2010, ?2010 Macmillan Publishers Lim.).

(12) The hills material should have a low thermal conductivity, significantly lower than the thermal conductivity of the material of the p-type and n-type legs of conductive material supported thereon, in order to further penalize by-pass paths of heat conduction flow alternative to the paths of productive heat conduction along the polycrystalline doped semiconductor thin film segments or legs defined over opposite slanted surfaces of the truncated rectangular pyramid shaped hills 3 or of hills with a trapezoidal cross section along one axis and straight sides or flanks orthogonal to it.

(13) Examples of suitable materials of lower thermal conductivity than the thermal conductivity of a thermoelectrically active polycrystalline semiconductor and their respective heat conduction coefficients are reported in the following table.

(14) TABLE-US-00001 Material Thickness [nm] Conductivity [W m.sup.?1 K.sup.1] Thermal SiO2 >250 ~1.2 SiO2 30-50 0.82 ? 0.02 (PECVD@300 C.) SiO2 90-180 1.00 ? 0.10 (PECVD@300 C.) SiO2 >200 ~1.2 (Bulk) (PECVD@300 C.) SiNx 20-40 0.55 ? 0.05 (PECVD@300 C.) SiNx 60-120 0.65 ? 0.05 (PECVD@300 C.) SiNx 180 ~1.45 (APCVD@900 C.)

(15) Hills 3 of a superlattice of nanoscale thin films of phononic silicon realized over a dielectric base layer on the surface of the substrate is another alternative capable of markedly reducing the thermal conductivity of the hills 3 of the integrated TEG structure.

(16) Parallel lines of defined tracts or segments of alternately p-doped and n-doped, 4 and 5, respectively, of a polycrystalline semiconductor material such as, for example, doped Si or SiGe, deposited in form of a thin film of substantially uniform thickness over the bottom isolation dielectric 2 and the spaced hills 3, constitute the two legs of thermoelectric material that electrically connect a junction at the valley bottom to the two adjacent junctions on top of the hills 3 (i.e. a unit or elementary cell of a Z-device structure). The deposited doped polycrystalline silicon layer of the segments 4 and 5 may have thickness, generally comprised between 10 and 1000 nm, but may even be as thick as one or more micrometers, depending on contemplated applications, scaling of the elementary cell structure, properties of the polycrystalline semiconductor material used and design choices of the integrated TEG.

(17) Physically, the cold and hot junctions, respectively at valley bottoms and at hill-tops or vice versa, are both constituted by metal contacts of low aspect ratio, respectively 6 and 7, electrically bridging an interruption gap between the defined end of a p-doped segment or leg 5 and the defined end of a n-doped thermoelectric segment or leg 4 of polycrystalline thin-film semiconductor, in order to avoid formation of p-n junctions along the string of elementary integration modules or cells in series of an electrically conductive line (chain) of cells.

(18) The deposited metal layer of the junction metal contacts 6 and 7 that extend over and in electrical contact with the end portions of the two segments 4 and 5 of polycrystalline semiconductor, for a good part of their portions laying onto the substantially planar valley bottoms and hill-tops, may have thickness ranging from about 0.1 to about 5 ?m.

(19) The cross sectional view of the drawing well represents the characteristic Z profile of the conductive legs 4 and 5 of thermo-electrically active material of the elementary cell.

(20) Preferably, there is a multi-layer interfacing between the metal overlapping the polycrystalline semiconductor thin film to control the electrical interface resistance between the metal and the semiconductor materials thereat and eventually disproportionate electrical conductivity versus thermal conductivity for reducing heat conduction toward the metallic bulk of the metal contacts, namely, the valley bottom contacts 6 and the hill-top contacts 7. As depicted in the enlargement lens, an effective interfacing multi-layer may comprise a 1-50 nm film 6a of a silicide belonging to the group: TiSi.sub.2, WSi.sub.2, MoSi.sub.2, PtSi.sub.2 and CoSi.sub.2, in contact with the polycrystalline doped semiconductor, an intermediate 1-10 nm thick film 6b of W or Ti and a 5-30 nm thick film 6c of TiN in contact with the metal layer 6, 7 of Al or of AlSi alloy or copper.

(21) According to a preferred embodiment of the novel integrated out-of-plane TEG structure, the void valley spaces among parallel lines or other arrangement of spaced hills 3 are closed at the top by a second wafer 8, provided with a thin dielectric layer 9 formed over a surface of the wafer to render it electrically non-conductive, and over which are then defined metal bond pads 10, adapted to bond with respective hill-top metal contacts 7 according to one of the many flip-chip bonding techniques, preferably using an aligned-bonding technique of thermo-compressive metal-to-metal bonding CuCu,WW, TiTi . . . etc., with or without diffusion layers, after a CMP planarization, or via plasma bonding (YOx/YOx), PECVD SiO2-SiO2, benzocyclobutene (BCB) to BCB bonding. Hybrid bonding techniques such as BCB and a variety of polymers or polymides, metal layers such Ti films and inter-metallic compounds (IMCs), CuSn Solid-Liquid-Interdiffusion (SLID) bonding, AuSn or AuIn eutectic bonding, may alternately be used as well as anodic bonding or micro-bump stacking.

(22) Also the so-called smart-cut processing or the layer transfer technology Smart Stacking? of Soitec, described in U.S. Pat. No. 5,374,564, may be used.

(23) Flip-chip aligned bonding, may be carried out on whole processed wafers, from which TEG device dices are successively cut to be packaged, or alternatively on cut dices thereof Generally, depending on the specific application, aligned bonding for realizing the TEG devices of this disclosure may be carried out in chip-to-chip, chip-to-wafer, wafer-to-wafer mode or according to chip-on-wafer-on-substrate or chip-on-chip-on-substrate approaches.

(24) Preferably, both the top and bottom wafers may be subjected to a backside thinning process aiming to reduce the thickness of commercial wafers, after devices manufacturing, including mechanical or chemical treatments, such as mechanical grinding, dry polishing, chemical-mechanical grinding, spin etching chemical-mechanical polishing and plasma dry etching. The aim is to reduce the original thickness to less than 100 ?m or to ultrathin values of less than 40 ?m. Thinning of the wafers reduces overall thermal resistance of the integrated out-of-plane TEG structure and makes it amenable to be deployed in next generation 3D integrated circuit.

(25) A fragmentary, three dimensional cross sectional sketch, showing the features of two lines L of elementary cells of the integrated Z-device structure may be observed in FIG. 2.

(26) The manner in which parallel electrically conductive lines of defined tracts or segments of alternately p-doped and n-doped, 4 and 5, of a semiconductor material, joined by valley-bottom and hill-top junction metal contacts 6 and 7 are created, orthogonally to array lines of spaced hills 3, may be immediately recognized.

(27) The width of the conductive lines L may be generally comprised between 0.1 and 500 ?m, more preferably between 0.5 and 10 ?m.

(28) A plurality of lines L of microcells are normally connected in electrical series, for example in an arrangement of a number of adjacently integrated parallel lines. FIG. 3 shows an exemplary layout of the electrically conductive parts of five parallel lines L of elementary cells, for constituting an integrated TEG module composed of a string of cells in electrical series corresponding to the sum of the number of cells of all the lines L terminating with connection pads A and B.

(29) Connection of the adjacent ends of two lines L is realized by defining lateral metal connections 6, i.e. defining by masking and selective etching step a secondly deposited metal layer, after having removed a firstly deposited metal layer for filling the gap space between the opposed ends of the polycrystalline semiconductor legs 4 and 5 from planar surfaces.

(30) In the tri-dimensional view of the arrangement of the conductive parts of the cells in series of FIG. 4, arrow heads describe the flow path of electrical current generated by the integrated TEG device under a temperature difference between hot hill-top metal junctions 7 and cold valley-bottom metal junctions 6.

(31) Of course, the DC voltage produced at the terminals A and B corresponds to the sum of the DC voltage developed by every elementary series connected cell of the string.

(32) A TEG device may include numerous modularly integrated multi-cell TEGs, each requiring two pads for connecting to one or several external circuits harvesting or exploiting the generated electrical power according to application needs. In order for one or several series/parallel networks of the plurality of monolithically integrated TEGs of a packaged device to be externally organized, the device must account for two pins for each individual integrated TEG. Therefore, an appropriate multi-TEG layout of monolithic integration, besides providing for the desired number of individually integrated TEGs must be compatible with the maximum number of pins that the packaged device may have.

(33) Alternatively, the finished TEG device may have few output pin pairs or even be a two-pin device by choosing to maximize serialization in order to achieve a large open-circuit output voltage.